TW508735B - A method to create a controllable and reproducible dual copper damascene structure - Google Patents
A method to create a controllable and reproducible dual copper damascene structure Download PDFInfo
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508735508735
五、發明說明(1) 發明背景: 發明範疇: 此發明與積體電路元件製造相關,特別的是它是—種 可以在雙嵌入(dual damascene)結構中降低碟狀凹陷 (dishing)及腐姓效應之方法。 相關技術說明: 在半導體積體電路製造中’普遍利用接觸f(c〇ntact )或介層孔(via)去連接不同的金屬層而形成内連線金屬層 結構。首先第一步驟先形成第一層或最底層之内連線金^ 層,然後第一層覆蓋於其上。第一層金屬層通常與晶圓基 底之主動區接觸,但並不限於此種接觸,第一層亦可與導 體接觸,而與其它元件形成一更大的多晶片結^。而^下 金屬層藉由二層中間之開口窗之金屬而導通,之前技術著 重於先形成第一層之内連線金屬層,接下來第二層覆蓋於 其上,此種技術必須在晶圓基底上已有主動區形^,而這 些主動區元件包含了雙載子電㈣,金 體(M0SFET),摻雜區域盥复它开杜柄、息々认 # ^ ^ 人/、八匕兀件週邊之輸入輸出端内連 去4 線金屬層表面可能被一絕緣層所覆蓋,★ 者疋基底先Λ化層,在此氧化層之上,用傳统微号 光學技術將内連線金屬層及開口窗、^ ι> 0Θ Μ ^ 固 因案疋義於其上。3 成開口 ®之疋義後,可能再覆上一 ,加強金屬之附著能力,戍者再/黏:層(glUe layer ),防止在後續製程中,=加t 一層阻障層咖心] 材科進入或從基底擴散出來。段 508735 五、發明說明(2) — - · 障層有不同的材料,例如··鈦/氮化鈦:鎢,鈦鎢合金/ 鈦,或鈦鎢氮化物,氮化矽,鈕,鉬等。在製作第一層金 屬内連線之最後階段是開口窗需充填金屬,一般是用/呂: 鎢或銅等材質。材質的選擇依據線寬,開口窗之縱橫比( aspect ratio)及表面平面度之需要而定。 /由於製作内連線金屬層之金屬導線有一些限制且容易 衍士些問題,近來在製程應用上改採銅,它具有低電阻 丄高^電致遷移能力^:^⑽⑽丨訂…⑻及減少應力產生 二,等優點。但銅亦有一些製程上的缺點,在二氧化矽及 含氧高分子中易於擴散。這使得在高溫製程中,銅擴散進 ^聚醯亞胺化合物(P〇lyimide),造成銅與氧的結合,而 形成嚴重的腐蝕現象。此種現象導致了附著能力的降低, 剝,,空洞及元件的不良,若銅擴散進入二氧化矽層,-將 使得介電層導通並降低二氧化矽之介電強&,因此二埒 ::層是必須的。氮化矽(silic〇n nitride)是阻障層 1 斤材料之一,然而氮化矽介電常數比二氧化矽高,二 氮化矽之應用。 礙了 、由於銅在反應性離子蝕刻(RIE)製程上非常難蝕 =以採用化學機械研磨方法,為了研磨銅在高速率下=, ^有刮傷金屬導線,研磨液中藉由提高對銅蝕刻之比且 讓鋼蝕刻速率增加,但增加此材料,卻造成了等向性 j,埋入銅線因此被钮刻,產生碟狀凹陷之現象。另、餘 氣長上的困難是銅對氧的敏感度,阻礙了銅在内連個 之發展’因為在微影製程曝完光後,將光罩圖案轉移’^ ^ 至晶V. Description of the invention (1) Background of the invention: The scope of the invention: This invention is related to the manufacture of integrated circuit components, and in particular it is a type that can reduce dishing and rotten names in a dual damascene structure. Effect method. Related technical description: In the fabrication of semiconductor integrated circuits, it is common to use contact f (conntact) or vias to connect different metal layers to form an interconnect metal layer structure. First, in the first step, a first layer or a bottom-most interconnecting gold layer is formed, and then the first layer covers it. The first metal layer is usually in contact with the active area of the wafer substrate, but it is not limited to this contact. The first layer can also be in contact with the conductor and form a larger multi-wafer junction with other components. The lower metal layer is conducted by the metal of the open window in the middle of the second layer. The previous technology focused on forming the first interconnecting metal layer and then the second layer covering it. This technology must be used in the crystal. There are already active regions on a circular substrate ^, and these active region elements include a double-electrode electron beam, a gold body (M0SFET), and a doped region that contains the open-cell handle, and the rest of the body # ^ ^ The surface of the 4-wire metal layer connected to the input and output ends of the element may be covered by an insulating layer. ★ The substrate is first Λ-layered, and on top of this oxide layer, the interconnecting metal is traditionally micro-optical optical technology. Layer and open window, ^ ι > 0Θ Μ ^ Gu Yin case is defined on it. 3 After the opening of the opening ®, it may be overlaid to strengthen the metal's adhesion ability, and then re / adhesive: glUe layer, to prevent the subsequent process, = add a layer of barrier layer coffee Branch enters or diffuses from the base. Paragraph 508735 V. Description of the invention (2) —-· The barrier layer has different materials, such as · titanium / titanium nitride: tungsten, titanium tungsten alloy / titanium, or titanium tungsten nitride, silicon nitride, button, molybdenum, etc. . In the final stage of making the first layer of metal interconnects, the opening window needs to be filled with metal, which is usually made of / Lu: tungsten or copper. The choice of material depends on the requirements of line width, aspect ratio of the open window and surface flatness. / Because there are some limitations in the production of metal wires for interconnecting metal layers and it is easy to cause problems, recently, copper has been changed to process applications. It has low resistance ^ high ^ electromigration ability ^: ^ ⑽⑽ order ... ⑻ and Reduced stress produces two advantages. However, copper also has some process shortcomings, and it is easy to diffuse in silicon dioxide and oxygen-containing polymers. This makes it possible for copper to diffuse into polyimide compounds during high-temperature processes, resulting in a combination of copper and oxygen, resulting in severe corrosion. This phenomenon leads to a reduction in adhesion, peeling, voids, and component failure. If copper diffuses into the silicon dioxide layer,-it will make the dielectric layer conductive and reduce the dielectric strength of the silicon dioxide & :: layer is required. Silicon nitride is one of the materials of the barrier layer, but the dielectric constant of silicon nitride is higher than that of silicon dioxide, which is the application of silicon nitride. Obstructed, because copper is very difficult to etch in the reactive ion etching (RIE) process = to use chemical mechanical polishing method, in order to grind copper at a high rate =, ^ There are scratches on the metal wires, by improving the copper The etching ratio increases the etching rate of steel, but increasing this material results in isotropic j. The buried copper wire is thus engraved and a dish-like depression occurs. In addition, the difficulty in the remaining gas length is the sensitivity of copper to oxygen, which hinders the development of copper interconnects. 'Because the photomask process is completed, the photomask pattern is transferred' ^ ^ to crystal
五 、發明說明(3) 片上’光阻必須藉由在含 銅製程不易製作。 、衣兄中加熱去除,因而使得 目刖業界廣泛採用單嵌入山 ,這是由於在毫微米超大型積體電^製,來製作鋼導線 (Plug)必須蝕刻的非常深,乾蝕刻命敢入結構之插塞 最近已有廠商使用銅作為傳導金屬線;;法滿足這需要。 以氧半導體(c_ ☆層金㈣ 早瓜入m構,首先在表面形成一 常指的是晶圓石夕基底,然後使用像屬=,此表面通 沉積内介電層(Intra Uvel Dielectl:ie 相沉積技術 化矽Si〇2,在介電層表面利用像離’如二乳 線渠溝arench)姓刻出來。幻生離子餘刻技術將導 再利用化學氣相沉積或金屬熱流法 將内介電層表面平坦化後,=成Ϊ = 、、、。構。早期早肷入結構使用反應性離子敍刻來作平坦化製 ,而如今化學機械研磨法已廣泛取而代之。 單嵌入製程的延伸為雙嵌入製程,藉由介電材料如二 氣化矽上有數千個開口窗,用來作金屬線和介層孔的連接 ’在同一時間將金屬充填在這些開口窗内。單嵌入結構是 個在絕緣層或介電層作一些渠溝形成内連線的銅製程; 雙嵌入結構則是一多重内連線製程,除了像單後入結構中 的渠溝外,亦形成連接的介層孔。雙嵌入製程大致^三類 :1)先連續沉積三個介電層,中間層為蝕刻中止層,此中 止層可以為S i N,上下二層則用二氧化矽。沉積完這三層 508735 利用微 層,而 方式一樣產生三層 至中止 準,然 五、發明說明(4) 介電層後, 刻穿透這 層上,蝕刻 層圖案作對 ,先沉積第 案轉移至晶 ,最後才將 雙嵌入 溝與介層孔 遭遇一些難 刻速率,造 屬線剖面不 緣則較淺。 製程難製作 ,金及銀, 深度,但卻 用在多晶秒 雙欲入 物。先前文 合物在化學 於欽化合物 銅較軟,研 程,會造成 :’形成介層,然後蝕 金二ί中止層。2)另一種 =溝圖案成形在介電 圖案則利用已形成的金屬 :次步驟沉積三層介電層 止層,然後將介層孔圖 ,再將介電層沉積於其上 片上’ 導線渠 結構是 同時製 題,由 成内連 均勻。 由於一 ,而内 雖然化 不易沉 及鶴的 製程使 章所提 機械研 比較硬 磨速率 表面上 影技術 金屬層 介電層 層,而 後飯刻 氧化石夕 曝完光 溝I虫刻 單嵌入 作,減 於薄膜 線接點 在晶片 些元件 連線所 學氣相 積這些 沉積, 用銅作 之碟狀 磨製程 且具有 快,因 產生碟 轉換圖 圖案則 ,先將 介層孔 。3 )分 及I虫刻 後I虫刻 出來。 結構之 少製程 沉積的 深度難 中心有 特徵尺 使用之 沉積技 金屬, 這些材 金屬導 凹陷及 中,研 化學鈍 此若銅 狀凹陷 改良, 步驟。 不均勻 以控制 較深的 寸有較 金屬材 術可以 所以化 料之阻 線,阻 腐蝕現 磨速率 性,所 和鈦化 及腐名虫 因為它 但是它 及要精 ’使得 剖面, 小的縱 質,一 製作出 學氣相 抗都比 障層用 象是由 的不同 以研磨 合物在 現象。 允許導線渠 在製程上也 確的控制蝕 在晶片上金 靠近晶片邊 橫比,濺鑛 般如銘,銅 較深的穿透 沉積一般應 紹銅為高。 欽及欽化合 於銅及鈦化 所導致。由 速率慢;而 同一研磨製V. Description of the invention (3) On-chip photoresist must not be easily produced by copper-containing processes. The heat removal in the clothes brother, so that the eyes of the industry widely used single-embedded mountains, this is due to the nano-scale large-scale integrated electrical system, to make steel wires (Plug) must be etched very deep, dry etching dare Structural plugs have recently used copper as a conductive metal wire; methods can meet this need. An oxygen semiconductor (c_ ☆ layer of gold 瓜 was implanted into the m-structure early, and a wafer stone substrate, often referred to as wafer wafer, was first formed on the surface, and then the image was used to deposit an internal dielectric layer (Intra Uvel Dielectl: ie Phase deposition technology siliconized silicon dioxide, carved out on the surface of the dielectric layer using the image of the nick, such as the second channel arench). The phantom ion post-etching technology will be used to chemical vapor deposition or metal heat flow method After the surface of the dielectric layer is flattened, = 成 Ϊ = ,,, .. The structure was implanted early using reactive ion engraving for planarization. Nowadays, chemical mechanical polishing has been widely replaced. Extension of the single-embedded process For the dual-embedded process, there are thousands of open windows on a dielectric material such as silicon dioxide, which are used to connect the metal wires and the vias. At the same time, the metal is filled in these open windows. Single embedded structure It is a copper process in which some trenches are formed in the insulating layer or the dielectric layer to form interconnects. The double-embedded structure is a multiple interconnect process. In addition to the trenches in the single-post-in structure, it also forms a connected dielectric. Layer hole. Double-embedding process roughly ^ three : 1) depositing a first three consecutive dielectric layer, the intermediate layer is an etch stop layer, a stop layer of which may be S i N, with the upper and lower layers is silicon dioxide. After the deposition of these three layers 508735, microlayers are used, and the same method is used to generate three layers to stop the standard. However, 5. Description of the invention (4) After the dielectric layer is etched through this layer, the etching layer pattern is paired, and the first transfer is deposited. It was not until the crystal that the double-embedded trench and the interstitial hole encountered some difficult-to-etch rates, and the origin line profile was relatively shallow. The process is difficult to produce, gold and silver, but deep, but it is used in polycrystalline seconds. The previous compound was chemically softer than the copper compound. In the process, it will cause: ’to form an interlayer and then etch the stop layer of gold II. 2) Another type of trench pattern is formed on the dielectric pattern using the formed metal: the next step is to deposit three layers of dielectric layer stopper, and then deposit the hole pattern of the dielectric layer, and then deposit the dielectric layer on the chip thereon. The structure is simultaneous problem-solving, which is evenly interconnected. Due to the fact that the internalization is not easy to sink and the crane's process makes the mechanical research mentioned in the chapter compare the hard grinding rate of the surface shadowing technology with the metal layer and the dielectric layer, and then the oxide stone is exposed and the light groove I is finished. Reduce the vapor deposition learned from the thin film line contacts on the wafers and some of the component connections. The dish-shaped grinding process made of copper has a fast speed. Because the disc conversion pattern is generated, the vias are first holed. 3) I insect is carved after I insect is engraved. There are few structures in the process. The depth of the deposition is difficult. There are characteristic rulers in the center. The metal used in these techniques is metal. These materials are metal-concave and intermediate. Non-uniformity is used to control deeper inches. There are more metal materials that can resist the resistance of the material and the corrosion rate of the current grinding. The titanium and rotten insects because of it but it must be refined to make the profile, small vertical The quality and the resistance of the gas phase are different from those of the barrier layer, which is caused by the abrasive compound. The wire channel is allowed to accurately control the etching in the process. The gold on the wafer is close to the side of the wafer. The aspect ratio is as good as a splash. The deeper penetration of copper is generally higher than copper. Qin and Qinhua caused by copper and titanium. By slow;
508735 五、發明說明(5) 本發明提供一種方法在_矣&卩久& ^ ^ , m . ,λ- Μ 乃凃隹钔表面降低碟狀凹陷及腐蝕現 象,因此改善在元件表面之平面度及均勻性。 ),將在/V金A"電層(IMD)上方沉積一銅晶層(Seed layer 金屬入/思 塗玻璃(寫)充填於開口窗内,去除内 雷μ = s上方之銅晶層,將旋塗材料去除,用選擇性盔 方法’將銅沉積於開口窗内,而阻障層及覆層: =也疋本發明之一部分’…文章中討論。範例技術 美國專利第5674787號,授與Zha〇等人雙嵌入内連線 、、、口構選擇性無電解電鍍沉積銅製程。 美國專利第5 1 83795號,Ting等人描述使用光阻去除 銅晶層之選擇性無電解電鍍銅製程。 美國專利第5705430號,Avanzino等人用一犧牲介声 孔充填之雙嵌入結構。 曰 美國專利第5817572號,Chi an g等人描述雙嵌入製程 美國專利第566337號,Koh等人藉由旋塗材料的沉積 及充填產生一低電極製程。 本發明主要是提供一種方法在銅導線雙後入製程中, 降低表面碟狀凹陷及腐蝕現象。 另一個主題是改善表面之整體平面度及均勻性。 根據這二個主題,本發明提供一種新方法產生雙欲入 結構’内金屬介電層首先沉積於矽基底上,覆層(cap〜 layer)沉積於内金屬介電層上方,將雙嵌入結構(介層孔508735 V. Description of the invention (5) The present invention provides a method for reducing the dish-like depression and corrosion phenomenon on the surface of _ 矣 & 卩 久 & ^ ^, m. Flatness and uniformity. ), Depositing a copper crystal layer (Seed layer metal / Situ glass (write)) on the / V gold A " electrical layer (IMD) and filling the opening window to remove the copper crystal layer above the inner lightning μ = s, The spin-coating material is removed and the selective helmet method is used to 'deposit copper in the open window, while the barrier layer and coating: = also part of the invention' ... discussed in the article. Example Technology US Patent No. 5674787, awarded A process for double-embedded interconnecting, zirconium, and electro-selective electroless plating of copper with Zhao 0 et al. US Patent No. 5 1 83795, Ting et al. Describe selective electroless copper electroplating using photoresist to remove copper crystal layers US Patent No. 5705430, Avanzino et al. Double-embedded structure filled with a sacrificial mesopore. Said US Patent No. 5817572, Chiang et al. Described the dual-embedded process US Patent No. 566337, Koh et al. The deposition and filling of the spin-coated material produces a low-electrode process. The present invention mainly provides a method to reduce the dish-like depression and corrosion phenomenon on the surface during the double-entry process of copper wires. Another theme is to improve the overall flatness and uniformity of the surface According to these two themes, the present invention provides a new method to generate a double-introduction structure. The inner metal dielectric layer is first deposited on a silicon substrate, and a cap layer is deposited over the inner metal dielectric layer to double-embed. Structure (via via
508735 五、發明說明(6) 及渠溝開口 欽基阻障層 沉積於阻障 材料可完全 和銅晶層, 層和銅晶層 用以保護開 並利用選擇 保護了内金 多的銅則由 )製作於 沉積於雙 層之上。 或部分固 而覆層則 時,介層 口窗内部 性無電解 屬介電層 化學機械 可被去除。在此製程 其周圍區威沉積一襯 f層及内金屬介電層内,將鈕 肷入結構内及覆層上方,然後 雙肷入結構内塗上旋塗材料, 化,去除内金屬介電層上方之 可部分保留或予以去^。♦去 孔及渠溝開口内之旋塗材^需 表面,避免遭受破壞。除去旋 電鍍法沉積銅於開u窗内,此 ,避免遭受電鍍銅製程時之污 研磨去除。當鋼沉積完成後, 最後-個階段,我們在雙嵌入 裡(liner)或氣化擴散保護層。 或鎢或 銅晶層 此旋塗 阻障層 除阻障 保留, 塗材料 時覆層 染,過 覆層則 結構及 圖號簡單説明: 10 金屬層 12 介層 14 渠溝 16 介電層 18 覆層 20 阻障層 22 鋼晶層 24 旋塗村料 26 無電鍍銅 30 氣化擴散保護層 發明詳細説明508735 V. Description of the invention (6) and trench opening Chinky barrier layer deposited on the barrier material can be completely with copper crystal layer, the layer and copper crystal layer are used to protect the opening and the copper which is selected to protect the inner gold is made by) Deposited on a double layer. When the coating is partially or partially solidified, the internal non-electrolysis of the dielectric layer and the window is a dielectric layer. The chemical mechanism can be removed. In this process, a lining layer F and an inner metal dielectric layer are deposited in the surrounding area, and the button is inserted into the structure and above the cladding layer, and then the double-injection structure is coated with spin coating material to remove the inner metal dielectric. Above the layer can be partially retained or removed ^. ♦ The spin-coated materials in the holes and trench openings need a surface to avoid damage. Removal electroplating method deposits copper in the open window, so as to avoid contamination during the process of copper electroplating. When the steel deposition is completed, in the last stage, we are in a double-liner or gasification diffusion protective layer. Or tungsten or copper crystal layer. This spin-coated barrier layer is kept in addition to the barrier. When coating the material, the coating is dyed, and the structure and drawing number of the overcoat layer are simply explained. 10 Metal layer 12 Interlayer 14 Channel trench 16 Dielectric layer 18 Overlay Layer 20 Barrier layer 22 Steel crystal layer 24 Spin-coating material 26 Electroless copper 30 Evaporation diffusion protective layer Detailed description of the invention
508735508735
參照第1圖内金 覆層1 8則沉積於内金 作為覆層的條件 化學機械研磨去除, ,大約100至30 0 0埃、 介電層,阻障層及銅 晶層加速了選擇性無 結構與其相鄰區域材 第2圖顯示在覆 之剖面圖。雙嵌入結 孔1 2和在介層孔1 2上 需注意的是第3a 材質之情況,第4a圖 醯亞胺。 屬介電層16沉積於金屬層1〇上方, 屬介電層1 6上方。 與銅阻障層一樣,必須容易被蝕刻或 另一個條件是必須沉積至適當的厚度 •此覆層在後續製程中可保護内金屬 晶層之功用,在前文已闡述過,而鋼 電解銅之沉積,阻障層則避免雙嵌入 料之相互擴散。 層18及内金屬介電層16之雙嵌入結構 構包含了直接與金屬層1〇接觸之介層 方之内連接線或渠溝12。 曰 圖和第3b圖旋塗材料為阻劑(resist) 和第4b圖旋塗材料則為旋塗玻璃或聚 第3a圖顯示銅晶層22和阻障層20沉積在雙嵌入結 之剖面圖。阻劑旋塗材料24沉積在銅晶層22之上方。 阻障層20沉積在雙嵌入結構之側壁及覆層丨8和内介電 層1 6之上方,其材質可為鈦或鎢或鈦基材料。 積在阻障層20之上方。 ^ 阻劑旋塗材料被用來充填於嵌入結構内,即充填於介 層孔12(第2圖)和内連接線14。另一種旋塗材料可為旋塗 玻璃或聚醯亞胺,這二種旋塗材料將在第4a圖和第4b圖 时淪。旋塗材料在後續製程中,可能部分或完全固化,其 主要功用為保護雙嵌入結構之内層表面。 八Referring to Figure 1, the internal gold coating 18 is deposited under the conditions of internal gold as a coating for chemical mechanical polishing removal, about 100 to 300 angstroms, the dielectric layer, the barrier layer and the copper crystal layer accelerate the selectivity. The structure and its adjacent area are shown in Figure 2 in the cross section of the cover. Double-embedded junction holes 12 and interposer holes 12 Note that the material of 3a is shown in Fig. 4a. A metal dielectric layer 16 is deposited over the metal layer 10 and over the metal dielectric layer 16. Like the copper barrier layer, it must be easily etched or another condition is that it must be deposited to an appropriate thickness. This coating can protect the inner metal crystal layer in the subsequent process, as described above. The barrier layer is deposited to avoid mutual diffusion of the dual inserts. The double-embedded structure of the layer 18 and the inner metal dielectric layer 16 includes interconnect lines or trenches 12 of the dielectric layer directly in contact with the metal layer 10. Figure 3b and Figure 3b are spin-coating materials for resist and Figure 4b are spin-coating materials for spin-on glass or poly. Figure 3a shows a cross-section view of copper crystal layer 22 and barrier layer 20 deposited on a double-embedded junction. . A resist spin-on material 24 is deposited over the copper crystal layer 22. The barrier layer 20 is deposited over the sidewalls and cladding layers 8 and the inner dielectric layer 16 of the dual-embedded structure, and the material can be titanium, tungsten, or a titanium-based material. Accumulated on the barrier layer 20. ^ The resist spin-on material is used to fill the embedded structure, that is, the interstitial hole 12 (Figure 2) and the interconnect 14. Another spin-coating material may be spin-coated glass or polyimide. These two spin-coating materials will be shown in Figures 4a and 4b. The spin coating material may be partially or completely cured in the subsequent process, and its main function is to protect the inner surface of the dual embedded structure. Eight
第12頁 508735 五、發明說明(8) 产,3a圖和第3b圖顯示如果旋塗材料24是阻劑材質,用 氧或氫基電漿蝕刻方法去除在銅晶層2 2上方和内金屬介電 層上方過多的旋塗材料24,去除掉旋塗材料後,藉由非等 向性乾蝕刻(氯或氟基電漿)去除銅晶層22和阻障^2〇,且 過蝕刻至覆層18。由於阻劑對乾蝕刻製程有报高二 ,阻劑24保護底下的銅晶層22。另一種方法是使用ms〇/ CCL4或HF/CHgCOOH選擇性濕蝕刻銅晶層22,而氫氟酸可以 選擇性蝕刻鈕/鎢/鈦基阻障層2 〇,而沒有蝕刻太多在雙 嵌入結構内之阻劑旋塗材料。 第4a圖和第4b圖說明旋塗材料為旋塗玻璃或聚醯亞胺 時之應用。在内金屬介電層16上方過多的旋塗材料24,銅 晶層22及阻障層20可以利用化學機械研磨法去除。當研磨 至覆層1 8,則可停止研磨。第4a圖為研磨之前整個結構, 第4b圖則顯示出阻障層2〇,銅晶層22,旋塗材料24已被去 除之剖面圖。 在去除覆層1 8上方之銅晶層和阻障層時,旋塗材料24 (第^4b圖)仍然存在於雙嵌入結構内,旋塗材料24保護了在 雙嵌入結構内之銅晶層22。覆層18上方之銅晶層22,阻障 f 2〇及旋塗材料24被去除之後,再用一獨立製程去除開口 固内之旋塗材料24。 由上述所提去除銅晶層,阻障層和旋塗材料之製程步驟 ^結如下表。第一行為所用之旋塗材料,第二行為選擇 性去除過多之旋塗材料,銅晶層和阻障層之方法,第三行 則為去除雙嵌入結構内旋塗材料之方法。Page 12 508735 V. Description of the invention (8) Figures 3a and 3b show that if the spin-coating material 24 is a resist material, use oxygen or hydrogen-based plasma etching to remove the metal above the copper crystal layer 22 and the inner metal. Excessive spin-coating material 24 over the dielectric layer. After removing the spin-coating material, the copper crystal layer 22 and the barrier ^ 20 are removed by anisotropic dry etching (chlorine or fluorine-based plasma), and over-etched to Cladding layer 18. Since the resist has a high grade for the dry etching process, the resist 24 protects the underlying copper crystal layer 22. Another method is to selectively wet etch the copper crystal layer 22 using msO / CCL4 or HF / CHgCOOH, while hydrofluoric acid can selectively etch the button / tungsten / titanium-based barrier layer 2 without etching too much in the dual embedding A resist spin coating material within the structure. Figures 4a and 4b illustrate applications where the spin coating material is spin coated glass or polyimide. The excessive spin-coating material 24, the copper crystal layer 22 and the barrier layer 20 above the inner metal dielectric layer 16 can be removed by chemical mechanical polishing. When grinding to the coating layer 18, grinding can be stopped. Figure 4a shows the entire structure before grinding, and Figure 4b shows a cross-sectional view of the barrier layer 20, the copper crystal layer 22, and the spin-on material 24. When the copper crystal layer and the barrier layer above the cover layer 18 are removed, the spin-coated material 24 (Fig. 4b) still exists in the dual-embedded structure, and the spin-coated material 24 protects the copper crystal layer in the dual-embedded structure. twenty two. After the copper crystal layer 22 above the cladding layer 18, the barrier f20 and the spin-on material 24 are removed, the spin-on material 24 inside the opening is removed by a separate process. The process steps for removing the copper crystal layer, the barrier layer and the spin-coated material from the above are summarized in the following table. The first line is a method of spin-coating material used in the second line, and the second line is a method of selectively removing too much spin-coated material, copper crystal layer and barrier layer, and the third line is a method of removing the spin-coated material in the dual embedded structure.
第13頁Page 13
第— > 笛 、 7 一列為去除銅晶層上方阻劑旋塗材 叫y項則為去除銅晶層和阻障層上方阻劑旋 劑, 蝕刻 料之蝕刻 塗材料之 Τ)δίΓ ~~ (氯或氟)或濕I虫刻 (DMSQCCL^The first-> column 7 is for removing the resist spin coating material above the copper crystal layer. The item called y is for removing the copper spin layer and the resist spin coating material above the barrier layer. T) δίΓ ~~ (Chlorine or fluorine) or wet worm (DMSQCCL ^
第三行 乾I虫刻(1/氮)The third line Dry I worm (1 / nitrogen)
去除雙肷入結構上方之旋塗材料製程為乾餘刻製程( ^格所示):溫度介於150至30 0 °c,蝕刻劑如表格所述 ,流量介於10到300 0 SCCM,壓力則大約50到loooG mT()RR ’钱刻去除時間約1至5分鐘。 去除雙嵌入結構内阻劑或聚醯亞胺旋塗材料製程為乾 钱刻,溫度150到30 0 °C,蝕刻劑為氫,流量1〇到3〇〇〇 < 6 SCCM,壓力則大約50到1 0 0 0 0 mTORR,蝕刻去除時間約1至 5分鐘。The process of removing the spin-coated material above the double-entry structure is a dry-remove process (shown in squares): the temperature is between 150 and 300 ° C, the etchant is as described in the table, the flow rate is between 10 and 300 0 SCCM, and the pressure Then it takes about 50 to loooG mT () RR 'money removal time is about 1 to 5 minutes. The process of removing the double-embedded internal resistance agent or polyimide spin-coating material is dry engraving, the temperature is 150 to 300 ° C, the etchant is hydrogen, the flow rate is 10 to 3,000 < 6 SCCM, and the pressure is about 50 to 1 0 0 0 0 mTORR, the etching removal time is about 1 to 5 minutes.
在製程中需注意的是銅充填入雙嵌入結構内之前,覆 層18(至少部分地)仍在金屬介電層上方,其保護内金屬介 電層,避免遭受銅之污染。 第5圖為經過選擇性無電解銅26沉積在雙嵌入結構内 之剖面圖。 本發明之關鍵是在作選擇性無電解銅沉積製程時,覆It should be noted in the manufacturing process that the coating 18 (at least partially) is still above the metal dielectric layer before the copper is filled into the dual embedded structure, which protects the inner metal dielectric layer from copper contamination. Figure 5 is a cross-sectional view of the selective embedded copper 26 deposited in a dual embedded structure. The key of the present invention is that during the selective electroless copper deposition process,
第14頁 508735Page 14 508735
五、發明說明(ίο) 製程鋼溶劑之污染。 雙嵌入結構内,而電 形成一銅薄膜,另一 積’但此技術還沒被 I作鋼沉積的優點是 不會有銅的沉積,沉 域之表面,如第5圖 化’消除了碟狀凹陷 有連續銅晶層可以傳V. Description of the Invention (ίο) Contamination of the solvent in the process steel. Double-embedded in the structure, and a copper film is formed electrically, another product is' but this technology has not been used as a steel deposit. The advantage is that there will be no copper deposition. A continuous copper crystal layer can pass
層18保護内金屬介電層避免遭受電錢 用一無電解電鍵製程將銅充填於 艘製程無法應用在此製程是因為它會 技術為選擇性化學氣相沉積作銅的沉 廣泛應用。使用選擇性無電解電鑛製 在雙嵌入結構開口窗外之週圍區域, 積完後銅插塞將會過沉積超過充填區 所示。用化學機械研磨法將表面平坦 及腐鍅現象,如第6圖所示。由於沒 導電流,因此無法使用電解電鐘法。 第6圖所示為經過化學機械研磨,將覆層18上方過多 的銅去除,雙嵌入結構26之剖面圖。 第7圖為一完整雙嵌入結構剖面圖沉積層3〇為一銅氧 化擴散阻障層,此層3〇沉積於覆層18之上方,為一保護層 ,保護層30材質含有沉積於整個表面,如第7圖所二 本發明有幾項特徵: 1 ·在去除覆層上方旋塗材料’銅晶層和阻障層時,旋 塗材料仍存在於雙嵌入結構之開口窗内,因此保護了結構 内之銅晶層。 2·覆層的存在是為了保護内金屬介電層,避免遭受選 擇性無電解銅沉積製程之污染。 3 ·去除過多的沉積銅後,覆層可以被去除或予以保留 ’作為内金屬介電層額外的保護。The layer 18 protects the inner metal dielectric layer from electrical charges. The copper filling process using an electroless bond process cannot be used in this process because it is widely used as a technology for selective chemical vapor deposition of copper. Using selective electroless electricity mining In the surrounding area outside the open window of the double-embedded structure, copper plugs will over-deposit beyond the filling area as shown. Use chemical mechanical polishing to flatten and rot the surface, as shown in Figure 6. Since there is no conductive current, the electrolytic clock method cannot be used. FIG. 6 is a cross-sectional view of the double-embedded structure 26 after removing excessive copper above the cladding layer 18 by chemical mechanical polishing. Fig. 7 is a cross-sectional view of a complete double-embedded structure. The deposited layer 30 is a copper oxide diffusion barrier layer. This layer 30 is deposited over the cladding layer 18 as a protective layer. The material of the protective layer 30 is deposited on the entire surface. As shown in Figure 7, the present invention has several features: 1. When the material 'copper crystal layer and barrier layer is spin-coated on top of the coating, the spin-coated material still exists in the opening window of the double-embedded structure, so it is protected. The copper crystal layer in the structure. 2. The cladding exists to protect the inner metal dielectric layer from contamination from the selective electroless copper deposition process. 3 · After removing excessively deposited copper, the cladding layer can be removed or retained ′ as additional protection for the inner metal dielectric layer.
第15頁 508735 五、發明說明(11) 4 ·覆層對銅有氧化擴散阻障之功用。 炎料 一般來說,碟狀凹陷和腐蝕效應是由於銅和阻障’、 地過沉積,碟 銅插塞 研磨速率不同所導致。第5圖所示 狀凹陷和腐韻現象並沒有發生。 0 ^然本發明利用一些圖例來作說明,但並不表示本發 些圖例,任何與本發明相關之變里性盥修 修改’都是本發明申請之專 ?本餐日月相關之變異或Page 15 508735 V. Description of the invention (11) 4 · The coating has the function of oxidative diffusion barrier to copper. Inflammation In general, dish-like depressions and corrosion effects are caused by copper and barrier ’, ground over-deposition, and different polishing rates of dish copper plugs. The sags and rot rhymes shown in Figure 5 did not occur. 0 ^ Although the present invention is described by using some illustrations, it does not mean that these illustrations are issued. Any modification related to the present invention is exclusive to the application of the present invention? Variations related to the day and month of this meal or
第16頁Page 16
叫 η 电 4〜首ij面圖。 508735 圖式簡單說明 第1圖為金屬層上方内金 第2圖在覆層和内金屬介 電層内形成雙嵌入 〜入結構之剖面圖 第3 a圖為阻障層, 構之别面圖 銅晶層和 阻劑旋塗材料 沉積於雙嵌入結 苐3b圖為第3a圖去除多餘 第4a圖為雙嵌入結構經過 或旋塗材料之剖面 =阻劑旋塗材料之剖面圖。 ’儿積阻障層,鋼晶層及旋塗玻璃 圖。 第4 b圖為第4 a圖雙嵌入么士;)¾证丄 構經過去除阻障層,銅晶層及旋 塗材料之剖面圖。 第5圖為經過選擇性無電解電鍍沉積銅之雙嵌入結構之剖 面圖。 第6圖為經過化學機械研磨後的剖面圖。 第7圖為沉積氧化擴散保護層後之剖面圖。Called η electricity 4 ~ the first ij plane. 508735 Brief description of the diagram. The first diagram is the inner gold layer above the metal layer. The second diagram is a cross-sectional view of the double embedded structure formed in the cladding layer and the inner metal dielectric layer. The third diagram is a barrier layer. The copper crystal layer and the resist spin-coating material are deposited on the double-embedded structure. Figure 3b shows the removal of the excess. Figure 4a shows the cross-section of the double-embedded structure or the spin-coated material = the cross-sectional view of the resist spin-coated material. ’Earth barrier layer, steel crystal layer and spin-coated glass. Figure 4b is the double-embedded Mozilla of Figure 4a;) ¾ The cross-sectional view of the structure after removing the barrier layer, copper crystal layer and spin coating material. Figure 5 is a cross-sectional view of a dual embedded structure of copper deposited by selective electroless plating. Fig. 6 is a sectional view after chemical mechanical polishing. FIG. 7 is a cross-sectional view after the oxidation diffusion protection layer is deposited.
第17頁Page 17
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