SG112797A1 - Substrate for semiconductor device, semiconductor chip mounting substrate, semiconductor device and method of fabrication thereof, and circuit board, together with electronic equipment - Google Patents
Substrate for semiconductor device, semiconductor chip mounting substrate, semiconductor device and method of fabrication thereof, and circuit board, together with electronic equipmentInfo
- Publication number
- SG112797A1 SG112797A1 SG200004247A SG200004247A SG112797A1 SG 112797 A1 SG112797 A1 SG 112797A1 SG 200004247 A SG200004247 A SG 200004247A SG 200004247 A SG200004247 A SG 200004247A SG 112797 A1 SG112797 A1 SG 112797A1
- Authority
- SG
- Singapore
- Prior art keywords
- semiconductor device
- substrate
- fabrication
- circuit board
- electronic equipment
- Prior art date
Links
- 239000004065 semiconductor Substances 0.000 title abstract 4
- 239000000758 substrate Substances 0.000 title abstract 4
- 238000004519 manufacturing process Methods 0.000 title 1
- 238000005389 semiconductor device fabrication Methods 0.000 title 1
- 239000000463 material Substances 0.000 abstract 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/562—Protection against mechanical damage
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
- H01L21/4803—Insulating or insulated parts, e.g. mountings, containers, diamond heatsinks
- H01L21/481—Insulating layers on insulating parts, with or without metallisation
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/93—Batch processes
- H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/0011—Working of insulating substrates or insulating layers
- H05K3/0044—Mechanical working of the substrate, e.g. drilling or punching
- H05K3/0052—Depaneling, i.e. dividing a panel into circuit boards; Working of the edges of circuit boards
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- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/05599—Material
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- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
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- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
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- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/484—Connecting portions
- H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
- H01L2224/48465—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
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- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
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- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
- H01L2224/8538—Bonding interfaces outside the semiconductor or solid-state body
- H01L2224/85399—Material
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- H01L2224/93—Batch processes
- H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/42—Wire connectors; Manufacturing methods related thereto
- H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
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- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
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- H01L2924/01004—Beryllium [Be]
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- H01L2924/01005—Boron [B]
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- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/102—Material of the semiconductor or solid state bodies
- H01L2924/1025—Semiconducting materials
- H01L2924/10251—Elemental semiconductors, i.e. Group IV
- H01L2924/10253—Silicon [Si]
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- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
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- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
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- H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
- H01L2924/1901—Structure
- H01L2924/1904—Component type
- H01L2924/19041—Component type being a capacitor
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- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
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- H01L2924/19043—Component type being a resistor
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- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/30—Technical effects
- H01L2924/301—Electrical effects
- H01L2924/3025—Electromagnetic shielding
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/09—Shape and layout
- H05K2201/09009—Substrate related
- H05K2201/09063—Holes or slots in insulating substrate not used for electrical connections
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/22—Secondary treatment of printed circuits
- H05K3/28—Applying non-metallic protective coatings
- H05K3/284—Applying non-metallic protective coatings for encapsulating mounted components
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Computer Hardware Design (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
- Dicing (AREA)
- Structure Of Printed Boards (AREA)
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP21318499 | 1999-07-28 | ||
JP2000173294A JP2001102486A (ja) | 1999-07-28 | 2000-06-09 | 半導体装置用基板、半導体チップ搭載基板、半導体装置及びその製造方法、回路基板並びに電子機器 |
Publications (1)
Publication Number | Publication Date |
---|---|
SG112797A1 true SG112797A1 (en) | 2005-07-28 |
Family
ID=26519652
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
SG200004247A SG112797A1 (en) | 1999-07-28 | 2000-07-27 | Substrate for semiconductor device, semiconductor chip mounting substrate, semiconductor device and method of fabrication thereof, and circuit board, together with electronic equipment |
Country Status (5)
Country | Link |
---|---|
US (2) | US6774500B1 (ko) |
JP (1) | JP2001102486A (ko) |
KR (1) | KR100356323B1 (ko) |
SG (1) | SG112797A1 (ko) |
TW (1) | TW515011B (ko) |
Families Citing this family (11)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN100407422C (zh) | 2001-06-07 | 2008-07-30 | 株式会社瑞萨科技 | 半导体装置及其制造方法 |
DE102004014438A1 (de) * | 2004-03-24 | 2005-11-03 | Siemens Ag | Leiterplattennutzen mit einer Vielzahl an Schaltungsträgern, Schaltungsträger und Verfahren zum Vereinzeln von Schaltungsträgern aus einem Leiterplattennutzen |
WO2008066133A1 (en) * | 2006-11-30 | 2008-06-05 | Tokuyama Corporation | Method for manufacturing metallized ceramic substrate chip |
JP4967628B2 (ja) * | 2006-12-05 | 2012-07-04 | パナソニック株式会社 | セラミック多層基板の製造方法 |
KR100871707B1 (ko) * | 2007-03-30 | 2008-12-05 | 삼성전자주식회사 | 깨짐을 억제하는 몰딩부를 갖는 웨이퍼 레벨 패키지 및 그제조방법 |
US7859084B2 (en) * | 2008-02-28 | 2010-12-28 | Panasonic Corporation | Semiconductor substrate |
JP2010004011A (ja) * | 2008-05-19 | 2010-01-07 | Panasonic Corp | 半導体装置及び半導体装置の製造方法 |
KR100951308B1 (ko) * | 2008-08-07 | 2010-04-05 | 삼성전기주식회사 | 카메라 모듈용 기판 제조방법 및 카메라 모듈용 기판 제조를 위한 기판 트레이 |
KR101001352B1 (ko) | 2008-09-04 | 2010-12-14 | 삼성전기주식회사 | 패키지용 기판 |
JP2010232471A (ja) * | 2009-03-27 | 2010-10-14 | Renesas Electronics Corp | 半導体装置の製造方法および半導体装置 |
KR101049466B1 (ko) | 2010-05-28 | 2011-07-15 | 삼성전기주식회사 | 기판 어레이 및 이를 이용한 카메라 모듈의 제조방법 |
Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4610079A (en) * | 1980-01-22 | 1986-09-09 | Tokyo Shibaura Denki Kabushiki Kaisha | Method of dicing a semiconductor wafer |
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JPS584814B2 (ja) * | 1976-04-27 | 1983-01-27 | 三菱電機株式会社 | 半導体装置 |
US4263341A (en) * | 1978-12-19 | 1981-04-21 | Western Electric Company, Inc. | Processes of making two-sided printed circuit boards, with through-hole connections |
US4355457A (en) * | 1980-10-29 | 1982-10-26 | Rca Corporation | Method of forming a mesa in a semiconductor device with subsequent separation into individual devices |
JPS63226053A (ja) * | 1987-03-13 | 1988-09-20 | Matsushita Electric Ind Co Ltd | 混成集積チツプモジユ−ル |
KR910003735B1 (ko) * | 1988-12-17 | 1991-06-10 | 삼성전자 주식회사 | 발광장치 |
KR920005461B1 (ko) * | 1990-03-03 | 1992-07-04 | 현대전자산업 주식회사 | 인쇄회로기판 제조방법 |
US5153379A (en) * | 1990-10-09 | 1992-10-06 | Motorola, Inc. | Shielded low-profile electronic component assembly |
JPH05136261A (ja) * | 1991-11-15 | 1993-06-01 | Kawasaki Steel Corp | 半導体チツプ及びウエハのダイシング方法 |
US5824569A (en) * | 1992-07-15 | 1998-10-20 | Micron Technology, Inc. | Semiconductor device having ball-bonded pads |
JPH06295962A (ja) * | 1992-10-20 | 1994-10-21 | Ibiden Co Ltd | 電子部品搭載用基板およびその製造方法並びに電子部品搭載装置 |
US5455456A (en) * | 1993-09-15 | 1995-10-03 | Lsi Logic Corporation | Integrated circuit package lid |
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2000
- 2000-06-09 JP JP2000173294A patent/JP2001102486A/ja not_active Withdrawn
- 2000-07-26 US US09/626,146 patent/US6774500B1/en not_active Expired - Fee Related
- 2000-07-27 KR KR1020000043287A patent/KR100356323B1/ko not_active IP Right Cessation
- 2000-07-27 SG SG200004247A patent/SG112797A1/en unknown
- 2000-07-28 TW TW089115171A patent/TW515011B/zh not_active IP Right Cessation
-
2004
- 2004-06-23 US US10/873,158 patent/US20040227259A1/en not_active Abandoned
Patent Citations (1)
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---|---|---|---|---|
US4610079A (en) * | 1980-01-22 | 1986-09-09 | Tokyo Shibaura Denki Kabushiki Kaisha | Method of dicing a semiconductor wafer |
Also Published As
Publication number | Publication date |
---|---|
TW515011B (en) | 2002-12-21 |
US6774500B1 (en) | 2004-08-10 |
JP2001102486A (ja) | 2001-04-13 |
KR100356323B1 (ko) | 2002-10-19 |
KR20010030016A (ko) | 2001-04-16 |
US20040227259A1 (en) | 2004-11-18 |
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