SG11201908050TA - Multiple plate line architecture for multideck memory array - Google Patents

Multiple plate line architecture for multideck memory array

Info

Publication number
SG11201908050TA
SG11201908050TA SG11201908050TA SG11201908050TA SG 11201908050T A SG11201908050T A SG 11201908050TA SG 11201908050T A SG11201908050T A SG 11201908050TA SG 11201908050T A SG11201908050T A SG 11201908050TA
Authority
SG
Singapore
Prior art keywords
international
plate line
lines
multideck
memory
Prior art date
Application number
Inventor
Ferdinando Bedeschi
Original Assignee
Micron Technology Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Micron Technology Inc filed Critical Micron Technology Inc
Publication of SG11201908050TA publication Critical patent/SG11201908050TA/en

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/22—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using ferroelectric elements
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/22—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using ferroelectric elements
    • G11C11/221—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using ferroelectric elements using ferroelectric capacitors
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/22—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using ferroelectric elements
    • G11C11/225—Auxiliary circuits
    • G11C11/2253—Address circuits or decoders
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/22—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using ferroelectric elements
    • G11C11/225—Auxiliary circuits
    • G11C11/2253—Address circuits or decoders
    • G11C11/2257—Word-line or row circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/22—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using ferroelectric elements
    • G11C11/225—Auxiliary circuits
    • G11C11/2259—Cell access
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/22—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using ferroelectric elements
    • G11C11/225—Auxiliary circuits
    • G11C11/2273—Reading or sensing circuits or methods
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C5/00—Details of stores covered by group G11C11/00
    • G11C5/02—Disposition of storage elements, e.g. in the form of a matrix array
    • G11C5/025—Geometric lay-out considerations of storage- and peripheral-blocks in a semiconductor storage device
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C5/00—Details of stores covered by group G11C11/00
    • G11C5/06—Arrangements for interconnecting storage elements electrically, e.g. by wiring
    • G11C5/063—Voltage and signal distribution in integrated semi-conductor memory access lines, e.g. word-line, bit-line, cross-over resistance, propagation delay
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C5/00—Details of stores covered by group G11C11/00
    • G11C5/06—Arrangements for interconnecting storage elements electrically, e.g. by wiring
    • G11C5/066—Means for reducing external access-lines for a semiconductor memory clip, e.g. by multiplexing at least address and data signals
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B53/00—Ferroelectric RAM [FeRAM] devices comprising ferroelectric memory capacitors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B53/00—Ferroelectric RAM [FeRAM] devices comprising ferroelectric memory capacitors
    • H10B53/20—Ferroelectric RAM [FeRAM] devices comprising ferroelectric memory capacitors characterised by the three-dimensional arrangements, e.g. with cells on different height levels
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/22—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using ferroelectric elements
    • G11C11/225—Auxiliary circuits
    • G11C11/2275—Writing or programming circuits or methods
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B53/00—Ferroelectric RAM [FeRAM] devices comprising ferroelectric memory capacitors
    • H10B53/30—Ferroelectric RAM [FeRAM] devices comprising ferroelectric memory capacitors characterised by the memory core region

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Semiconductor Memories (AREA)
  • Physics & Mathematics (AREA)
  • Dram (AREA)
  • Geometry (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Storage Device Security (AREA)

Abstract

b 670-a 670-b 660 D Plate line decoder Global plate line Load plate line (WV 600 FIG. 6 W O 20 18/ 18 295 1 Al (12) INTERNATIONAL APPLICATION PUBLISHED UNDER THE PATENT COOPERATION TREATY (PCT) (19) World Intellectual Property Organization International Bureau (43) International Publication Date 04 October 2018 (04.10.2018) W I PO I PCT onion °nolo OH 11010111 ow (10) International Publication Number WO 2018/182951 Al (51) International Patent Classification: Gl1C 11/22 (2006.01) Gl1C 5/06 (2006.01) (21) International Application Number: PCT/US2018/021807 (22) International Filing Date: 09 March 2018 (09.03.2018) (25) Filing Language: English (26) Publication Language: English (30) Priority Data: 15/469,865 27 March 2017 (27.03.2017) US (71) Applicant: MICRON TECHNOLOGY, INC. [US/US]; 8000 South Federal Way, Boise, Idaho 83716-9632 (US). (72) Inventor: BEDESCHI, Ferdinando; 8000 South Federal Way, Boise, Idaho 83716-9632 (US). (74) Agent: HARRIS, Philip W.; Holland & Hart LLP, P.O. Box 11583, Salt Lake City, Utah 84147 (US). (81) Designated States (unless otherwise indicated, for every kind of national protection available): AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BN, BR, BW, BY, BZ, CA, CH, CL, CN, CO, CR, CU, CZ, DE, DJ, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IR, IS, JO, JP, KE, KG, KH, KN, KP, KR, KW, KZ, LA, LC, LK, LR, LS, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PA, PE, PG, PH, PL, PT, QA, RO, RS, RU, RW, SA, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TH, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW. (84) Designated States (unless otherwise indicated, for every kind of regional protection available): ARIPO (BW, GH, GM, KE, LR, LS, MW, MZ, NA, RW, SD, SL, ST, SZ, TZ, UG, ZM, ZW), Eurasian (AM, AZ, BY, KG, KZ, RU, TJ, TM), European (AL, AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, SM, TR), OAPI (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, KM, ML, MR, NE, SN, TD, TG). Declarations under Rule 4.17: as to applicant's entitlement to apply for and be granted a patent (Rule 4.1700) as to the applicant's entitlement to claim the priority of the earlier application (Rule 4.17(iii)) Published: — with international search report (Art. 21(3)) (54) Title: MULTIPLE PLATE LINE ARCHITECTURE FOR MULTIDECK MEMORY ARRAY (57) : Methods, systems, and devices for multiple plate line archi- tecture for multideck memory arrays are described. A memory device may include two or more three-dimensional arrays of ferroelectric memory cells 650 overlying a substrate layer that includes various components of support cir- 620 ‘ ,.. , ' 655-6 655-a 610-b 655-c 680-6 cuitry, such as decoders and sense amplifiers. Each memory cell of the array may have a ferroelectric container and a selector device. Multiple plate lines SO-b or other access lines may be routed through the various decks of the device to support access to memory cells within those decks. Plate lines or other access lines may be coupled between support circuitry and memory cells through on pitch via (OPV) structures. OPV structures may include selector devices to provide an additional degree of freedom in multideck selectivity. Various number of plate lines and access lines may be employed to accommodate different configurations and orientations of the ferroelectric containers.
SG11201908050T 2017-03-27 2018-03-09 Multiple plate line architecture for multideck memory array SG11201908050TA (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US15/469,865 US10262715B2 (en) 2017-03-27 2017-03-27 Multiple plate line architecture for multideck memory array
PCT/US2018/021807 WO2018182951A1 (en) 2017-03-27 2018-03-09 Multiple plate line architecture for multideck memory array

Publications (1)

Publication Number Publication Date
SG11201908050TA true SG11201908050TA (en) 2019-10-30

Family

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Family Applications (2)

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SG10202110256Y SG10202110256YA (en) 2017-03-27 2018-03-09 Multiple plate line architecture for multideck memory array
SG11201908050T SG11201908050TA (en) 2017-03-27 2018-03-09 Multiple plate line architecture for multideck memory array

Family Applications Before (1)

Application Number Title Priority Date Filing Date
SG10202110256Y SG10202110256YA (en) 2017-03-27 2018-03-09 Multiple plate line architecture for multideck memory array

Country Status (8)

Country Link
US (4) US10262715B2 (en)
EP (1) EP3602558A4 (en)
JP (2) JP7222903B2 (en)
KR (3) KR102262372B1 (en)
CN (1) CN110462740B (en)
SG (2) SG10202110256YA (en)
TW (1) TWI671742B (en)
WO (1) WO2018182951A1 (en)

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Also Published As

Publication number Publication date
KR102392613B1 (en) 2022-04-29
TW201903765A (en) 2019-01-16
KR20210068612A (en) 2021-06-09
WO2018182951A1 (en) 2018-10-04
CN110462740A (en) 2019-11-15
TWI671742B (en) 2019-09-11
EP3602558A1 (en) 2020-02-05
JP2022027811A (en) 2022-02-14
SG10202110256YA (en) 2021-10-28
KR20190114020A (en) 2019-10-08
CN110462740B (en) 2023-07-18
US20190244652A1 (en) 2019-08-08
US10304513B2 (en) 2019-05-28
KR20220054726A (en) 2022-05-03
US10262715B2 (en) 2019-04-16
US20180330771A1 (en) 2018-11-15
US20180277181A1 (en) 2018-09-27
JP2020517092A (en) 2020-06-11
KR102262372B1 (en) 2021-06-09
JP7222903B2 (en) 2023-02-15
US20200388315A1 (en) 2020-12-10
US11227648B2 (en) 2022-01-18
US10734057B2 (en) 2020-08-04
EP3602558A4 (en) 2020-12-23

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