SG11201907532VA - Active boundary quilt architecture memory - Google Patents

Active boundary quilt architecture memory

Info

Publication number
SG11201907532VA
SG11201907532VA SG11201907532VA SG11201907532VA SG11201907532VA SG 11201907532V A SG11201907532V A SG 11201907532VA SG 11201907532V A SG11201907532V A SG 11201907532VA SG 11201907532V A SG11201907532V A SG 11201907532VA SG 11201907532V A SG11201907532V A SG 11201907532VA
Authority
SG
Singapore
Prior art keywords
memory
international
active boundary
portions
memory array
Prior art date
Application number
SG11201907532VA
Inventor
Christophe Vincent Antoine Laurent
Original Assignee
Micron Technology Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Micron Technology Inc filed Critical Micron Technology Inc
Publication of SG11201907532VA publication Critical patent/SG11201907532VA/en

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C5/00—Details of stores covered by group G11C11/00
    • G11C5/02—Disposition of storage elements, e.g. in the form of a matrix array
    • G11C5/025—Geometric lay-out considerations of storage- and peripheral-blocks in a semiconductor storage device
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/22—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using ferroelectric elements
    • G11C11/225—Auxiliary circuits
    • G11C11/2253—Address circuits or decoders
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/22—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using ferroelectric elements
    • G11C11/225—Auxiliary circuits
    • G11C11/2259—Cell access
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
    • G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
    • G11C13/0021—Auxiliary circuits
    • G11C13/0023—Address circuits or decoders
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C8/00—Arrangements for selecting an address in a digital store
    • G11C8/10—Decoders
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/0203—Particular design considerations for integrated circuits
    • H01L27/0207—Geometrical layout of the components, e.g. computer aided design; custom LSI, semi-custom LSI, standard cell technique
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B63/00—Resistance change memory devices, e.g. resistive RAM [ReRAM] devices
    • H10B63/20—Resistance change memory devices, e.g. resistive RAM [ReRAM] devices comprising selection components having two electrodes, e.g. diodes
    • H10B63/24—Resistance change memory devices, e.g. resistive RAM [ReRAM] devices comprising selection components having two electrodes, e.g. diodes of the Ovonic threshold switching type
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N70/00—Solid-state devices without a potential-jump barrier or surface barrier, and specially adapted for rectifying, amplifying, oscillating or switching
    • H10N70/20—Multistable switching devices, e.g. memristors
    • H10N70/231—Multistable switching devices, e.g. memristors based on solid-state phase change, e.g. between amorphous and crystalline phases, Ovshinsky effect
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/06—Sense amplifiers; Associated circuits, e.g. timing or triggering circuits
    • G11C7/062—Differential amplifiers of non-latching type, e.g. comparators, long-tailed pairs

Abstract

WO 18/ 15 175 6 Al (12) INTERNATIONAL APPLICATION PUBLISHED UNDER THE PATENT COOPERATION TREATY (PCT) (19) World Intellectual Property Organization International Bureau (43) International Publication Date 23 August 2018 (23.08.2018) WIP0 I PCT O V SID o OH H How iflo VII IE (10) International Publication Number WO 2018/151756 Al (51) International Patent Classification: Gl1C 11/22 (2006.01) (21) International Application Number: PCT/US2017/049441 (22) International Filing Date: 30 August 2017 (30.08.2017) (25) Filing Language: English (26) Publication Language: English (30) Priority Data: 15/434,401 16 February 2017 (16.02.2017) US (71) Applicant: MICRON TECHNOLOGY, INC. [US/US]; 8000 S. Federal Way, Boise, Idaho 83716-9632 (US). (72) Inventor: LAURENT, Christophe Vincent Antoine; 8000 S. Federal Way, Boise, Idaho 83716-9632 (US). (74) Agent: HARRIS, Philip W.; Holland & Hart LLP, P.O. Box 11583, Salt Lake City, Utah 84147 (US). (81) Designated States (unless otherwise indicated, for every kind of national protection available): AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BN, BR, BW, BY, BZ, CA, CH, CL, CN, CO, CR, CU, CZ, DE, DJ, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IR, IS, JO, JP, KE, KG, KH, KN, KP, KR, KW, KZ, LA, LC, LK, LR, LS, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PA, PE, PG, PH, PL, PT, QA, RO, RS, RU, RW, SA, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TH, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW. (84) Designated States (unless otherwise indicated, for every kind of regional protection available): ARIPO (BW, GH, GM, KE, LR, LS, MW, MZ, NA, RW, SD, SL, ST, SZ, TZ, UG, ZM, ZW), Eurasian (AM, AZ, BY, KG, KZ, RU, TJ, TM), European (AL, AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, SM, TR), OAPI (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, KM, ML, MR, NE, SN, TD, TG). Declarations under Rule 4.17: as to applicant's entitlement to apply for and be granted a patent (Rule 4.17(ii)) as to the applicant's entitlement to claim the priority of the earlier application (Rule 4.17(iii)) Published: — with international search report (Art. 21(3)) (54) Title: ACTIVE BOUNDARY QUILT ARCHITECTURE MEMORY (57) : Methods, systems, and apparatus that increase avail- 415_a able memory or storage using active boundary areas in quilt architec- ture are described. A memory array may include memory cells overly- ing each portion of a substrate layer that includes certain types of sup- port circuitry, such as decoders and sense amplifiers. Active boundary portions, which may be elements of the memory array having a differ- ent configuration from other portions of the memory array, may be po- sitioned on two sides of the memory array and may increase available data in a quilt architecture memory. The active boundary portions may include support components to access both memory cells of neighbor- ing memory portions and memory cells overlying the active boundary portions. Address scrambling may produce a uniform increase in num- ber of available data in conjunction with the active boundary portions. El Core portion Boundary portion Control circuit portion FIG. 9 900
SG11201907532VA 2017-02-16 2017-08-30 Active boundary quilt architecture memory SG11201907532VA (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US15/434,401 US9792958B1 (en) 2017-02-16 2017-02-16 Active boundary quilt architecture memory
PCT/US2017/049441 WO2018151756A1 (en) 2017-02-16 2017-08-30 Active boundary quilt architecture memory

Publications (1)

Publication Number Publication Date
SG11201907532VA true SG11201907532VA (en) 2019-09-27

Family

ID=60021644

Family Applications (1)

Application Number Title Priority Date Filing Date
SG11201907532VA SG11201907532VA (en) 2017-02-16 2017-08-30 Active boundary quilt architecture memory

Country Status (8)

Country Link
US (4) US9792958B1 (en)
EP (1) EP3583600A4 (en)
JP (1) JP6982089B2 (en)
KR (3) KR102338201B1 (en)
CN (1) CN110291584B (en)
SG (1) SG11201907532VA (en)
TW (1) TWI635504B (en)
WO (1) WO2018151756A1 (en)

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Also Published As

Publication number Publication date
KR20190104642A (en) 2019-09-10
TWI635504B (en) 2018-09-11
CN110291584A (en) 2019-09-27
US9792958B1 (en) 2017-10-17
US20190103139A1 (en) 2019-04-04
TW201832229A (en) 2018-09-01
JP2020511778A (en) 2020-04-16
JP6982089B2 (en) 2021-12-17
US20180233177A1 (en) 2018-08-16
WO2018151756A1 (en) 2018-08-23
EP3583600A4 (en) 2020-12-02
US10157643B2 (en) 2018-12-18
EP3583600A1 (en) 2019-12-25
KR20220162815A (en) 2022-12-08
US11355162B2 (en) 2022-06-07
CN110291584B (en) 2023-07-18
US10818323B2 (en) 2020-10-27
KR102338201B1 (en) 2021-12-13
US20200395050A1 (en) 2020-12-17
KR20210152016A (en) 2021-12-14

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