SG11201801408YA - Method for producing bonded soi wafer - Google Patents

Method for producing bonded soi wafer

Info

Publication number
SG11201801408YA
SG11201801408YA SG11201801408YA SG11201801408YA SG11201801408YA SG 11201801408Y A SG11201801408Y A SG 11201801408YA SG 11201801408Y A SG11201801408Y A SG 11201801408YA SG 11201801408Y A SG11201801408Y A SG 11201801408YA SG 11201801408Y A SG11201801408Y A SG 11201801408YA
Authority
SG
Singapore
Prior art keywords
soi wafer
bonded soi
producing bonded
producing
wafer
Prior art date
Application number
SG11201801408YA
Inventor
Toru Ishizuka
Masatake Nakano
Original Assignee
Shin Etsu Handotai Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Shin Etsu Handotai Co Ltd filed Critical Shin Etsu Handotai Co Ltd
Publication of SG11201801408YA publication Critical patent/SG11201801408YA/en

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76251—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
    • H01L21/76254—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques with separation/delamination along an ion implanted layer, e.g. Smart-cut, Unibond
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/185—Joining of semiconductor bodies for junction formation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02002—Preparing wafers
    • H01L21/02005—Preparing bulk and homogeneous wafers
    • H01L21/02008—Multistep processes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/02227—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process
    • H01L21/0223—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by oxidation, e.g. oxidation of the substrate
    • H01L21/02233—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by oxidation, e.g. oxidation of the substrate of the semiconductor substrate or a semiconductor layer
    • H01L21/02236—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by oxidation, e.g. oxidation of the substrate of the semiconductor substrate or a semiconductor layer group IV semiconductor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02518—Deposited layers
    • H01L21/02521—Materials
    • H01L21/02551—Group 12/16 materials
    • H01L21/02554—Oxides
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02518—Deposited layers
    • H01L21/02587—Structure
    • H01L21/0259—Microstructure
    • H01L21/02598—Microstructure monocrystalline
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/322—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to modify their internal properties, e.g. to produce internal imperfections
    • H01L21/3221—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to modify their internal properties, e.g. to produce internal imperfections of silicon bodies, e.g. for gettering
    • H01L21/3226—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to modify their internal properties, e.g. to produce internal imperfections of silicon bodies, e.g. for gettering of silicon on insulator
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/324—Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1203—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body the substrate comprising an insulating body on a semiconductor body, e.g. SOI
    • C—CHEMISTRY; METALLURGY
    • C30—CRYSTAL GROWTH
    • C30B—SINGLE-CRYSTAL GROWTH; UNIDIRECTIONAL SOLIDIFICATION OF EUTECTIC MATERIAL OR UNIDIRECTIONAL DEMIXING OF EUTECTOID MATERIAL; REFINING BY ZONE-MELTING OF MATERIAL; PRODUCTION OF A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; SINGLE CRYSTALS OR HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; AFTER-TREATMENT OF SINGLE CRYSTALS OR A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; APPARATUS THEREFOR
    • C30B15/00—Single-crystal growth by pulling from a melt, e.g. Czochralski method
    • C30B15/007—Pulling on a substrate
    • C—CHEMISTRY; METALLURGY
    • C30—CRYSTAL GROWTH
    • C30B—SINGLE-CRYSTAL GROWTH; UNIDIRECTIONAL SOLIDIFICATION OF EUTECTIC MATERIAL OR UNIDIRECTIONAL DEMIXING OF EUTECTOID MATERIAL; REFINING BY ZONE-MELTING OF MATERIAL; PRODUCTION OF A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; SINGLE CRYSTALS OR HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; AFTER-TREATMENT OF SINGLE CRYSTALS OR A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; APPARATUS THEREFOR
    • C30B15/00—Single-crystal growth by pulling from a melt, e.g. Czochralski method
    • C30B15/20—Controlling or regulating
    • C—CHEMISTRY; METALLURGY
    • C30—CRYSTAL GROWTH
    • C30B—SINGLE-CRYSTAL GROWTH; UNIDIRECTIONAL SOLIDIFICATION OF EUTECTIC MATERIAL OR UNIDIRECTIONAL DEMIXING OF EUTECTOID MATERIAL; REFINING BY ZONE-MELTING OF MATERIAL; PRODUCTION OF A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; SINGLE CRYSTALS OR HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; AFTER-TREATMENT OF SINGLE CRYSTALS OR A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; APPARATUS THEREFOR
    • C30B29/00—Single crystals or homogeneous polycrystalline material with defined structure characterised by the material or by their shape
    • C30B29/02—Elements
    • C30B29/06—Silicon

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Manufacturing & Machinery (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Element Separation (AREA)
  • Crystals, And After-Treatments Of Crystals (AREA)
  • Formation Of Insulating Films (AREA)
SG11201801408YA 2015-09-28 2016-08-22 Method for producing bonded soi wafer SG11201801408YA (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2015189399A JP6447439B2 (en) 2015-09-28 2015-09-28 Manufacturing method of bonded SOI wafer
PCT/JP2016/003798 WO2017056376A1 (en) 2015-09-28 2016-08-22 Method for producing bonded soi wafer

Publications (1)

Publication Number Publication Date
SG11201801408YA true SG11201801408YA (en) 2018-03-28

Family

ID=58422873

Family Applications (1)

Application Number Title Priority Date Filing Date
SG11201801408YA SG11201801408YA (en) 2015-09-28 2016-08-22 Method for producing bonded soi wafer

Country Status (8)

Country Link
US (1) US11056381B2 (en)
EP (1) EP3358600B1 (en)
JP (1) JP6447439B2 (en)
KR (1) KR102509310B1 (en)
CN (1) CN108028170B (en)
SG (1) SG11201801408YA (en)
TW (1) TWI698907B (en)
WO (1) WO2017056376A1 (en)

Families Citing this family (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE102016112139B3 (en) * 2016-07-01 2018-01-04 Infineon Technologies Ag A method of reducing an impurity concentration in a semiconductor body
TWI668739B (en) * 2018-04-03 2019-08-11 環球晶圓股份有限公司 Epitaxy substrate and method of manufacturing the same
US10943813B2 (en) 2018-07-13 2021-03-09 Globalwafers Co., Ltd. Radio frequency silicon on insulator wafer platform with superior performance, stability, and manufacturability
JP7242220B2 (en) * 2018-09-03 2023-03-20 キヤノン株式会社 Bonded wafer, manufacturing method thereof, and through-hole forming method
KR102200437B1 (en) 2018-09-12 2021-01-08 주식회사 이피지 Method for manufacturing through hole electrode
JP7345245B2 (en) 2018-11-13 2023-09-15 信越半導体株式会社 Manufacturing method of bonded SOI wafer
FR3091010B1 (en) * 2018-12-24 2020-12-04 Soitec Silicon On Insulator SEMICONDUCTOR TYPE STRUCTURE FOR DIGITAL AND RADIO FREQUENCY APPLICATIONS, AND METHOD OF MANUFACTURING SUCH A STRUCTURE
US11932964B2 (en) 2019-04-05 2024-03-19 Tokuyama Coporation Polycrystalline silicon material
SG11202111070YA (en) 2019-04-05 2021-11-29 Tokuyama Corp Polycrystalline silicon material
FR3110282B1 (en) * 2020-05-18 2022-04-15 Soitec Silicon On Insulator Process for manufacturing a semiconductor-on-insulator substrate for radiofrequency applications
FR3110283B1 (en) * 2020-05-18 2022-04-15 Soitec Silicon On Insulator Process for manufacturing a semiconductor-on-insulator substrate for radio frequency applications

Family Cites Families (41)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH09331049A (en) * 1996-04-08 1997-12-22 Canon Inc Pasted soi substrate and its production
JP3697106B2 (en) * 1998-05-15 2005-09-21 キヤノン株式会社 Method for manufacturing semiconductor substrate and method for manufacturing semiconductor thin film
WO2000055397A1 (en) * 1999-03-16 2000-09-21 Shin-Etsu Handotai Co., Ltd. Production method for silicon wafer and silicon wafer
US6375738B1 (en) * 1999-03-26 2002-04-23 Canon Kabushiki Kaisha Process of producing semiconductor article
JP4463957B2 (en) * 2000-09-20 2010-05-19 信越半導体株式会社 Silicon wafer manufacturing method and silicon wafer
JP2002184960A (en) * 2000-12-18 2002-06-28 Shin Etsu Handotai Co Ltd Manufacturing method of soi wafer and soi wafer
US6743495B2 (en) * 2001-03-30 2004-06-01 Memc Electronic Materials, Inc. Thermal annealing process for producing silicon wafers with improved surface characteristics
JP2003068744A (en) * 2001-08-30 2003-03-07 Shin Etsu Handotai Co Ltd Silicon wafer manufacturing method, silicon wafer, and soi wafer
US7084046B2 (en) * 2001-11-29 2006-08-01 Shin-Etsu Handotai Co., Ltd. Method of fabricating SOI wafer
JP2003224247A (en) * 2002-01-29 2003-08-08 Shin Etsu Handotai Co Ltd Soi wafer and its manufacturing method
JP2005206391A (en) * 2004-01-20 2005-08-04 Shin Etsu Handotai Co Ltd Method for guaranteeing resistivity of silicon single crystal substrate, method for manufacturing silicon single crystal substrate, and silicon single crystal substrate
JP2006216826A (en) * 2005-02-04 2006-08-17 Sumco Corp Manufacturing method of soi wafer
JP2007059704A (en) * 2005-08-25 2007-03-08 Sumco Corp Method for manufacturing laminated board and laminated board
JP4715470B2 (en) * 2005-11-28 2011-07-06 株式会社Ｓｕｍｃｏ Release wafer reclaim processing method and release wafer regenerated by this method
JP2007227424A (en) * 2006-02-21 2007-09-06 Sumco Corp Production process of simox wafer
KR100701314B1 (en) 2006-12-05 2007-03-29 곽종보 A generator for lighting
JP4820801B2 (en) * 2006-12-26 2011-11-24 株式会社Ｓｕｍｃｏ Manufacturing method of bonded wafer
JP5045095B2 (en) * 2006-12-26 2012-10-10 信越半導体株式会社 Manufacturing method of semiconductor device
JP5009124B2 (en) * 2007-01-04 2012-08-22 コバレントマテリアル株式会社 Manufacturing method of semiconductor substrate
WO2008132895A1 (en) * 2007-04-20 2008-11-06 Semiconductor Energy Laboratory Co., Ltd. Method for manufacturing soi substrate and semiconductor device
JP5280015B2 (en) * 2007-05-07 2013-09-04 信越半導体株式会社 Manufacturing method of SOI substrate
JP5245380B2 (en) * 2007-06-21 2013-07-24 信越半導体株式会社 Manufacturing method of SOI wafer
JP5510256B2 (en) 2010-10-06 2014-06-04 株式会社Ｓｕｍｃｏ Silicon wafer manufacturing method
JP5993550B2 (en) 2011-03-08 2016-09-14 信越半導体株式会社 Manufacturing method of silicon single crystal wafer
US8846493B2 (en) * 2011-03-16 2014-09-30 Sunedison Semiconductor Limited Methods for producing silicon on insulator structures having high resistivity regions in the handle wafer
US9293329B2 (en) * 2011-04-06 2016-03-22 Isis Innovation Limited Processing a wafer for an electronic circuit
JP2014107357A (en) * 2012-11-26 2014-06-09 Shin Etsu Handotai Co Ltd Soi wafer manufacturing method
US9634098B2 (en) * 2013-06-11 2017-04-25 SunEdison Semiconductor Ltd. (UEN201334164H) Oxygen precipitation in heavily doped silicon wafers sliced from ingots grown by the Czochralski method
US9209069B2 (en) * 2013-10-15 2015-12-08 Sunedison Semiconductor Limited (Uen201334164H) Method of manufacturing high resistivity SOI substrate with reduced interface conductivity
US9768056B2 (en) * 2013-10-31 2017-09-19 Sunedison Semiconductor Limited (Uen201334164H) Method of manufacturing high resistivity SOI wafers with charge trapping layers based on terminated Si deposition
JP6118757B2 (en) * 2014-04-24 2017-04-19 信越半導体株式会社 Manufacturing method of bonded SOI wafer
EP3221884B1 (en) * 2014-11-18 2022-06-01 GlobalWafers Co., Ltd. High resistivity semiconductor-on-insulator wafers with charge trapping layers and method of manufacturing thereof
EP4170705A3 (en) * 2014-11-18 2023-10-18 GlobalWafers Co., Ltd. High resistivity semiconductor-on-insulator wafer and a method of manufacturing
JP6179530B2 (en) * 2015-01-23 2017-08-16 信越半導体株式会社 Manufacturing method of bonded SOI wafer
EP3266038B1 (en) * 2015-03-03 2019-09-25 GlobalWafers Co., Ltd. Method of depositing charge trapping polycrystalline silicon films on silicon substrates with controllable film stress
US9881832B2 (en) * 2015-03-17 2018-01-30 Sunedison Semiconductor Limited (Uen201334164H) Handle substrate for use in manufacture of semiconductor-on-insulator structure and method of manufacturing thereof
US10026642B2 (en) * 2016-03-07 2018-07-17 Sunedison Semiconductor Limited (Uen201334164H) Semiconductor on insulator structure comprising a sacrificial layer and method of manufacture thereof
US10269617B2 (en) * 2016-06-22 2019-04-23 Globalwafers Co., Ltd. High resistivity silicon-on-insulator substrate comprising an isolation region
SG10201913373WA (en) * 2016-10-26 2020-03-30 Globalwafers Co Ltd High resistivity silicon-on-insulator substrate having enhanced charge trapping efficiency
EP4009361A1 (en) * 2016-12-05 2022-06-08 GlobalWafers Co., Ltd. High resistivity silicon-on-insulator structure
US10453703B2 (en) * 2016-12-28 2019-10-22 Sunedison Semiconductor Limited (Uen201334164H) Method of treating silicon wafers to have intrinsic gettering and gate oxide integrity yield

Also Published As

Publication number Publication date
CN108028170A (en) 2018-05-11
EP3358600A4 (en) 2019-05-29
US11056381B2 (en) 2021-07-06
KR20180058713A (en) 2018-06-01
JP2017069240A (en) 2017-04-06
US20180247860A1 (en) 2018-08-30
WO2017056376A1 (en) 2017-04-06
EP3358600B1 (en) 2022-08-03
TWI698907B (en) 2020-07-11
KR102509310B1 (en) 2023-03-13
TW201721710A (en) 2017-06-16
JP6447439B2 (en) 2019-01-09
CN108028170B (en) 2022-03-15
EP3358600A1 (en) 2018-08-08

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