SG11201709392SA - Method for manufacturing bonded soi wafer - Google Patents

Method for manufacturing bonded soi wafer

Info

Publication number
SG11201709392SA
SG11201709392SA SG11201709392SA SG11201709392SA SG11201709392SA SG 11201709392S A SG11201709392S A SG 11201709392SA SG 11201709392S A SG11201709392S A SG 11201709392SA SG 11201709392S A SG11201709392S A SG 11201709392SA SG 11201709392S A SG11201709392S A SG 11201709392SA
Authority
SG
Singapore
Prior art keywords
soi wafer
bonded soi
manufacturing bonded
manufacturing
wafer
Prior art date
Application number
SG11201709392SA
Inventor
Norihiro Kobayashi
Osamu Ishikawa
Kenji Meguro
Taishi Wakabayashi
Hiroyuki Oonishi
Original Assignee
Shinetsu Handotai Kk
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Shinetsu Handotai Kk filed Critical Shinetsu Handotai Kk
Publication of SG11201709392SA publication Critical patent/SG11201709392SA/en

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/20—Deposition of semiconductor materials on a substrate, e.g. epitaxial growth solid phase epitaxy
    • H01L21/2003—Deposition of semiconductor materials on a substrate, e.g. epitaxial growth solid phase epitaxy characterised by the substrate
    • H01L21/2007—Bonding of semiconductor wafers to insulating substrates or to semiconducting substrates using an intermediate insulating layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02518—Deposited layers
    • H01L21/02521—Materials
    • H01L21/02524—Group 14 semiconducting materials
    • H01L21/02532—Silicon, silicon germanium, germanium
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02518—Deposited layers
    • H01L21/02587—Structure
    • H01L21/0259—Microstructure
    • H01L21/02595—Microstructure polycrystalline
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/31051—Planarisation of the insulating layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/322—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to modify their internal properties, e.g. to produce internal imperfections
    • H01L21/3221—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to modify their internal properties, e.g. to produce internal imperfections of silicon bodies, e.g. for gettering
    • H01L21/3226—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to modify their internal properties, e.g. to produce internal imperfections of silicon bodies, e.g. for gettering of silicon on insulator
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/324—Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76251—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
    • H01L21/76254—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques with separation/delamination along an ion implanted layer, e.g. Smart-cut, Unibond
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Manufacturing & Machinery (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Recrystallisation Techniques (AREA)
SG11201709392SA 2015-06-09 2016-03-14 Method for manufacturing bonded soi wafer SG11201709392SA (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2015116675A JP6353814B2 (en) 2015-06-09 2015-06-09 Manufacturing method of bonded SOI wafer
PCT/JP2016/001417 WO2016199329A1 (en) 2015-06-09 2016-03-14 Bonded soi wafer manufacturing method

Publications (1)

Publication Number Publication Date
SG11201709392SA true SG11201709392SA (en) 2017-12-28

Family

ID=57503158

Family Applications (1)

Application Number Title Priority Date Filing Date
SG11201709392SA SG11201709392SA (en) 2015-06-09 2016-03-14 Method for manufacturing bonded soi wafer

Country Status (8)

Country Link
US (1) US10566196B2 (en)
EP (1) EP3309819B1 (en)
JP (1) JP6353814B2 (en)
KR (1) KR102499512B1 (en)
CN (1) CN107533952B (en)
SG (1) SG11201709392SA (en)
TW (1) TWI692001B (en)
WO (1) WO2016199329A1 (en)

Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10269617B2 (en) * 2016-06-22 2019-04-23 Globalwafers Co., Ltd. High resistivity silicon-on-insulator substrate comprising an isolation region
JP6827442B2 (en) * 2018-06-14 2021-02-10 信越半導体株式会社 Manufacturing method of bonded SOI wafer and bonded SOI wafer
CN110943066A (en) * 2018-09-21 2020-03-31 联华电子股份有限公司 Semiconductor structure with high-resistance chip and bonding method of high-resistance chip
FR3098642B1 (en) 2019-07-12 2021-06-11 Soitec Silicon On Insulator method of manufacturing a structure comprising a thin layer transferred to a support provided with a charge trapping layer
FR3129028B1 (en) * 2021-11-09 2023-11-10 Soitec Silicon On Insulator METHOD FOR PREPARING A SUPPORT SUBSTRATE PROVIDED WITH A CHARGE TRAPPING LAYER
FR3129029B1 (en) * 2021-11-09 2023-09-29 Soitec Silicon On Insulator METHOD FOR PREPARING A SUPPORT SUBSTRATE PROVIDED WITH A CHARGE TRAPPING LAYER
JP7529000B2 (en) 2022-11-15 2024-08-06 株式会社Sumco Manufacturing method of laminated wafer

Family Cites Families (20)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0719839B2 (en) * 1989-10-18 1995-03-06 株式会社東芝 Method for manufacturing semiconductor substrate
JP2766417B2 (en) * 1992-02-10 1998-06-18 三菱マテリアル株式会社 Manufacturing method of bonded dielectric separation wafer
JP3391184B2 (en) * 1996-03-28 2003-03-31 信越半導体株式会社 Silicon wafer and method for manufacturing the same
US6171982B1 (en) * 1997-12-26 2001-01-09 Canon Kabushiki Kaisha Method and apparatus for heat-treating an SOI substrate and method of preparing an SOI substrate by using the same
US6815774B1 (en) * 1998-10-29 2004-11-09 Mitsubishi Materials Silicon Corporation Dielectrically separated wafer and method of the same
US7667283B1 (en) * 2003-06-06 2010-02-23 Northrop Grumman Systems Corporation Coiled circuit camera
KR20050013398A (en) * 2003-07-28 2005-02-04 주식회사 실트론 A Producing Method For Silicon Single Crystal Wafer and Silicon On Insulator Wafer
EP1665367A2 (en) 2003-09-26 2006-06-07 Universite Catholique De Louvain Method of manufacturing a multilayer semiconductor structure with reduced ohmic losses
FR2860341B1 (en) * 2003-09-26 2005-12-30 Soitec Silicon On Insulator METHOD FOR MANUFACTURING LOWERED LOWER MULTILAYER STRUCTURE
US7910455B2 (en) 2006-04-27 2011-03-22 Shin-Etsu Handotai Co., Ltd. Method for producing SOI wafer
JP5185284B2 (en) 2006-12-26 2013-04-17 ソイテック Method for manufacturing a semiconductor on insulator structure
JP5532680B2 (en) 2009-05-27 2014-06-25 信越半導体株式会社 Manufacturing method of SOI wafer and SOI wafer
FR2953640B1 (en) * 2009-12-04 2012-02-10 S O I Tec Silicon On Insulator Tech METHOD FOR MANUFACTURING A SEMICONDUCTOR TYPE STRUCTURE ON INSULATION, WITH REDUCED ELECTRICAL LOSSES AND CORRESPONDING STRUCTURE
JP5673170B2 (en) * 2011-02-09 2015-02-18 信越半導体株式会社 Bonded substrate, method for manufacturing bonded substrate, semiconductor device, and method for manufacturing semiconductor device
FR2973159B1 (en) 2011-03-22 2013-04-19 Soitec Silicon On Insulator METHOD FOR MANUFACTURING BASE SUBSTRATE
FR2973158B1 (en) * 2011-03-22 2014-02-28 Soitec Silicon On Insulator METHOD FOR MANUFACTURING SEMICONDUCTOR-TYPE SUBSTRATE ON INSULATION FOR RADIO FREQUENCY APPLICATIONS
JP5821828B2 (en) * 2012-11-21 2015-11-24 信越半導体株式会社 Manufacturing method of SOI wafer
JP6070487B2 (en) * 2013-09-04 2017-02-01 信越半導体株式会社 SOI wafer manufacturing method, SOI wafer, and semiconductor device
JP5942948B2 (en) * 2013-09-17 2016-06-29 信越半導体株式会社 Manufacturing method of SOI wafer and bonded SOI wafer
JP6118757B2 (en) * 2014-04-24 2017-04-19 信越半導体株式会社 Manufacturing method of bonded SOI wafer

Also Published As

Publication number Publication date
JP6353814B2 (en) 2018-07-04
CN107533952A (en) 2018-01-02
US10566196B2 (en) 2020-02-18
TWI692001B (en) 2020-04-21
EP3309819B1 (en) 2022-05-04
WO2016199329A1 (en) 2016-12-15
EP3309819A4 (en) 2019-02-06
KR102499512B1 (en) 2023-02-14
US20180122639A1 (en) 2018-05-03
KR20180015634A (en) 2018-02-13
TW201711086A (en) 2017-03-16
EP3309819A1 (en) 2018-04-18
CN107533952B (en) 2020-08-21
JP2017005078A (en) 2017-01-05

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