SG107099A1 - Memory cell, memory circuit block, data writing and data reading method - Google Patents

Memory cell, memory circuit block, data writing and data reading method

Info

Publication number
SG107099A1
SG107099A1 SG200202676A SG200202676A SG107099A1 SG 107099 A1 SG107099 A1 SG 107099A1 SG 200202676 A SG200202676 A SG 200202676A SG 200202676 A SG200202676 A SG 200202676A SG 107099 A1 SG107099 A1 SG 107099A1
Authority
SG
Singapore
Prior art keywords
circuit block
reading method
data
memory cell
memory
Prior art date
Application number
SG200202676A
Other languages
English (en)
Inventor
Miyatake Hisatada
Sunaga Toshio
Kitamura Kohji
Original Assignee
Ibm
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Ibm filed Critical Ibm
Publication of SG107099A1 publication Critical patent/SG107099A1/en

Links

Classifications

    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B82—NANOTECHNOLOGY
    • B82Y—SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES
    • B82Y10/00—Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/02—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements
    • G11C11/16—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements using elements in which the storage effect is based on magnetic spin effect
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/02—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements
    • G11C11/16—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements using elements in which the storage effect is based on magnetic spin effect
    • G11C11/165—Auxiliary circuits
    • G11C11/1653—Address circuits or decoders
    • G11C11/1657—Word-line or row circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/02—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements
    • G11C11/16—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements using elements in which the storage effect is based on magnetic spin effect
    • G11C11/165—Auxiliary circuits
    • G11C11/1673—Reading or sensing circuits or methods
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/02—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements
    • G11C11/16—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements using elements in which the storage effect is based on magnetic spin effect
    • G11C11/165—Auxiliary circuits
    • G11C11/1675—Writing or programming circuits or methods
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B61/00—Magnetic memory devices, e.g. magnetoresistive RAM [MRAM] devices
    • H10B61/20—Magnetic memory devices, e.g. magnetoresistive RAM [MRAM] devices comprising components having three or more electrodes, e.g. transistors
    • H10B61/22—Magnetic memory devices, e.g. magnetoresistive RAM [MRAM] devices comprising components having three or more electrodes, e.g. transistors of the field-effect transistor [FET] type

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Chemical & Material Sciences (AREA)
  • Nanotechnology (AREA)
  • Physics & Mathematics (AREA)
  • Mathematical Physics (AREA)
  • Theoretical Computer Science (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Mram Or Spin Memory Techniques (AREA)
  • Hall/Mr Elements (AREA)
  • Semiconductor Memories (AREA)
SG200202676A 2001-05-30 2002-05-06 Memory cell, memory circuit block, data writing and data reading method SG107099A1 (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2001161718A JP2002368196A (ja) 2001-05-30 2001-05-30 メモリセル、記憶回路ブロック、データの書き込み方法及びデータの読み出し方法

Publications (1)

Publication Number Publication Date
SG107099A1 true SG107099A1 (en) 2004-11-29

Family

ID=19004951

Family Applications (1)

Application Number Title Priority Date Filing Date
SG200202676A SG107099A1 (en) 2001-05-30 2002-05-06 Memory cell, memory circuit block, data writing and data reading method

Country Status (3)

Country Link
US (1) US6842361B2 (ja)
JP (1) JP2002368196A (ja)
SG (1) SG107099A1 (ja)

Families Citing this family (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2004071897A (ja) * 2002-08-07 2004-03-04 Sony Corp 磁気抵抗効果素子及び磁気メモリ装置
KR100615089B1 (ko) * 2004-07-14 2006-08-23 삼성전자주식회사 낮은 구동 전류를 갖는 자기 램
US7369428B2 (en) * 2003-09-29 2008-05-06 Samsung Electronics Co., Ltd. Methods of operating a magnetic random access memory device and related devices and structures
US7372722B2 (en) * 2003-09-29 2008-05-13 Samsung Electronics Co., Ltd. Methods of operating magnetic random access memory devices including heat-generating structures
US7031183B2 (en) * 2003-12-08 2006-04-18 Freescale Semiconductor, Inc. MRAM device integrated with other types of circuitry
JP4819316B2 (ja) * 2004-02-23 2011-11-24 ルネサスエレクトロニクス株式会社 半導体装置
JP4569231B2 (ja) * 2004-09-07 2010-10-27 Ｔｄｋ株式会社 磁気メモリ及びその製造方法
US7608538B2 (en) * 2007-01-05 2009-10-27 International Business Machines Corporation Formation of vertical devices by electroplating
US8077508B1 (en) * 2009-08-19 2011-12-13 Grandis, Inc. Dynamic multistate memory write driver
US9099181B2 (en) 2009-08-19 2015-08-04 Grandis, Inc. Non-volatile static ram cell circuit and timing method
US8315090B2 (en) 2010-06-07 2012-11-20 Grandis, Inc. Pseudo page mode memory architecture and method
US8625339B2 (en) 2011-04-11 2014-01-07 Grandis, Inc. Multi-cell per memory-bit circuit and method
US8077501B2 (en) * 2009-09-11 2011-12-13 Grandis, Inc. Differential read and write architecture
US8456926B2 (en) 2010-11-18 2013-06-04 Grandis, Inc. Memory write error correction circuit
US8723557B2 (en) 2010-06-07 2014-05-13 Grandis, Inc. Multi-supply symmetric driver circuit and timing method
JP5116816B2 (ja) * 2010-07-28 2013-01-09 ルネサスエレクトロニクス株式会社 半導体集積回路装置および磁気メモリ装置

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5734605A (en) * 1996-09-10 1998-03-31 Motorola, Inc. Multi-layer magnetic tunneling junction memory cells
JP2003017662A (ja) * 2001-06-27 2003-01-17 Internatl Business Mach Corp <Ibm> メモリセル、記憶回路ブロック及びデータの書き込み方法

Family Cites Families (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5640343A (en) * 1996-03-18 1997-06-17 International Business Machines Corporation Magnetic memory array using magnetic tunnel junction devices in the memory cells
US6256224B1 (en) * 2000-05-03 2001-07-03 Hewlett-Packard Co Write circuit for large MRAM arrays
US6130835A (en) * 1997-12-02 2000-10-10 International Business Machines Corporation Voltage biasing for magnetic RAM with magnetic tunnel memory cells
US5991193A (en) * 1997-12-02 1999-11-23 International Business Machines Corporation Voltage biasing for magnetic ram with magnetic tunnel memory cells
US6034887A (en) * 1998-08-05 2000-03-07 International Business Machines Corporation Non-volatile magnetic memory cell and devices
US6005800A (en) * 1998-11-23 1999-12-21 International Business Machines Corporation Magnetic memory array with paired asymmetric memory cells for improved write margin
JP3741258B2 (ja) * 2000-03-31 2006-02-01 シャープ株式会社 半導体記憶装置およびその救済方法
US6269018B1 (en) * 2000-04-13 2001-07-31 International Business Machines Corporation Magnetic random access memory using current through MTJ write mechanism
US6324093B1 (en) * 2000-09-15 2001-11-27 Hewlett-Packard Company Write-once thin-film memory
JP4656720B2 (ja) * 2000-09-25 2011-03-23 ルネサスエレクトロニクス株式会社 薄膜磁性体記憶装置
JP4726290B2 (ja) * 2000-10-17 2011-07-20 ルネサスエレクトロニクス株式会社 半導体集積回路
JP4726292B2 (ja) * 2000-11-14 2011-07-20 ルネサスエレクトロニクス株式会社 薄膜磁性体記憶装置
JP4667594B2 (ja) * 2000-12-25 2011-04-13 ルネサスエレクトロニクス株式会社 薄膜磁性体記憶装置
US6603678B2 (en) * 2001-01-11 2003-08-05 Hewlett-Packard Development Company, L.P. Thermally-assisted switching of magnetic memory elements

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5734605A (en) * 1996-09-10 1998-03-31 Motorola, Inc. Multi-layer magnetic tunneling junction memory cells
JP2003017662A (ja) * 2001-06-27 2003-01-17 Internatl Business Mach Corp <Ibm> メモリセル、記憶回路ブロック及びデータの書き込み方法

Also Published As

Publication number Publication date
US20030081454A1 (en) 2003-05-01
US6842361B2 (en) 2005-01-11
JP2002368196A (ja) 2002-12-20

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