NL8802934A - Geheugen met een bitlijnbelastingsschakeling van variabele impedantiewaarde. - Google Patents

Geheugen met een bitlijnbelastingsschakeling van variabele impedantiewaarde. Download PDF

Info

Publication number
NL8802934A
NL8802934A NL8802934A NL8802934A NL8802934A NL 8802934 A NL8802934 A NL 8802934A NL 8802934 A NL8802934 A NL 8802934A NL 8802934 A NL8802934 A NL 8802934A NL 8802934 A NL8802934 A NL 8802934A
Authority
NL
Netherlands
Prior art keywords
transistor
type
pmos
transistors
electrode
Prior art date
Application number
NL8802934A
Other languages
English (en)
Dutch (nl)
Original Assignee
Sony Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from JP62299084A external-priority patent/JPH01140491A/ja
Priority claimed from JP62301365A external-priority patent/JPH01143096A/ja
Application filed by Sony Corp filed Critical Sony Corp
Publication of NL8802934A publication Critical patent/NL8802934A/nl

Links

Classifications

    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C11/00Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/41Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
    • G11C11/413Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction
    • G11C11/417Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction for memory cells of the field-effect type
    • G11C11/419Read-write [R-W] circuits

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Static Random-Access Memory (AREA)
NL8802934A 1987-11-27 1988-11-28 Geheugen met een bitlijnbelastingsschakeling van variabele impedantiewaarde. NL8802934A (nl)

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
JP62299084A JPH01140491A (ja) 1987-11-27 1987-11-27 メモリ装置
JP29908487 1987-11-27
JP62301365A JPH01143096A (ja) 1987-11-28 1987-11-28 メモリ装置
JP30136587 1987-11-28

Publications (1)

Publication Number Publication Date
NL8802934A true NL8802934A (nl) 1989-06-16

Family

ID=26561781

Family Applications (1)

Application Number Title Priority Date Filing Date
NL8802934A NL8802934A (nl) 1987-11-27 1988-11-28 Geheugen met een bitlijnbelastingsschakeling van variabele impedantiewaarde.

Country Status (4)

Country Link
US (1) US5075891A (fr)
FR (1) FR2623932B1 (fr)
GB (1) GB2213009B (fr)
NL (1) NL8802934A (fr)

Families Citing this family (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5182726A (en) * 1991-01-23 1993-01-26 Texas Instruments Incorporated Circuit and method for discharging a memory array
WO1992022070A1 (fr) * 1991-05-30 1992-12-10 Integrated Device Technology, Inc. Memoire statiques et procedes de lecture de memoires statiques
US5228106A (en) * 1991-05-30 1993-07-13 Integrated Device Technology, Inc. Track-and-regenerate amplifiers and memories using such amplifiers
JP3176985B2 (ja) * 1992-05-27 2001-06-18 株式会社東芝 半導体メモリ
US5508964A (en) * 1993-01-08 1996-04-16 Texas Instruments Incorporated Write recovery time minimization for Bi-CMOS SRAM
EP0936627B1 (fr) 1998-02-13 2004-10-20 STMicroelectronics S.r.l. Amplificateur de détection pour mémoire non volatile à basse tension
CA2613400C (fr) * 2005-06-24 2014-08-26 The Flewelling Ford Family Trust Procede et dispositif d'abaissement d'impedance d'un transistor a effet de champ
US7436696B2 (en) * 2006-04-28 2008-10-14 Taiwan Semiconductor Manufacturing Company, Ltd. Read-preferred SRAM cell design
US9094277B2 (en) * 2011-09-07 2015-07-28 Viasat, Inc. Digital compensation technique using area efficient tri-state architecture

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5951072B2 (ja) * 1979-02-26 1984-12-12 日本電気株式会社 半導体メモリ装置
JPS6027114B2 (ja) * 1980-07-24 1985-06-27 日本電気株式会社 メモリ装置
US4791613A (en) * 1983-09-21 1988-12-13 Inmos Corporation Bit line and column circuitry used in a semiconductor memory
US4636983A (en) * 1984-12-20 1987-01-13 Cypress Semiconductor Corp. Memory array biasing circuit for high speed CMOS device
US4730279A (en) * 1985-03-30 1988-03-08 Kabushiki Kaisha Toshiba Static semiconductor memory device
GB2176357B (en) * 1985-06-12 1989-07-12 Stc Plc Improvements in semiconductor memories
JPH0640439B2 (ja) * 1986-02-17 1994-05-25 日本電気株式会社 半導体記憶装置
JPS62200595A (ja) * 1986-02-26 1987-09-04 Sony Corp メモリ装置

Also Published As

Publication number Publication date
GB2213009B (en) 1992-02-05
FR2623932A1 (fr) 1989-06-02
FR2623932B1 (fr) 1993-10-15
GB8827224D0 (en) 1988-12-29
US5075891A (en) 1991-12-24
GB2213009A (en) 1989-08-02

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BC A request for examination has been filed
BV The patent application has lapsed