NL174413B - Werkwijze voor het op een dragerlichaam vormen van een verbindingspatroon, dat ten minste twee boven elkaar liggende, elektrisch geisoleerde geleiderpatronen omvat. - Google Patents

Werkwijze voor het op een dragerlichaam vormen van een verbindingspatroon, dat ten minste twee boven elkaar liggende, elektrisch geisoleerde geleiderpatronen omvat.

Info

Publication number
NL174413B
NL174413B NLAANVRAGE7108656,A NL7108656A NL174413B NL 174413 B NL174413 B NL 174413B NL 7108656 A NL7108656 A NL 7108656A NL 174413 B NL174413 B NL 174413B
Authority
NL
Netherlands
Prior art keywords
cartridges
forming
electrically insulated
body including
carrier body
Prior art date
Application number
NLAANVRAGE7108656,A
Other languages
English (en)
Other versions
NL7108656A (nl
NL174413C (nl
Inventor
G E Smith
Original Assignee
Western Electric Co
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Western Electric Co filed Critical Western Electric Co
Publication of NL7108656A publication Critical patent/NL7108656A/xx
Publication of NL174413B publication Critical patent/NL174413B/nl
Application granted granted Critical
Publication of NL174413C publication Critical patent/NL174413C/nl

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/52Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321After treatment
    • H01L21/3213Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
    • H01L21/32133Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only
    • H01L21/32134Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by liquid etching only
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/7684Smoothing; Planarisation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/48Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/482Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of lead-in layers inseparably applied to the semiconductor body
    • H01L23/485Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of lead-in layers inseparably applied to the semiconductor body consisting of layered constructions comprising conductive layers and insulating layers, e.g. planar contacts
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10NELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N97/00Electric solid-state thin-film or thick-film devices, not otherwise provided for
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001Technical content checked by a classifier
    • H01L2924/0002Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10STECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00Metal treatment
    • Y10S148/041Doping control in crystal growth
    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10STECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00Metal treatment
    • Y10S148/042Doping, graded, for tapered etching
    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10STECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00Metal treatment
    • Y10S148/049Equivalence and options
    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10STECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00Metal treatment
    • Y10S148/051Etching
    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10STECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00Metal treatment
    • Y10S148/067Graded energy gap
    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10STECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00Metal treatment
    • Y10S148/122Polycrystalline

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Chemical & Material Sciences (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • General Chemical & Material Sciences (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Weting (AREA)
NLAANVRAGE7108656,A 1970-06-29 1971-06-23 Werkwijze voor het op een dragerlichaam vormen van een verbindingspatroon, dat ten minste twee boven elkaar liggende, elektrisch geisoleerde geleiderpatronen omvat. NL174413C (nl)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US5078070A 1970-06-29 1970-06-29

Publications (3)

Publication Number Publication Date
NL7108656A NL7108656A (nl) 1971-12-31
NL174413B true NL174413B (nl) 1984-01-02
NL174413C NL174413C (nl) 1984-06-01

Family

ID=21967382

Family Applications (1)

Application Number Title Priority Date Filing Date
NLAANVRAGE7108656,A NL174413C (nl) 1970-06-29 1971-06-23 Werkwijze voor het op een dragerlichaam vormen van een verbindingspatroon, dat ten minste twee boven elkaar liggende, elektrisch geisoleerde geleiderpatronen omvat.

Country Status (9)

Country Link
US (1) US3675319A (nl)
JP (1) JPS557018B1 (nl)
BE (1) BE768899A (nl)
CA (1) CA922425A (nl)
DE (1) DE2132099C3 (nl)
FR (1) FR2096566B1 (nl)
GB (1) GB1348731A (nl)
NL (1) NL174413C (nl)
SE (1) SE373983B (nl)

Families Citing this family (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3936331A (en) * 1974-04-01 1976-02-03 Fairchild Camera And Instrument Corporation Process for forming sloped topography contact areas between polycrystalline silicon and single-crystal silicon
GB1501114A (en) * 1974-04-25 1978-02-15 Rca Corp Method of making a semiconductor device
US4181564A (en) * 1978-04-24 1980-01-01 Bell Telephone Laboratories, Incorporated Fabrication of patterned silicon nitride insulating layers having gently sloping sidewalls
US4354309A (en) * 1978-12-29 1982-10-19 International Business Machines Corp. Method of manufacturing a metal-insulator-semiconductor device utilizing a graded deposition of polycrystalline silicon
US5285571A (en) * 1992-10-13 1994-02-15 General Electric Company Method for extending an electrical conductor over an edge of an HDI substrate
DE19649972C2 (de) * 1996-11-22 2002-11-07 Siemens Ag Verfahren zur Herstellung eines Leitungssatzes für Kraftfahrzeuge
US20140264340A1 (en) * 2013-03-14 2014-09-18 Sandia Corporation Reversible hybridization of large surface area array electronics
US9905471B2 (en) * 2016-04-28 2018-02-27 Taiwan Semiconductor Manufacturing Co., Ltd. Integrated circuit structure and method forming trenches with different depths

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3260634A (en) * 1961-02-17 1966-07-12 Motorola Inc Method of etching a semiconductor wafer to provide tapered dice
NL285523A (nl) * 1961-11-24
FR1379429A (fr) * 1963-01-31 1964-11-20 Motorola Inc Procédé d'isolement électrique pour circuits miniaturisés
DE1564896A1 (de) * 1966-08-30 1970-01-08 Telefunken Patent Halbleiteranordnung
BE758160A (fr) * 1969-10-31 1971-04-01 Fairchild Camera Instr Co Structure metallique a couches multiples et procede de fabrication d'une telle structure
JPS563951B2 (nl) * 1973-05-15 1981-01-28

Also Published As

Publication number Publication date
NL7108656A (nl) 1971-12-31
BE768899A (fr) 1971-11-03
DE2132099B2 (de) 1979-10-11
FR2096566B1 (nl) 1975-02-07
US3675319A (en) 1972-07-11
DE2132099A1 (de) 1972-01-05
SE373983B (nl) 1975-02-17
NL174413C (nl) 1984-06-01
GB1348731A (en) 1974-03-20
JPS557018B1 (nl) 1980-02-21
CA922425A (en) 1973-03-06
DE2132099C3 (de) 1983-12-01
FR2096566A1 (nl) 1972-02-18

Similar Documents

Publication Publication Date Title
NL155779B (nl) Drager voor langwerpige voorwerpen, die ieder van een flens zijn voorzien.
NL173075B (nl) Werkwijze voor het vervaardigen van een koolstofhoudende pekdraad en desgewenst een koolstofdraad.
NL178382C (nl) Werkwijze voor het vervaardigen van een gedrukte schakeling op een geisoleerde basisplaat.
NL172388B (nl) Werkwijze voor het vormen van elektrisch geleidende banen op het oppervlak van een drager.
NL170485C (nl) Werkwijze voor het vervaardigen van een gelaagde dragerplaat, voorzien van twee of meer boven elkaar aangebrachte geleiderpatronen.
NL7514558A (nl) Geheugensysteem voor elektrische informatie.
NL7610673A (nl) Werkwijze voor het bereiden van een elektrisch geleidend thermoplastisch elastomeer.
NL187098C (nl) Werkwijze ter vervaardiging van een geexpandeerd, suikervrij, halfvochtig huisdierenvoeder.
NL172378C (nl) Werkwijze voor het testen van een programmeerbaar gegevenscommunicatie-eindstation.
NL164142B (nl) Werkwijze voor het vormen van een hologram.
NL163454B (nl) Werkwijze voor het vervaardigen van een mechanisch stijve, gasdichte verpakkingshouder.
NL174413C (nl) Werkwijze voor het op een dragerlichaam vormen van een verbindingspatroon, dat ten minste twee boven elkaar liggende, elektrisch geisoleerde geleiderpatronen omvat.
NL178462C (nl) Halfgeleiderinrichting, omvattende een halfgeleiderlichaam met ten minste een kruising tussen twee van elkaar geisoleerde elektrische verbindingen.
NL177887C (nl) Werkwijze voor het vervaardigen van een tabaksfolie.
NL164098C (nl) Werkwijze ter vervaardiging van een elektrode voor elektrochemische processen.
NL181447C (nl) Verbindingsstuk voor het vormen van een knooppunt.
ES197325Y (es) Conjunto electrico para vehiculos.
NL170444C (nl) Werkwijze voor het vervaardigen van draden, die een complexvormende binding bevatten.
NL147371B (nl) Elektrisch bedienbaar schuifdak voor een voertuig.
NL162420C (nl) Werkwijze voor het bekleden van een geleidend substraat.
NL166411C (nl) Werkwijze voor het bereiden van gesulfideerde platina-op-koolstof-katalysatoren.
NL176817C (nl) Werkwijze voor het vervaardigen van een elektrisch contactorgaan.
NL167139B (nl) Werkwijze voor het vervaardigen van een doorzichtige geleider.
NL180483B (nl) Werkwijze voor het regenereren van een katalysator, die iridium op een drager bevat.
NL170894C (nl) Werkwijze voor het vervaardigen van een hologram.

Legal Events

Date Code Title Description
BC A request for examination has been filed
V4 Discontinued because of reaching the maximum lifetime of a patent