NL1006162C2 - Werkwijze voor het vervaardigen van een geïntegreerde keten met geleiderstructuren. - Google Patents

Werkwijze voor het vervaardigen van een geïntegreerde keten met geleiderstructuren. Download PDF

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Publication number
NL1006162C2
NL1006162C2 NL1006162A NL1006162A NL1006162C2 NL 1006162 C2 NL1006162 C2 NL 1006162C2 NL 1006162 A NL1006162 A NL 1006162A NL 1006162 A NL1006162 A NL 1006162A NL 1006162 C2 NL1006162 C2 NL 1006162C2
Authority
NL
Netherlands
Prior art keywords
layer
openings
etch stop
etching
stop layer
Prior art date
Application number
NL1006162A
Other languages
English (en)
Dutch (nl)
Inventor
Tri-Rung Yew
Water Lur
Shih-Wei Sun
Mong-Chung Liu
Original Assignee
United Microelectronics Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority to GB9709431A priority Critical patent/GB2325083B/en
Priority to DE19719909A priority patent/DE19719909A1/de
Priority to FR9705992A priority patent/FR2763424B1/fr
Application filed by United Microelectronics Corp filed Critical United Microelectronics Corp
Priority to NL1006162A priority patent/NL1006162C2/nl
Priority to JP9140353A priority patent/JPH10335456A/ja
Priority to US08/873,500 priority patent/US5801094A/en
Priority claimed from US08/873,500 external-priority patent/US5801094A/en
Application granted granted Critical
Publication of NL1006162C2 publication Critical patent/NL1006162C2/nl

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H01L21/76807—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures
    • H01L21/7681—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures involving one or more buried masks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H01L21/76804—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics by forming tapered via holes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Electrodes Of Semiconductors (AREA)
NL1006162A 1997-02-28 1997-05-29 Werkwijze voor het vervaardigen van een geïntegreerde keten met geleiderstructuren. NL1006162C2 (nl)

Priority Applications (6)

Application Number Priority Date Filing Date Title
GB9709431A GB2325083B (en) 1997-05-09 1997-05-09 A dual damascene process
DE19719909A DE19719909A1 (de) 1997-05-09 1997-05-13 Zweifaches Damaszierverfahren
FR9705992A FR2763424B1 (fr) 1997-05-09 1997-05-15 Processus de damasquinage double
NL1006162A NL1006162C2 (nl) 1997-05-09 1997-05-29 Werkwijze voor het vervaardigen van een geïntegreerde keten met geleiderstructuren.
JP9140353A JPH10335456A (ja) 1997-05-09 1997-05-29 集積回路の製造方法
US08/873,500 US5801094A (en) 1997-02-28 1997-06-12 Dual damascene process

Applications Claiming Priority (12)

Application Number Priority Date Filing Date Title
GB9709431 1997-05-09
GB9709431A GB2325083B (en) 1997-05-09 1997-05-09 A dual damascene process
DE19719909 1997-05-13
DE19719909A DE19719909A1 (de) 1997-05-09 1997-05-13 Zweifaches Damaszierverfahren
FR9705992 1997-05-15
FR9705992A FR2763424B1 (fr) 1997-05-09 1997-05-15 Processus de damasquinage double
NL1006162 1997-05-29
JP14035397 1997-05-29
NL1006162A NL1006162C2 (nl) 1997-05-09 1997-05-29 Werkwijze voor het vervaardigen van een geïntegreerde keten met geleiderstructuren.
JP9140353A JPH10335456A (ja) 1997-05-09 1997-05-29 集積回路の製造方法
US08/873,500 US5801094A (en) 1997-02-28 1997-06-12 Dual damascene process
US87350097 1997-06-12

Publications (1)

Publication Number Publication Date
NL1006162C2 true NL1006162C2 (nl) 1998-12-01

Family

ID=27545067

Family Applications (1)

Application Number Title Priority Date Filing Date
NL1006162A NL1006162C2 (nl) 1997-02-28 1997-05-29 Werkwijze voor het vervaardigen van een geïntegreerde keten met geleiderstructuren.

Country Status (5)

Country Link
JP (1) JPH10335456A (de)
DE (1) DE19719909A1 (de)
FR (1) FR2763424B1 (de)
GB (1) GB2325083B (de)
NL (1) NL1006162C2 (de)

Families Citing this family (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6346454B1 (en) * 1999-01-12 2002-02-12 Agere Systems Guardian Corp. Method of making dual damascene interconnect structure and metal electrode capacitor
JP2000216247A (ja) * 1999-01-22 2000-08-04 Nec Corp 半導体装置及びその製造方法
JP3502288B2 (ja) * 1999-03-19 2004-03-02 富士通株式会社 半導体装置およびその製造方法
US6313025B1 (en) * 1999-08-30 2001-11-06 Agere Systems Guardian Corp. Process for manufacturing an integrated circuit including a dual-damascene structure and an integrated circuit
JP4858895B2 (ja) * 2000-07-21 2012-01-18 富士通セミコンダクター株式会社 半導体装置の製造方法
KR100368320B1 (ko) * 2000-12-28 2003-01-24 주식회사 하이닉스반도체 반도체 소자의 금속 배선 형성 방법
JP2011077468A (ja) * 2009-10-02 2011-04-14 Panasonic Corp 半導体装置の製造方法および半導体装置
JP5104924B2 (ja) * 2010-08-23 2012-12-19 富士通セミコンダクター株式会社 半導体装置
JP5891846B2 (ja) * 2012-02-24 2016-03-23 富士通セミコンダクター株式会社 半導体装置の製造方法
JP6853663B2 (ja) * 2015-12-28 2021-03-31 株式会社半導体エネルギー研究所 半導体装置

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0224013A2 (de) * 1985-10-28 1987-06-03 International Business Machines Corporation Verfahren zur Herstellung koplanarer Viellagen-Metall-Isolator-Schichten auf einem Substrat
EP0555032A1 (de) * 1992-02-06 1993-08-11 STMicroelectronics, Inc. Halbleiter-Kontaktöffnungsstruktur und -verfahren
WO1996012297A2 (en) * 1994-10-11 1996-04-25 Advanced Micro Devices, Inc. Simplified dual damascene process for multilevel metallization and interconnection structure

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH03198327A (ja) * 1989-12-26 1991-08-29 Fujitsu Ltd 半導体装置の製造方法
US5466639A (en) * 1994-10-06 1995-11-14 Micron Semiconductor, Inc. Double mask process for forming trenches and contacts during the formation of a semiconductor memory device
US5801094A (en) * 1997-02-28 1998-09-01 United Microelectronics Corporation Dual damascene process

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0224013A2 (de) * 1985-10-28 1987-06-03 International Business Machines Corporation Verfahren zur Herstellung koplanarer Viellagen-Metall-Isolator-Schichten auf einem Substrat
EP0555032A1 (de) * 1992-02-06 1993-08-11 STMicroelectronics, Inc. Halbleiter-Kontaktöffnungsstruktur und -verfahren
WO1996012297A2 (en) * 1994-10-11 1996-04-25 Advanced Micro Devices, Inc. Simplified dual damascene process for multilevel metallization and interconnection structure

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
H.M.DALAL ET AL.: "METHODS OF OPENING CONTACT HOLES IN OXIDE-NITRIDE STRUCTURE", IBM TECHNICAL DISCLOSURE BULLETIN, vol. 24, no. 9, February 1982 (1982-02-01), N.Y USA, pages 4728 - 4729, XP002049435 *

Also Published As

Publication number Publication date
JPH10335456A (ja) 1998-12-18
GB2325083B (en) 1999-04-14
FR2763424A1 (fr) 1998-11-20
FR2763424B1 (fr) 2003-06-27
DE19719909A1 (de) 1998-11-19
GB9709431D0 (en) 1997-07-02
GB2325083A (en) 1998-11-11

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