MX9502241A - Dispositivo semiconductor de memoria para obtener un ancho de banda grande o alto y metodo para arreglar las lineas de señales para el mismo. - Google Patents

Dispositivo semiconductor de memoria para obtener un ancho de banda grande o alto y metodo para arreglar las lineas de señales para el mismo.

Info

Publication number
MX9502241A
MX9502241A MX9502241A MX9502241A MX9502241A MX 9502241 A MX9502241 A MX 9502241A MX 9502241 A MX9502241 A MX 9502241A MX 9502241 A MX9502241 A MX 9502241A MX 9502241 A MX9502241 A MX 9502241A
Authority
MX
Mexico
Prior art keywords
memory device
semiconductor memory
pair
signal lines
line
Prior art date
Application number
MX9502241A
Other languages
English (en)
Inventor
Dong-Il Seo
Se-Jin Jeong
Original Assignee
Samsung Electronics Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Samsung Electronics Co Ltd filed Critical Samsung Electronics Co Ltd
Publication of MX9502241A publication Critical patent/MX9502241A/es

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C5/00—Details of stores covered by group G11C11/00
    • G11C5/06—Arrangements for interconnecting storage elements electrically, e.g. by wiring
    • G11C5/063—Voltage and signal distribution in integrated semi-conductor memory access lines, e.g. word-line, bit-line, cross-over resistance, propagation delay
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1006—Data managing, e.g. manipulating data before writing or reading out, data bus switches or control circuits therefor
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/70—Masking faults in memories by using spares or by reconfiguring
    • G11C29/78—Masking faults in memories by using spares or by reconfiguring using programmable devices
    • G11C29/785—Masking faults in memories by using spares or by reconfiguring using programmable devices with redundancy programming schemes
    • G11C29/787—Masking faults in memories by using spares or by reconfiguring using programmable devices with redundancy programming schemes using a fuse hierarchy
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers

Landscapes

  • Dram (AREA)
  • Static Random-Access Memory (AREA)
  • Semiconductor Memories (AREA)

Abstract

Un dispositivo semiconductor de memoria incluye ordenaciones compuestas de una pluralidad de bloques de referencia que almacenan una pluralidad de celdas de memoria, una pluralidad de líneas de palabras que se extienden en la direccion de la longitud de un circuito integrado, una pluralidad de líneas de bitios que se extienden en una direccion vertical de la longitud de un circuito integrado, cada par de líneas de bitios está compuesto de una línea de bitios y una línea de bitios complementaria, una pluralidad de líneas de entrada/salida de datos arreglada en la porcion superior de las ordenaciones o arreglos, y que se extienden en la direccion vertical, cada par de líneas de entrada/salida de datos está compuesto de una línea de entrada/salida de datos y una línea de entrada/salida de datos complementaria, y se conectan una por una a cada par de líneas de bitios, y una pluralidad de líneas de seleccion de columnas arregladas en la direccion vertical, y adyacentes a la línea de entrada/salida de datos y a la línea de entrada/salida de datos complementaria, para controlar la conexion de cada par de líneas de bitios a las líneas de entrada/salida de datos.
MX9502241A 1994-05-20 1995-05-17 Dispositivo semiconductor de memoria para obtener un ancho de banda grande o alto y metodo para arreglar las lineas de señales para el mismo. MX9502241A (es)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR19940011050 1994-05-20

Publications (1)

Publication Number Publication Date
MX9502241A true MX9502241A (es) 1997-02-28

Family

ID=19383493

Family Applications (1)

Application Number Title Priority Date Filing Date
MX9502241A MX9502241A (es) 1994-05-20 1995-05-17 Dispositivo semiconductor de memoria para obtener un ancho de banda grande o alto y metodo para arreglar las lineas de señales para el mismo.

Country Status (9)

Country Link
US (3) US5537346A (es)
EP (1) EP0683493B1 (es)
JP (1) JP2786609B2 (es)
KR (1) KR0181202B1 (es)
CN (1) CN1099117C (es)
DE (1) DE69515927T2 (es)
MX (1) MX9502241A (es)
RU (1) RU2170955C2 (es)
TW (1) TW270983B (es)

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IT1266450B1 (it) * 1993-12-07 1996-12-30 Texas Instruments Italia Spa Mini-memoria cache per memorie di campo.
JP3579205B2 (ja) 1996-08-06 2004-10-20 株式会社ルネサステクノロジ 半導体記憶装置、半導体装置、データ処理装置及びコンピュータシステム
JP3466034B2 (ja) * 1996-12-27 2003-11-10 富士通株式会社 半導体記憶装置
JPH10302471A (ja) * 1997-02-28 1998-11-13 Mitsubishi Electric Corp 半導体記憶装置
US6044481A (en) * 1997-05-09 2000-03-28 Artisan Components, Inc. Programmable universal test interface for testing memories with different test methodologies
US6072730A (en) * 1997-10-25 2000-06-06 Artisan Components, Inc. Low power differential signal transition techniques for use in memory devices
US6154386A (en) * 1998-06-16 2000-11-28 G-Link Technology Memory device having a wide data path
US6072737A (en) 1998-08-06 2000-06-06 Micron Technology, Inc. Method and apparatus for testing embedded DRAM
US6034900A (en) * 1998-09-02 2000-03-07 Micron Technology, Inc. Memory device having a relatively wide data bus
US6448631B2 (en) 1998-09-23 2002-09-10 Artisan Components, Inc. Cell architecture with local interconnect and method for making same
US6367059B1 (en) 1999-03-23 2002-04-02 Artisan Components, Inc. Carry chain standard cell with charge sharing reduction architecture
US6339541B1 (en) * 2000-06-16 2002-01-15 United Memories, Inc. Architecture for high speed memory circuit having a relatively large number of internal data lines
DE10110624B4 (de) * 2001-03-06 2010-04-08 Qimonda Ag Integrierter Speicher mit mehreren Speicherbereichen
US6664634B2 (en) * 2001-03-15 2003-12-16 Micron Technology, Inc. Metal wiring pattern for memory devices
KR100516735B1 (ko) * 2001-12-08 2005-09-22 주식회사 하이닉스반도체 메모리 셀 어레이 내부 배선을 이용한 로오 엑세스 정보전달 장치
US7218564B2 (en) * 2004-07-16 2007-05-15 Promos Technologies Inc. Dual equalization devices for long data line pairs
US8259509B2 (en) * 2008-08-18 2012-09-04 Elpida Memory, Inc. Semiconductor memory device and method with auxiliary I/O line assist circuit and functionality
KR20100112490A (ko) * 2009-04-09 2010-10-19 삼성전자주식회사 데이터 라인 레이아웃
RU2453935C1 (ru) * 2010-10-26 2012-06-20 Валов Сергей Геннадьевич Способ снижения энергопотребления в n-мерной контекстно-адресуемой памяти
JP5684161B2 (ja) * 2012-01-26 2015-03-11 株式会社東芝 半導体装置

Family Cites Families (14)

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Publication number Priority date Publication date Assignee Title
JPH01246091A (ja) * 1988-03-29 1989-10-02 Amada Co Ltd スイング式機械のアーム長初期設定方法
JPH01278065A (ja) * 1988-04-28 1989-11-08 Hitachi Ltd 半導体記憶装置
JPH0772991B2 (ja) * 1988-12-06 1995-08-02 三菱電機株式会社 半導体記憶装置
EP0454998B1 (en) * 1990-03-28 1995-11-08 Nec Corporation Semiconductor memory device
JPH0696582A (ja) * 1990-09-17 1994-04-08 Texas Instr Inc <Ti> メモリアレイアーキテクチャ
JPH0562461A (ja) * 1991-04-09 1993-03-12 Mitsubishi Electric Corp 半導体記憶装置
US5652723A (en) * 1991-04-18 1997-07-29 Mitsubishi Denki Kabushiki Kaisha Semiconductor memory device
KR940003410B1 (ko) * 1991-08-01 1994-04-21 삼성전자 주식회사 망사 구조의 전원선을 가지는 반도체 메모리 장치
EP0544247A3 (en) * 1991-11-27 1993-10-20 Texas Instruments Inc Memory architecture
JP2775552B2 (ja) * 1991-12-26 1998-07-16 三菱電機株式会社 半導体記憶装置
JP2938706B2 (ja) * 1992-04-27 1999-08-25 三菱電機株式会社 同期型半導体記憶装置
US5325336A (en) * 1992-09-10 1994-06-28 Mitsubishi Denki Kabushiki Kaisha Semiconductor memory device having power line arranged in a meshed shape
US5457648A (en) * 1992-10-08 1995-10-10 Intel Corporation Random access memory with digital signals running over the small signal region of the array
EP0593152B1 (en) * 1992-10-14 2000-12-27 Sun Microsystems, Inc. Random access memory design

Also Published As

Publication number Publication date
DE69515927T2 (de) 2000-11-16
EP0683493B1 (en) 2000-03-29
US5783480A (en) 1998-07-21
EP0683493A3 (es) 1995-12-27
DE69515927D1 (de) 2000-05-04
RU95107895A (ru) 1997-02-10
CN1149187A (zh) 1997-05-07
EP0683493A2 (en) 1995-11-22
JP2786609B2 (ja) 1998-08-13
JPH07320480A (ja) 1995-12-08
KR950034254A (ko) 1995-12-26
CN1099117C (zh) 2003-01-15
TW270983B (es) 1996-02-21
US5537346A (en) 1996-07-16
KR0181202B1 (ko) 1999-04-15
RU2170955C2 (ru) 2001-07-20
US5621679A (en) 1997-04-15

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