MX2010004187A - Esquema de linea de bit de precarga a nivel de suelo para operacion de lectura en memoria de acceo aleatorio magnetoresistiva de torsion por transferencia de rotacion. - Google Patents

Esquema de linea de bit de precarga a nivel de suelo para operacion de lectura en memoria de acceo aleatorio magnetoresistiva de torsion por transferencia de rotacion.

Info

Publication number
MX2010004187A
MX2010004187A MX2010004187A MX2010004187A MX2010004187A MX 2010004187 A MX2010004187 A MX 2010004187A MX 2010004187 A MX2010004187 A MX 2010004187A MX 2010004187 A MX2010004187 A MX 2010004187A MX 2010004187 A MX2010004187 A MX 2010004187A
Authority
MX
Mexico
Prior art keywords
random access
access memory
read operation
transfer torque
spin transfer
Prior art date
Application number
MX2010004187A
Other languages
English (en)
Inventor
Sei Seung Yoon
Seung H Kang
Original Assignee
Qualcomm Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Qualcomm Inc filed Critical Qualcomm Inc
Publication of MX2010004187A publication Critical patent/MX2010004187A/es

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/02—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements
    • G11C11/16—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements using elements in which the storage effect is based on magnetic spin effect
    • G11C11/165—Auxiliary circuits
    • G11C11/1673—Reading or sensing circuits or methods
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/02—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements
    • G11C11/16—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements using elements in which the storage effect is based on magnetic spin effect
    • G11C11/165—Auxiliary circuits
    • G11C11/1693—Timing circuits or methods
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/02—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements
    • G11C11/14—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements using thin-film elements
    • G11C11/15—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements using thin-film elements using multiple magnetic layers
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/02—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements
    • G11C11/16—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements using elements in which the storage effect is based on magnetic spin effect
    • G11C11/165—Auxiliary circuits
    • G11C11/1653—Address circuits or decoders
    • G11C11/1657—Word-line or row circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/02—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements
    • G11C11/16—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements using elements in which the storage effect is based on magnetic spin effect
    • G11C11/165—Auxiliary circuits
    • G11C11/1697—Power supply circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C5/00—Details of stores covered by group G11C11/00
    • G11C5/06—Arrangements for interconnecting storage elements electrically, e.g. by wiring
    • G11C5/063—Voltage and signal distribution in integrated semi-conductor memory access lines, e.g. word-line, bit-line, cross-over resistance, propagation delay

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Mram Or Spin Memory Techniques (AREA)
  • Hall/Mr Elements (AREA)

Abstract

Se describen sistemas, circuitos y métodos para operaciones de lectura en Memoria de Acceso Aleatorio Magnetoresistiva de Torsión por Transferencia de Rotación (STT-MRAM); se proporciona una pluralidad de células de bits, cada una acoplada a una de una pluralidad de líneas de bits, líneas de palabras y líneas fuente; una pluralidad de transistores de precarga correspondiente a una de la pluralidad de líneas de bits está configurada para descargar las líneas de bits al suelo antes de una operación de lectura.
MX2010004187A 2007-10-17 2008-10-17 Esquema de linea de bit de precarga a nivel de suelo para operacion de lectura en memoria de acceo aleatorio magnetoresistiva de torsion por transferencia de rotacion. MX2010004187A (es)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US11/873,684 US20090103354A1 (en) 2007-10-17 2007-10-17 Ground Level Precharge Bit Line Scheme for Read Operation in Spin Transfer Torque Magnetoresistive Random Access Memory
PCT/US2008/080300 WO2009052371A2 (en) 2007-10-17 2008-10-17 Ground level precharge bit line scheme for read operation in spin transfer torque magnetoresistive random access memory

Publications (1)

Publication Number Publication Date
MX2010004187A true MX2010004187A (es) 2010-05-14

Family

ID=40506505

Family Applications (1)

Application Number Title Priority Date Filing Date
MX2010004187A MX2010004187A (es) 2007-10-17 2008-10-17 Esquema de linea de bit de precarga a nivel de suelo para operacion de lectura en memoria de acceo aleatorio magnetoresistiva de torsion por transferencia de rotacion.

Country Status (8)

Country Link
US (1) US20090103354A1 (es)
EP (1) EP2206121A2 (es)
JP (1) JP2011501342A (es)
KR (1) KR20100080935A (es)
CN (1) CN101878506A (es)
CA (1) CA2702487A1 (es)
MX (1) MX2010004187A (es)
WO (1) WO2009052371A2 (es)

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US7957183B2 (en) * 2009-05-04 2011-06-07 Magic Technologies, Inc. Single bit line SMT MRAM array architecture and the programming method
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US8207757B1 (en) * 2011-02-07 2012-06-26 GlobalFoundries, Inc. Nonvolatile CMOS-compatible logic circuits and related operating methods
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US9224453B2 (en) * 2013-03-13 2015-12-29 Qualcomm Incorporated Write-assisted memory with enhanced speed
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KR102154026B1 (ko) 2013-08-29 2020-09-09 삼성전자주식회사 자기 메모리 장치의 동작 방법
KR102116792B1 (ko) 2013-12-04 2020-05-29 삼성전자 주식회사 자기 메모리 장치, 이의 동작 방법 및 이를 포함하는 반도체 시스템
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US9343131B1 (en) * 2015-02-24 2016-05-17 International Business Machines Corporation Mismatch and noise insensitive sense amplifier circuit for STT MRAM
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Also Published As

Publication number Publication date
KR20100080935A (ko) 2010-07-13
US20090103354A1 (en) 2009-04-23
CN101878506A (zh) 2010-11-03
WO2009052371A2 (en) 2009-04-23
CA2702487A1 (en) 2009-04-23
JP2011501342A (ja) 2011-01-06
WO2009052371A3 (en) 2009-06-11
EP2206121A2 (en) 2010-07-14

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