KR950026032A - 다결정실리콘 박막트랜지스터의 제조방법 - Google Patents
다결정실리콘 박막트랜지스터의 제조방법 Download PDFInfo
- Publication number
- KR950026032A KR950026032A KR1019940003531A KR19940003531A KR950026032A KR 950026032 A KR950026032 A KR 950026032A KR 1019940003531 A KR1019940003531 A KR 1019940003531A KR 19940003531 A KR19940003531 A KR 19940003531A KR 950026032 A KR950026032 A KR 950026032A
- Authority
- KR
- South Korea
- Prior art keywords
- thin film
- film transistor
- layer
- manufacturing
- gate pattern
- Prior art date
Links
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 12
- 239000010409 thin film Substances 0.000 title claims abstract description 10
- 229910021420 polycrystalline silicon Inorganic materials 0.000 title claims abstract 5
- 238000000034 method Methods 0.000 claims abstract description 9
- 229920002120 photoresistant polymer Polymers 0.000 claims abstract description 3
- 229920005591 polysilicon Polymers 0.000 claims abstract 4
- 239000000758 substrate Substances 0.000 claims abstract 2
- 239000010408 film Substances 0.000 claims description 2
- 238000002844 melting Methods 0.000 claims 1
- 230000008018 melting Effects 0.000 claims 1
- 239000002184 metal Substances 0.000 claims 1
- 229910052751 metal Inorganic materials 0.000 claims 1
- 238000010586 diagram Methods 0.000 description 3
- 150000004767 nitrides Chemical class 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66742—Thin film unipolar transistors
- H01L29/6675—Amorphous silicon or polysilicon transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/78606—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device
- H01L29/78618—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device characterised by the drain or the source properties, e.g. the doping structure, the composition, the sectional shape or the contact structure
- H01L29/78621—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device characterised by the drain or the source properties, e.g. the doping structure, the composition, the sectional shape or the contact structure with LDD structure or an extension or an offset region or characterised by the doping profile
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/78645—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with multiple gate
- H01L29/78648—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with multiple gate arranged on opposing sides of the channel
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Thin Film Transistor (AREA)
Abstract
본 발명은 다결정실리콘 박막트랜지스터의 제조방법에 관한 것으로, 좀 더 상세하게는 투명기판(11)에 하부 게이트 패턴(12)을 형성시킨후, 완충 절연층(13), p-Si층(14), 게이트 절연막(15), 상부 게이트층(18) 및 포토레지스트층(17)을 순차적으로 적층시킨 다음, 배면노광법을 이용하여 상기 상부 게이트층(18)을 드라이 에칭시켜 상부 게이트 패턴(16)을 형성시키는 다결정실리콘 박막트랜지스터의 제조방법에 관한 것이다.
Description
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제2도는 본 발명에 따른 박막 트랜지스터의 단면도이며, 제3도는 포토레지스트를 이용하여 제조되는 종래의 박막 트랜지스터를 제조하는 공정을 개략적으로 도시한 제조공정도이고, 제4도는 질화막을 이용하여 제조되는 종래의 박막 트랜지스터를 제조하는 공정을 개략적으로 도시한 제조공정도이며, 제5도는 본 발명에 따라 박막 트랜지스터를 제조하는 공정을 개략적으로 도시한 제조공정도이다.
Claims (4)
- 다결정실리콘 박막트랜지스터의 제조방법에 있어서, 투명기판(11)에 하부 게이트 패턴(12)을 형성시킨후, 완충 절연층(13), p-Si층(14), 게이트 절연막(15), 상부 게이트층(18) 및 포토레지스트층(17)을 순차적으로 적층시킨 다음, 배면노광법을 이용하여 상기 상부 게이트층(18)을 드라이 에칭시켜 상부 게이트 패턴(16)을 형성시키는 것을 특징으로 하는 다결정실리콘 박막트랜지스터의 제조방법.
- 제1항에 있어서, 상기 하부 게이트 패턴(12)이 고온에 내성을 갖는 고융점 금속인 Cr, Mo 또는 W로 이루어짐을 특징으로 하는 다결정실리콘 박막트랜지스터의 제조방법.
- 제1항에 있어서, 상기 상부 게이트 패턴(16)이 하부 게이트 패턴(12)보다 작은 크기로 형성됨을 특징으로 하는 다결정실리콘 박막 트랜지스터의 제조방법.
- 제1항에 있어서, 상기 다결정실리콘 박막트랜지스터가 오프-셋 또는 LDD 구조임을 특징으로 하는 다결정 실리콘 박막트랜지스터의 제조방법.※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.
Priority Applications (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR1019940003531A KR950026032A (ko) | 1994-02-25 | 1994-02-25 | 다결정실리콘 박막트랜지스터의 제조방법 |
US08/396,162 US5702960A (en) | 1994-02-25 | 1995-02-27 | Method for manufacturing polysilicon thin film transistor |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR1019940003531A KR950026032A (ko) | 1994-02-25 | 1994-02-25 | 다결정실리콘 박막트랜지스터의 제조방법 |
Publications (1)
Publication Number | Publication Date |
---|---|
KR950026032A true KR950026032A (ko) | 1995-09-18 |
Family
ID=19377844
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
KR1019940003531A KR950026032A (ko) | 1994-02-25 | 1994-02-25 | 다결정실리콘 박막트랜지스터의 제조방법 |
Country Status (2)
Country | Link |
---|---|
US (1) | US5702960A (ko) |
KR (1) | KR950026032A (ko) |
Families Citing this family (10)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP3176527B2 (ja) * | 1995-03-30 | 2001-06-18 | シャープ株式会社 | 半導体装置の製造方法 |
US6277679B1 (en) | 1998-11-25 | 2001-08-21 | Semiconductor Energy Laboratory Co., Ltd. | Method of manufacturing thin film transistor |
US6674136B1 (en) * | 1999-03-04 | 2004-01-06 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device having driver circuit and pixel section provided over same substrate |
CN1375113A (zh) * | 1999-09-16 | 2002-10-16 | 松下电器产业株式会社 | 薄膜晶体管及其制造方法 |
KR20030056827A (ko) * | 2001-12-28 | 2003-07-04 | 엘지.필립스 엘시디 주식회사 | 폴리실리콘 박막트랜지스터의 형성방법 |
JP2004343018A (ja) * | 2003-03-20 | 2004-12-02 | Fujitsu Ltd | 半導体装置及びその製造方法 |
KR100703467B1 (ko) * | 2005-01-07 | 2007-04-03 | 삼성에스디아이 주식회사 | 박막트랜지스터 |
CN104538458A (zh) * | 2014-12-22 | 2015-04-22 | 京东方科技集团股份有限公司 | 一种显示装置、阵列基板、薄膜晶体管及其制作方法 |
CN105575776B (zh) | 2016-01-04 | 2019-03-15 | 京东方科技集团股份有限公司 | 掩膜图案的形成方法、薄膜晶体管及形成方法、显示装置 |
CN105742240B (zh) * | 2016-04-05 | 2019-09-13 | 武汉华星光电技术有限公司 | 一种ltps阵列基板的制造方法 |
Family Cites Families (10)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS61105870A (ja) * | 1984-10-30 | 1986-05-23 | Seiko Epson Corp | 薄膜トランジスタの製造方法 |
US5198377A (en) * | 1987-07-31 | 1993-03-30 | Kinya Kato | Method of manufacturing an active matrix cell |
US5130263A (en) * | 1990-04-17 | 1992-07-14 | General Electric Company | Method for photolithographically forming a selfaligned mask using back-side exposure and a non-specular reflecting layer |
US5198379A (en) * | 1990-04-27 | 1993-03-30 | Sharp Kabushiki Kaisha | Method of making a MOS thin film transistor with self-aligned asymmetrical structure |
DE69109547T2 (de) * | 1990-07-06 | 1996-01-18 | Seiko Epson Corp | Verfahren zur Herstellung eines Substrates für eine Flüssigkristall-Anzeigevorrichtung. |
US5420048A (en) * | 1991-01-09 | 1995-05-30 | Canon Kabushiki Kaisha | Manufacturing method for SOI-type thin film transistor |
KR940007451B1 (ko) * | 1991-09-06 | 1994-08-18 | 주식회사 금성사 | 박막트랜지스터 제조방법 |
JP3019526B2 (ja) * | 1991-09-19 | 2000-03-13 | 日本電気株式会社 | 薄膜トランジスタの製造方法 |
US5348897A (en) * | 1992-12-01 | 1994-09-20 | Paradigm Technology, Inc. | Transistor fabrication methods using overlapping masks |
US5385854A (en) * | 1993-07-15 | 1995-01-31 | Micron Semiconductor, Inc. | Method of forming a self-aligned low density drain inverted thin film transistor |
-
1994
- 1994-02-25 KR KR1019940003531A patent/KR950026032A/ko not_active Application Discontinuation
-
1995
- 1995-02-27 US US08/396,162 patent/US5702960A/en not_active Expired - Lifetime
Also Published As
Publication number | Publication date |
---|---|
US5702960A (en) | 1997-12-30 |
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