KR950024587A - Address generator for motion compensation - Google Patents

Address generator for motion compensation Download PDF

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Publication number
KR950024587A
KR950024587A KR1019940000771A KR19940000771A KR950024587A KR 950024587 A KR950024587 A KR 950024587A KR 1019940000771 A KR1019940000771 A KR 1019940000771A KR 19940000771 A KR19940000771 A KR 19940000771A KR 950024587 A KR950024587 A KR 950024587A
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KR
South Korea
Prior art keywords
address
motion vector
generating
address generator
read
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Application number
KR1019940000771A
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Korean (ko)
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KR0123090B1 (en
Inventor
김영준
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배순훈
대우전자 주식회사
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Priority to KR1019940000771A priority Critical patent/KR0123090B1/en
Publication of KR950024587A publication Critical patent/KR950024587A/en
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Publication of KR0123090B1 publication Critical patent/KR0123090B1/en

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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N19/00—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals
    • H04N19/42—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals characterised by implementation details or hardware specially adapted for video compression or decompression, e.g. dedicated software implementation
    • H04N19/43—Hardware specially adapted for motion estimation or compensation
    • H04N19/433—Hardware specially adapted for motion estimation or compensation characterised by techniques for memory access
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N19/00—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals
    • H04N19/10—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using adaptive coding
    • H04N19/134—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using adaptive coding characterised by the element, parameter or criterion affecting or controlling the adaptive coding
    • H04N19/136—Incoming video signal characteristics or properties
    • H04N19/137—Motion inside a coding unit, e.g. average field, frame or block difference
    • H04N19/139—Analysis of motion vectors, e.g. their magnitude, direction, variance or reliability
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N19/00—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals
    • H04N19/10—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using adaptive coding
    • H04N19/169—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using adaptive coding characterised by the coding unit, i.e. the structural portion or semantic portion of the video signal being the object or the subject of the adaptive coding
    • H04N19/182—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using adaptive coding characterised by the coding unit, i.e. the structural portion or semantic portion of the video signal being the object or the subject of the adaptive coding the unit being a pixel
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N19/00—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals
    • H04N19/10—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using adaptive coding
    • H04N19/169—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using adaptive coding characterised by the coding unit, i.e. the structural portion or semantic portion of the video signal being the object or the subject of the adaptive coding
    • H04N19/186—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using adaptive coding characterised by the coding unit, i.e. the structural portion or semantic portion of the video signal being the object or the subject of the adaptive coding the unit being a colour or a chrominance component

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  • Engineering & Computer Science (AREA)
  • Multimedia (AREA)
  • Signal Processing (AREA)
  • Compression Or Coding Systems Of Tv Signals (AREA)
  • Color Television Systems (AREA)
  • Television Signal Processing For Recording (AREA)
  • Image Input (AREA)

Abstract

본 발명에 따른 프레임 메모리내의 픽셀 데이타 위치를 지정하기 위한 어드레스 생성기에 있어서, 픽셀 데이타를 쓰기 또는 읽기 위한 어드레스를 생성하는 쓰기/읽기 어드레스 생성부(31)와, 픽셀 데이타 읽기시 움직임 벡터가 수평축에 대해서 발생했을 때 이에 대한 어드레스를 생성하는 수평 읽기 어드레스 생성부(32)와, 픽셀 데이타 읽기시 움직임 벡터가 수직축에 대해서 발생했을 때 이에 대한 어드래스를 생성하는 수직 읽기 어드레스 생성부(33)와, 픽셀 데이타 읽기시 움직임 벡터가 수평 및 수직축에 대해서 발생했을 때 이에 대한 어드레스를 생성하는 수평 및 수직 읽기 어드레스 생성부(34)와, 상기 어드레스 생성부(32),(33) 및 (34)로 부터의 어드레스와 움직임 벡터를 가산하는 다수개의 가산부(35),(36),(37)와, 선택신호(SO)에 응답하여, 상기 쓰기/읽기 어드레스 생성부(31) 또는 상기 가산부(35),(36),(3 7)로 부터의 어드레스를 선택적으로 출력하는 멀티플렉서(38)를 포함한다. 따라서, 본 어드레스 생성기는 움직임 보상에서 움직임 벡터를 픽셀단위 뿐만 아니라 반 픽셀(half pjxel) 단위로 처리할 수 있다.In the address generator for designating a pixel data position in a frame memory according to the present invention, a write / read address generator 31 for generating an address for writing or reading pixel data, and a motion vector at the time of reading the pixel data are located on the horizontal axis. A horizontal read address generator 32 for generating an address thereof when it occurs, a vertical read address generator 33 for generating an address when a motion vector is generated with respect to the vertical axis when reading pixel data, From the horizontal and vertical read address generator 34 and the address generators 32, 33 and 34, which generate an address for the motion vector when the pixel vector is read on the horizontal and vertical axes. The write / responders 35, 36, and 37 for adding the address and the motion vector of < RTI ID = 0.0 > and < / RTI > It includes a group address generating section 31 or the addition unit 35, 36, a multiplexer 38 for selectively outputting the address of the from (37). Therefore, the present address generator may process the motion vector not only in pixel but also in half pixel (half pjxel) in motion compensation.

Description

움직임 보상을 위한 어드레스 생성기Address generator for motion compensation

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제2도는 본 발명에 따른 어드레스 생성부의 구조를 도시한 블럭도,2 is a block diagram showing the structure of an address generator according to the present invention;

제3도는 본 발명에 따른 어드레스 발생장치를 도시한 블럭도,3 is a block diagram showing an address generator according to the present invention;

제4도는 본 발명에 따른 어드레스 발생장치의 쓰기/읽기 어드레스 생성부의 작동을 도시한 타이밍도,4 is a timing diagram showing an operation of a write / read address generator of the address generator according to the present invention;

제7도는 본 발명에 따른 어드레스 발생장치의 수평 및 수직읽기 어드레스 생성부의 작동을 도시한 타이민도.7 is a diagram showing the operation of the horizontal and vertical read address generator of the address generator according to the present invention.

Claims (2)

프레임 메모리내의 픽셀 데이타 위치를 지정하기 위한 어드레스 생성기에 있어서, 픽셀 데이타를 쓰기 또는 읽기 위한 어드레스를 생성하는 쓰기/읽기 어드레스 생성부(31)와, 픽셀 데이타 읽기시 움직임 벡터가 수평축에 대해서 발생했을 때 이에 대한 어드레스를 생성하는 수평 읽기 어드레스 생성부(32)와; 픽셀 데이타 읽기시 움직임 벡터가 수직축에 대해서 발생했을 때 이에 대한 어드레스를 생성하는 수직 읽기 어드레스 생성부(33)와; 픽셀 데이타 읽기시 움직임 벡터가 수평 및 수직축에 대해서발생했을 때 이에 대한 어드레스를 생성하는 수평 및 수직 읽기 어드레스 생성부(34)와; 상기 어드레스 생성부(32),(33) 및 (34)로 부터의 어드레스와 움직임 벡터를 가산하는 다수개의 가산부(35),(36),(37)와; 선택신호(SO)에 응답하여, 상기 쓰기/읽기 어드레스 생성부(31) 또는 상기 가산부(35),(36),(37)로 부터의 어드레스를 선택적으로 출력하는 멀티플렉서(38)를 포함하는 것을 특징으로 하는 어드레스 생성기.In the address generator for specifying the position of pixel data in the frame memory, a write / read address generator 31 for generating an address for writing or reading pixel data, and when a motion vector occurs on the horizontal axis when pixel data is read. A horizontal read address generator 32 generating an address thereof; A vertical read address generator 33 for generating an address for the motion vector when the motion vector is generated on the vertical axis when reading the pixel data; Horizontal and vertical read address generators 34 for generating an address for the motion vector when the pixel vector is read on the horizontal and vertical axes; A plurality of adders (35), (36), (37) for adding an address and a motion vector from the address generators (32), (33), and (34); A multiplexer 38 for selectively outputting an address from the write / read address generator 31 or the adders 35, 36, 37 in response to the selection signal SO; An address generator, characterized in that. 제1항에 있어서, 상기 어드레스 생성부(31),(32),(33) 및 (34)가 영상신호중 휘도신호중 어드레스를 생성하기 위한 Y카운터(21)와; 영상신호중 색도신호의 어드레스를 생성하기 의한 U카운터(22) 및 V 카운터(23)을 포함하는 것을 특징으로 하는 어드레스 생성기.2. The apparatus of claim 1, wherein the address generators (31), (32), (33), and (34) comprise: a Y counter (21) for generating an address among luminance signals among video signals; And an U counter (22) and a V counter (23) for generating an address of the chroma signal in the video signal. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019940000771A 1994-01-18 1994-01-18 Address generator for compensating the motion KR0123090B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019940000771A KR0123090B1 (en) 1994-01-18 1994-01-18 Address generator for compensating the motion

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019940000771A KR0123090B1 (en) 1994-01-18 1994-01-18 Address generator for compensating the motion

Publications (2)

Publication Number Publication Date
KR950024587A true KR950024587A (en) 1995-08-21
KR0123090B1 KR0123090B1 (en) 1997-11-17

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