KR970009398A - Parallel processing method of video signal and its device - Google Patents

Parallel processing method of video signal and its device Download PDF

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Publication number
KR970009398A
KR970009398A KR1019950020203A KR19950020203A KR970009398A KR 970009398 A KR970009398 A KR 970009398A KR 1019950020203 A KR1019950020203 A KR 1019950020203A KR 19950020203 A KR19950020203 A KR 19950020203A KR 970009398 A KR970009398 A KR 970009398A
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South Korea
Prior art keywords
signal
divided
signals
video
parallel
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KR1019950020203A
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Korean (ko)
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KR0172491B1 (en
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반영균
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김광호
삼성전자 주식회사
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Priority to KR1019950020203A priority Critical patent/KR0172491B1/en
Publication of KR970009398A publication Critical patent/KR970009398A/en
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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N7/00—Television systems
    • H04N7/015—High-definition television systems
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N5/00—Details of television systems
    • H04N5/04—Synchronising
    • H04N5/08—Separation of synchronising signals from picture signals
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N5/00—Details of television systems
    • H04N5/222—Studio circuitry; Studio devices; Studio equipment
    • H04N5/262—Studio circuits, e.g. for mixing, switching-over, change of character of image, other special effects ; Cameras specially adapted for the electronic generation of special effects
    • H04N5/265—Mixing
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M1/00—Analogue/digital conversion; Digital/analogue conversion
    • H03M1/12—Analogue/digital converters
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M1/00—Analogue/digital conversion; Digital/analogue conversion
    • H03M1/66—Digital/analogue converters

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  • Engineering & Computer Science (AREA)
  • Multimedia (AREA)
  • Signal Processing (AREA)
  • Studio Circuits (AREA)
  • Television Signal Processing For Recording (AREA)

Abstract

본 발명은 화면을 분할하여 분할된 화면의 영상신호를 병렬로 처리하는 방법 및 그 장치에 관한 것이다. 본 발명은 영상신호에서 수평동기신호를 제외한 신호구간을 소정의 갯수로 분할한다. 이때, 분할영역의 경계선부분에는 분할경계선을 공유하는 인접영역의 경계선부분과 중첩되는 더미데이타를 포함한다. 분할된 영상신호들을 처리한 후 다시 합성할 때는 이더미데이타를 버리고 합성한 후 최종단계에서 동기신호를 삽입한다. 따라서, 본 발명은 경계부분의 신호가 왜곡되지 않아 깨끗한 화면을 제공하는 효과를 가져온다.The present invention relates to a method and an apparatus for processing a video signal of a divided screen in parallel by dividing the screen. The present invention divides a signal section excluding a horizontal synchronous signal from a video signal into a predetermined number. In this case, the boundary line portion of the divided region includes dummy data overlapping with the boundary line portion of the adjacent region sharing the divided boundary line. When the video signals are processed and then synthesized again, the Etheremidata is discarded and synthesized, and a synchronization signal is inserted in the final step. Therefore, the present invention brings the effect of providing a clear screen because the signal of the boundary portion is not distorted.

Description

영상신호의 병렬처리방법 및 그 장치Parallel processing method of video signal and its device

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제6도는 본 발명에 의한 화면분할방법을 나타내는 도면, 제7도는 제6도에 의해 분할된 각 영역의 영상신호.FIG. 6 is a diagram showing a screen division method according to the present invention, and FIG. 7 is a video signal of each region divided by FIG.

Claims (12)

화면을 다수개의 영역으로 분할하여 각 영역의 영상신호를 병렬로 처리하는 방법에 있어서, 상기 분할영역의 분할경계선부분에 더미데이타(Dummy Data)를 포함하도록 1수평주기의 영상신호를 분할하는 단계; 상기 분할된 영상신호들을 병렬로 신호처리하는 단계; 및 상기 신호처리된 영상신호들에서 더미데이타를 제외한 신호구간만을 합성하는 단계를 포함하는 영상신호의 병렬처리방법.A method of processing a video signal of each area in parallel by dividing a screen into a plurality of areas, the method comprising: dividing a video signal of one horizontal period so that dummy data is included in a division boundary line of the divided area; Signal processing the divided image signals in parallel; And synthesizing only a signal section excluding dummy data from the signal processed image signals. 제1항에 있어서, 상기 더미데이타는 상기 분할경계선을 공유하는 인접영역끼리 동일한 것을 특징으로 하는 영상신호의 병렬처리방법.The method of claim 1, wherein the dummy data is identical to adjacent areas sharing the divided boundary lines. 제1항에 있어서, 상기 1수평동기신호의 영상신호를 분할할 때 수평동기신호를 제외한 신호구간만이 분할되는 것을 특징으로 하는 영상신호의 병렬처리방법.The parallel processing method of claim 1, wherein when dividing the video signal of the one horizontal synchronization signal, only a signal section excluding the horizontal synchronization signal is divided. 제3항에 있어서, 상기 신호합성 후에 수평동기신호를 삽입하는 단계를 더 포함하는 영상신호의 병렬처리방법.4. The parallel processing method of claim 3, further comprising inserting a horizontal synchronization signal after the signal synthesis. 제4항에 있어서, 상기 수평동기신호는 상기 합성한 영상신호들을 아날로그형태로 변환한 후에 삽압하는 것을 목적으로 하는 영상신호의 병렬처리방법.5. The parallel processing method of claim 4, wherein the horizontal synchronous signal is inserted into the analog image signal after converting the synthesized image signal into an analog form. 화면을 다수개의 영역으로 분할하여 각 영역의 영상신호를 병렬로 처리하는 장치에 있어서, 상기 분할영역의 분할경계선부분에 더미데이타(Dummy Data)를 포함하도록 1수평주기의 영상신호를 분할하여 분할한 영상신호들을 각각저장하는 메모리들; 상기 메모리들로부터 신호를 독출하여 신호처리하는 영상신호처리부; 상기 신호처리된 영상신호들에서 더미데이타를 제외한 신호구간만을 합성하는 신호합성부; 및 상기 각부의 동작을 제어하기 위한 제어신호를 발생하는제어부를 포함하는 영상신호의 병렬처리장치.A device for dividing a screen into a plurality of areas and processing video signals of each area in parallel, wherein the video signal of one horizontal period is divided and divided so as to include dummy data in the division boundary line of the divided area. Memories respectively storing image signals; An image signal processor configured to read and signal signals from the memories; A signal synthesizer for synthesizing only a signal section excluding dummy data from the signal processed image signals; And a control unit generating a control signal for controlling the operation of each unit. 제6항에 있어서, 상기 더미데이타는 상기 분할경계선을 공유하는 인접영역끼리 동일한 것을 특징으로 하는 영상신호의 병렬처리장치.7. The apparatus of claim 6, wherein the dummy data is the same between adjacent regions sharing the division boundary line. 제6항에 있어서, 상기 1수평주기의 영상신호에서 수평동기신호를 제외한 신호구간만이 분할되는 것을 특징으로 하는 영상신호의 병렬처리장치.7. The apparatus of claim 6, wherein only a signal section excluding the horizontal synchronization signal is divided from the video signal of one horizontal period. 제6항에 있어서, 상기 메모리들은 1수평주기의 영상신호를 저장할 수 있는 용량을 상기 분할영역의 갯수만큼 분할한 형태인 것을 특징으로 하는 영상신호의 병렬처리장치.The parallel processing apparatus of claim 6, wherein the memories are divided by the number of division areas by a capacity capable of storing a video signal of one horizontal period. 제9항에 있어서, 상기 제어부는 상기 메모리들에 인가할 기록인에이블신호들의 양끝이 소정부분 중첩되도록 발생하여 이 부분의 신호가 상기 분할경계선을 공유하는 두개 영역의 영상신호를 각각 저장하는 메모리에 모두 기록되는 것을 특징으로 하는 영상신호의 병렬처리장치.10. The memory of claim 9, wherein the control unit generates a plurality of overlapping ends of the write enable signals to be applied to the memories, and stores the video signals of two regions in which the signals of the portions share the divided boundary lines. Parallel processing apparatus for a video signal, characterized in that all are recorded. 제6항에 있어서, 상기 신호합성부는 상기 병렬로 신호처리된 신호들을 순차적으로 절환하여 출력하는 멀티플렉서로 구성되는 것을 특징으로 하는 영상신호의 병렬처리장치.7. The apparatus of claim 6, wherein the signal synthesizing unit comprises a multiplexer which sequentially switches and outputs the signals processed in parallel. 제8항에 있어서, 상기 합성된 신호에 동기신호를 삽입하는 동기신호합성부를 더 포함하는 영상신호의 병렬처리장치.The apparatus of claim 8, further comprising a synchronization signal synthesis unit configured to insert a synchronization signal into the synthesized signal. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019950020203A 1995-07-10 1995-07-10 Parallel management method and apparatus of image signal KR0172491B1 (en)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100417086B1 (en) * 1995-12-30 2004-06-23 고려화학 주식회사 Coating composition using resin cured by heat and ultraviolet simultaneously

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7525548B2 (en) * 2005-11-04 2009-04-28 Nvidia Corporation Video processing with multiple graphical processing units

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100417086B1 (en) * 1995-12-30 2004-06-23 고려화학 주식회사 Coating composition using resin cured by heat and ultraviolet simultaneously

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