KR950023001A - Digital element video signal converter using a combination of pixel and line address - Google Patents
Digital element video signal converter using a combination of pixel and line address Download PDFInfo
- Publication number
- KR950023001A KR950023001A KR1019930030025A KR930030025A KR950023001A KR 950023001 A KR950023001 A KR 950023001A KR 1019930030025 A KR1019930030025 A KR 1019930030025A KR 930030025 A KR930030025 A KR 930030025A KR 950023001 A KR950023001 A KR 950023001A
- Authority
- KR
- South Korea
- Prior art keywords
- pixel
- counter
- signal
- line
- decoder
- Prior art date
Links
Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N7/00—Television systems
- H04N7/015—High-definition television systems
Landscapes
- Engineering & Computer Science (AREA)
- Multimedia (AREA)
- Signal Processing (AREA)
- Processing Of Color Television Signals (AREA)
- Color Television Systems (AREA)
- Television Systems (AREA)
Abstract
본 발명은 CCIR(International Radio Consultative Committee) 권고안 601을 출력하는 디지탈 디코더로부터 입력된 신호를 CCIR 권고안 656을 참고하여 CCIR 656형식으로 출력 할 수 있도록 하드 웨어로 구현한 것이다.The present invention is implemented in hardware so that the signal input from the digital decoder that outputs the International Radio Consultative Committee (CCIR) Recommendation 601 can be output in CCIR 656 format with reference to CCIR Recommendation 656.
본 발명은 NTSC 디지탈 디코더로 부터 받은 601 신호를 656 형식으로 변환하여 656형식의 데이타와 통신이 가능한 디지탈 영상장비에 연결하여 사용할 수 있다.The present invention can be used by converting a 601 signal received from an NTSC digital decoder into a 656 format and connecting to a digital imaging apparatus capable of communicating with the 656 format data.
Description
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.
제1도는 본 발명의 주변장치와의 구성도,1 is a block diagram of the peripheral device of the present invention,
제2도는 라인 내에서 워드의 배열 구성도,2 is an arrangement diagram of words in a line;
제3도는 타이밍 기준 신호의 구성도,3 is a configuration diagram of a timing reference signal;
제4도는 프레임 내에서 영상 신호의 배열 구성도,4 is an arrangement diagram of an image signal in a frame;
제5도는 본 발명에 따른 구성도,5 is a block diagram according to the present invention,
Claims (1)
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR1019930030025A KR970003796B1 (en) | 1993-12-27 | 1993-12-27 | Digital source image-signal change device using the number of pixel and line |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR1019930030025A KR970003796B1 (en) | 1993-12-27 | 1993-12-27 | Digital source image-signal change device using the number of pixel and line |
Publications (2)
Publication Number | Publication Date |
---|---|
KR950023001A true KR950023001A (en) | 1995-07-28 |
KR970003796B1 KR970003796B1 (en) | 1997-03-21 |
Family
ID=19373036
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
KR1019930030025A KR970003796B1 (en) | 1993-12-27 | 1993-12-27 | Digital source image-signal change device using the number of pixel and line |
Country Status (1)
Country | Link |
---|---|
KR (1) | KR970003796B1 (en) |
-
1993
- 1993-12-27 KR KR1019930030025A patent/KR970003796B1/en not_active IP Right Cessation
Also Published As
Publication number | Publication date |
---|---|
KR970003796B1 (en) | 1997-03-21 |
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Payment date: 20030226 Year of fee payment: 7 |
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