KR970056957A - Image processing equipment - Google Patents

Image processing equipment Download PDF

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Publication number
KR970056957A
KR970056957A KR1019950072195A KR19950072195A KR970056957A KR 970056957 A KR970056957 A KR 970056957A KR 1019950072195 A KR1019950072195 A KR 1019950072195A KR 19950072195 A KR19950072195 A KR 19950072195A KR 970056957 A KR970056957 A KR 970056957A
Authority
KR
South Korea
Prior art keywords
analog
digital
counter
address
processing apparatus
Prior art date
Application number
KR1019950072195A
Other languages
Korean (ko)
Inventor
김성운
Original Assignee
배순훈
대우전자 주식회사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 배순훈, 대우전자 주식회사 filed Critical 배순훈
Priority to KR1019950072195A priority Critical patent/KR970056957A/en
Publication of KR970056957A publication Critical patent/KR970056957A/en

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Classifications

    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04NPICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N25/00Circuitry of solid-state image sensors [SSIS]; Control thereof
    • H04N25/70SSIS architectures; Circuits associated therewith
    • H04N25/71Charge-coupled device [CCD] sensors; Charge-transfer registers specially adapted for CCD sensors
    • H04N25/745Circuitry for generating timing or clock signals
    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04NPICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N25/00Circuitry of solid-state image sensors [SSIS]; Control thereof
    • H04N25/70SSIS architectures; Circuits associated therewith
    • H04N25/71Charge-coupled device [CCD] sensors; Charge-transfer registers specially adapted for CCD sensors
    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04NPICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N25/00Circuitry of solid-state image sensors [SSIS]; Control thereof
    • H04N25/70SSIS architectures; Circuits associated therewith
    • H04N25/71Charge-coupled device [CCD] sensors; Charge-transfer registers specially adapted for CCD sensors
    • H04N25/75Circuitry for providing, modifying or processing image signals from the pixel array

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  • Engineering & Computer Science (AREA)
  • Multimedia (AREA)
  • Signal Processing (AREA)
  • Closed-Circuit Television Systems (AREA)
  • Image Input (AREA)
  • Facsimiles In General (AREA)

Abstract

본 발명은 화상처리 장치에 관한 것으로, CCD 카메라(10)에서의 영상신호를 입력받아 디지탈 값으로 변환하는 아날로그/디지탈(A/D) 카운터(20);상기 아날로그/디지탈 카운터(20)에서 변환되는 영상데이타를 어드레스 카운터(50)에서 발생된 어드레스 발생동작에 따라 저장하는 프레임 버퍼(40)를 구비하는 화성처리 장치에 있어서, 상기 아날로그/디지탈 변환기의 아날로그/디지탈 변환동작, 어드레스 카운터의 어드레스 발생동작, CCD 카메라에서의 영상신호 출력동작이 클럭신호에 동기가 맞추어져 동작하도록 기준클럭 발생회로(370)를 구비하여 이루어지는 것을 특징으로 한다.The present invention relates to an image processing apparatus, comprising: an analog / digital (A / D) counter 20 for receiving an image signal from a CCD camera 10 and converting the image signal into a digital value; converting the analog / digital counter 20 In the conversion processing apparatus having a frame buffer 40 for storing the image data to be stored in accordance with the address generating operation generated by the address counter 50, the analog / digital conversion operation of the analog / digital converter, the address generation of the address counter The reference clock generation circuit 370 is provided so that the operation and the video signal output operation from the CCD camera are synchronized with the clock signal.

Description

화상처리 장치Image processing equipment

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제3도는 본 발명에 따른 화상처리 장치의 블록 구성도3 is a block diagram of an image processing apparatus according to the present invention.

제4도는 제3도의 타이밍도이다.4 is a timing diagram of FIG.

Claims (2)

CCD 카메라(10)에서의 영상신호를 입력받아 디지탈 값으로 변환하는 아날로그/디지탈(A/D)카운터(20); 상기 아날로그/디지탈 카운터(20)에서 변환되는 영상데이타를 어드레스 카운터(50)에서 발생된 어드레스 발생동작에 따라 저장하는 프레임 버퍼(40)를 구비하는 화상처리 장치에 있어서, 상기 아날로그/디지탈 변환기의 아날로그/디지탈 변환동작, 어드레스 카운터의 어드레스 발생동작, CCD카메라에서의 영상신호 출력동작이 클럭신호에 동기가 맞추어져 동작하도록 기준클럭 발생회로(370)를 포함하는 것을 특징으로 하는 화상 처리 장치.An analog / digital (A / D) counter 20 which receives an image signal from the CCD camera 10 and converts the image signal into a digital value; An image processing apparatus comprising a frame buffer 40 for storing image data converted by the analog / digital counter 20 in accordance with an address generating operation generated by the address counter 50, wherein the analog of the analog / digital converter is provided. And a reference clock generation circuit (370) so that the digital conversion operation, the address generation operation of the address counter, and the video signal output operation from the CCD camera are synchronized with the clock signal. 제1항에 있어서 상기 화상처리 장치는, 기준클럭 발생회로(370)에서 입력되는 클럭과 동기가 맞추어진 신호를 출력하는 수직/수평동기 발생회로(360)를 더 구비하여 이루어지는 것을 특징으로 하는 화상처리 장치.The image processing apparatus of claim 1, wherein the image processing apparatus further comprises a vertical / horizontal synchronization generating circuit 360 for outputting a signal synchronized with a clock input from the reference clock generating circuit 370. Processing unit. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019950072195A 1995-12-27 1995-12-27 Image processing equipment KR970056957A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019950072195A KR970056957A (en) 1995-12-27 1995-12-27 Image processing equipment

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019950072195A KR970056957A (en) 1995-12-27 1995-12-27 Image processing equipment

Publications (1)

Publication Number Publication Date
KR970056957A true KR970056957A (en) 1997-07-31

Family

ID=66640811

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019950072195A KR970056957A (en) 1995-12-27 1995-12-27 Image processing equipment

Country Status (1)

Country Link
KR (1) KR970056957A (en)

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