KR950023000A - Digital element video signal converter using a combination of pixel and line address - Google Patents
Digital element video signal converter using a combination of pixel and line address Download PDFInfo
- Publication number
- KR950023000A KR950023000A KR1019930030024A KR930030024A KR950023000A KR 950023000 A KR950023000 A KR 950023000A KR 1019930030024 A KR1019930030024 A KR 1019930030024A KR 930030024 A KR930030024 A KR 930030024A KR 950023000 A KR950023000 A KR 950023000A
- Authority
- KR
- South Korea
- Prior art keywords
- signal
- pixel
- decoder
- output
- ccir
- Prior art date
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Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N7/00—Television systems
- H04N7/015—High-definition television systems
Landscapes
- Engineering & Computer Science (AREA)
- Multimedia (AREA)
- Signal Processing (AREA)
- Television Systems (AREA)
- Color Television Systems (AREA)
Abstract
본 발명은 CCIR(International Radio Consultative Committee) 권고안 656형식의 영상 신호를 2채널 디지탈 인코더의 입력으로 이용할 수 있도록 CCIR 권고안 656을 참고하여 하드웨어로 구현한 것이다.The present invention is implemented in hardware with reference to CCIR Recommendation 656 so that a video signal of the International Radio Consultative Committee (CCIR) Recommendation 656 format can be used as an input of a two-channel digital encoder.
본 발명은 CCIR 656영상신호를 입력하여 이 신호에서 타이밍 기준 신호의 값을 알아내 이 값을 이용하여 화소화 라인 카운터를 작동 시켜 카운터의 출력 신호인 화소와 라인 번지수의 조합을 이용하여 656신호를 동기 신호와 CCIR 601의 데이타로 변환하는 장치를 제공한다.The present invention inputs the CCIR 656 image signal to find the value of the timing reference signal from the signal, and operates the pixelized line counter using this value to generate the 656 signal using a combination of pixel and line address, which are the output signals of the counter. The present invention provides an apparatus for converting a signal into a synchronization signal and data of a CCIR 601.
Description
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.
제1도는 본 발명의 주변장치와의 연결구성도,1 is a connection diagram of the peripheral device of the present invention,
제5도는 본 발명에 따른 구성도,5 is a block diagram according to the present invention,
Claims (1)
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR1019930030024A KR970003795B1 (en) | 1993-12-27 | 1993-12-27 | Digital source image-signal change device using the number of pixel and line |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR1019930030024A KR970003795B1 (en) | 1993-12-27 | 1993-12-27 | Digital source image-signal change device using the number of pixel and line |
Publications (2)
Publication Number | Publication Date |
---|---|
KR950023000A true KR950023000A (en) | 1995-07-28 |
KR970003795B1 KR970003795B1 (en) | 1997-03-21 |
Family
ID=19373035
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
KR1019930030024A KR970003795B1 (en) | 1993-12-27 | 1993-12-27 | Digital source image-signal change device using the number of pixel and line |
Country Status (1)
Country | Link |
---|---|
KR (1) | KR970003795B1 (en) |
-
1993
- 1993-12-27 KR KR1019930030024A patent/KR970003795B1/en not_active IP Right Cessation
Also Published As
Publication number | Publication date |
---|---|
KR970003795B1 (en) | 1997-03-21 |
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