KR970057721A - Interlaced / Sequential Scan Compatible Circuits in Image Processing Equipment - Google Patents

Interlaced / Sequential Scan Compatible Circuits in Image Processing Equipment Download PDF

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Publication number
KR970057721A
KR970057721A KR1019950069150A KR19950069150A KR970057721A KR 970057721 A KR970057721 A KR 970057721A KR 1019950069150 A KR1019950069150 A KR 1019950069150A KR 19950069150 A KR19950069150 A KR 19950069150A KR 970057721 A KR970057721 A KR 970057721A
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KR
South Korea
Prior art keywords
analog
digital
field
video signal
units
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Application number
KR1019950069150A
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Korean (ko)
Inventor
이상일
Original Assignee
배순훈
대우전자 주식회사
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Priority to KR1019950069150A priority Critical patent/KR970057721A/en
Publication of KR970057721A publication Critical patent/KR970057721A/en

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Abstract

본 발명은 영상처리장치에 있어서 비월/순차주사 호환회로에 관한 것으로서, 필드 단위로 입력되는 영상신호를 저장하는 제1및 2필드 메모리(21,22), 제 1및 제2필드 메모리에서 필드 단위로 출력되는 영상신호를 아날로그신호로 변환하는 제1및 제2디지탈/아날로그 변환기(23,24), 제 1및 제2디지탈/아날로그 변환기에서 각각 출력되는 필드단위의 아날로그 영상신호를 합성하여 프레임 단위의 아날로그 영상신호를 출력하는 합성기(25),합성기에서 출력되는 프레임 단위의 아날로그 영상신호를 디지탈 영상신호로 변환하는 아날로그/디지탈 변환기(26),아날로그/디지탈 변환기에서 출력되는 프레임 단위의 디지탈 영상신호를 저장하는 프레임 메모리 (27)를 구비한다. 따라서, 비월주사 방식으로 입력되는 영상신호를 필드메모리에 저장한 후, 아날로그신호로 변환하여 합성함으로써 프레임 영상신호를 구성하고, 이를 다시 디지탈신호로 변환하여 프레임 메모리에 저장함으로써 화질을 개선할 수 있다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to interlaced / sequential scan compatible circuits in an image processing apparatus, comprising first and second field memories (21, 22) for storing image signals input in field units, and field units in first and second field memories. Frame unit by synthesizing analog video signals in field units output from the first and second digital to analog converters 23 and 24 and the first and second digital to analog converters respectively. A synthesizer 25 for outputting an analog video signal, an analog / digital converter 26 for converting an analog video signal in a frame unit output from the synthesizer into a digital video signal, and a digital video signal in a frame unit output from an analog / digital converter. It has a frame memory 27 for storing. Therefore, the video signal inputted by the interlaced scanning method is stored in the field memory, and then converted into an analog signal to be synthesized to form a frame video signal, and then converted into a digital signal and stored in the frame memory, thereby improving image quality. .

Description

영상처리장치에 있어서 비월/순차주사 호환회로Interlaced / Sequential Scan Compatible Circuits in Image Processing Equipment

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제2도의 (가)는 영상처리장치에 있어서 본 발명에 의한 비월주사를 순차주사로 변환하는 회로를 나타낸 블럭도,제2도의 (나)는 영상처리장치에 있어서 본 발명에 의한 순차주사를 비월주사로 변환하는 회로를 나타낸 블럭도.FIG. 2A is a block diagram showing a circuit for converting interlaced scanning according to the present invention into a sequential scan in an image processing apparatus, and FIG. 2B is an interlaced progressive scan according to the present invention in an image processing apparatus. A block diagram showing a circuit for converting to scan.

Claims (1)

필드 단위로 입력되는 영상신호를 저장하는 제1및 제2필드 메모리(21,22); 상기 제1 및 제2필드 메모리에서 필드 단위로 출력되는 영상신호를 아날로그신호로 변환하는 제1 및 제2디지탈/아날로그 변환기(23,24);상기 제1및 제2디지탈/아날로그 변환기에서 각각 출력되는 필드단위의 아날로그 영상신호를 합성하여 프레임 단위의 아날로그 영상신호를 출력하는 합성기(25);상기 합성기에서 출력되는 프레임 단위의 아날로그 영상신호를 디지탈 영상신호로 변환하는 아날로그/디지탈 변환기 (26);및 상기 아날로그/디지탈 변환기에서 출력되는 프레임 단위의 디지탈 영상신호를 저장하는 프레임 메모리(27)를 구비하는 것을 특징으로 하는 영상처리장치에 있어서 비월/순차주사 호환회로.First and second field memories 21 and 22 for storing image signals input in units of fields; First and second digital to analog converters 23 and 24 for converting image signals output in field units from the first and second field memories into analog signals; outputting from the first and second digital to analog converters, respectively; A synthesizer (25) for synthesizing the analog video signals in field units and outputting the analog video signals in frame units; an analog / digital converter (26) for converting the analog video signals in frame units output from the synthesizer into digital video signals; And a frame memory (27) for storing a digital image signal in units of frames output from the analog / digital converter. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019950069150A 1995-12-30 1995-12-30 Interlaced / Sequential Scan Compatible Circuits in Image Processing Equipment KR970057721A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019950069150A KR970057721A (en) 1995-12-30 1995-12-30 Interlaced / Sequential Scan Compatible Circuits in Image Processing Equipment

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Application Number Priority Date Filing Date Title
KR1019950069150A KR970057721A (en) 1995-12-30 1995-12-30 Interlaced / Sequential Scan Compatible Circuits in Image Processing Equipment

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KR970057721A true KR970057721A (en) 1997-07-31

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100472436B1 (en) * 2000-08-29 2005-03-07 삼성전자주식회사 Apparatus for processing external input video signal in digital television adaptively

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100472436B1 (en) * 2000-08-29 2005-03-07 삼성전자주식회사 Apparatus for processing external input video signal in digital television adaptively

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