KR940022794A - 반도체 장치의 제조방법 - Google Patents

반도체 장치의 제조방법 Download PDF

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Publication number
KR940022794A
KR940022794A KR1019940004504A KR19940004504A KR940022794A KR 940022794 A KR940022794 A KR 940022794A KR 1019940004504 A KR1019940004504 A KR 1019940004504A KR 19940004504 A KR19940004504 A KR 19940004504A KR 940022794 A KR940022794 A KR 940022794A
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South Korea
Prior art keywords
semiconductor substrate
manufacturing
forming
semiconductor device
region
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KR1019940004504A
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English (en)
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KR0166991B1 (ko
Inventor
히사토 오야마쓰
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사또오 후미오
가부시기가이샤 도시바
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Publication of KR940022794A publication Critical patent/KR940022794A/ko
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Publication of KR0166991B1 publication Critical patent/KR0166991B1/ko

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76202—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO
    • H01L21/76213—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO introducing electrical inactive or active impurities in the local oxidation region, e.g. to alter LOCOS oxide growth characteristics or for additional isolation purpose
    • H01L21/76216—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO introducing electrical inactive or active impurities in the local oxidation region, e.g. to alter LOCOS oxide growth characteristics or for additional isolation purpose introducing electrical active impurities in the local oxidation region for the sole purpose of creating channel stoppers
    • H01L21/76218—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO introducing electrical inactive or active impurities in the local oxidation region, e.g. to alter LOCOS oxide growth characteristics or for additional isolation purpose introducing electrical active impurities in the local oxidation region for the sole purpose of creating channel stoppers introducing both types of electrical active impurities in the local oxidation region for the sole purpose of creating channel stoppers, e.g. for isolation of complementary doped regions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/107—Substrate region of field-effect devices
    • H01L29/1075—Substrate region of field-effect devices of field-effect transistors
    • H01L29/1079—Substrate region of field-effect devices of field-effect transistors with insulated gate
    • H01L29/1083—Substrate region of field-effect devices of field-effect transistors with insulated gate with an inactive supplementary region, e.g. for preventing punch-through, improving capacity effect or leakage current

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Ceramic Engineering (AREA)
  • Element Separation (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)

Abstract

고집적화 및 동작 속도의 향상을 동시에 달성할 수 있는 반도체 장치의 제조방법을 제공한다.
반도체 기판(101)의 표면부에 있어서 소자 분리 영역에 절연막(202,203)을 형성하는 단계와, 절연막(202,203)이 형성된 반도체 기판(101)의 표면중 소망의 영역Ⅱ)에 사진식각법을 사용하여 레지스트막(204)을 형성하는 단계와, 레지스트막 (204)을 마스크로 하여 소망의 영역(Ⅱ)이외의 영역(Ⅰ)에 채널 스토퍼용의 불순물 이온을 주입하는 단계를 포함한다.

Description

반도체 장치의 제조방법
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제1도는 본 발명의 일실시예의 반도체 장치의 제조방법을 설명하는 공정별 소자 단면도.

Claims (2)

  1. 반도체 기판의 표면 부분에 있어서의 소자 분리 영역에 절연막을 형성하는 단계와; 상기 절연막이 형성된 상기 반도체 기판의 표면중 소망의 영역에 사진식각법을 사용하여 레지스트막을 형성하는 단계와; 상기 레지스트막을 마이크로 하여 채널 스토퍼용의 이온을 주입하는 단계를 포함하는 것을 특징으로 하는 반도체 장치의 제조방법.
  2. 제1항에 있어서, 상기 반도체 기판의 표면 부분에 형성된 상기 절연막중 상기 소망의 영역에 형성된 것은 상기 소망의 영역 이외에 형성된 것보다도 폭이 넓게 형성되는 것을 특징으로 하는 반도체 장치의 제조방법.
    ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.
KR1019940004504A 1993-03-11 1994-03-09 반도체 장치 KR0166991B1 (ko)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP93-050955 1993-03-11
JP05095593A JP3462886B2 (ja) 1993-03-11 1993-03-11 半導体装置

Publications (2)

Publication Number Publication Date
KR940022794A true KR940022794A (ko) 1994-10-21
KR0166991B1 KR0166991B1 (ko) 1999-02-01

Family

ID=12873251

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019940004504A KR0166991B1 (ko) 1993-03-11 1994-03-09 반도체 장치

Country Status (4)

Country Link
US (1) US5691564A (ko)
EP (1) EP0615288A3 (ko)
JP (1) JP3462886B2 (ko)
KR (1) KR0166991B1 (ko)

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5672539A (en) * 1994-01-14 1997-09-30 Micron Technology, Inc. Method for forming an improved field isolation structure using ozone enhanced oxidation and tapering
JP2694815B2 (ja) * 1995-03-31 1997-12-24 日本電気株式会社 半導体装置およびその製造方法
EP0762493A1 (en) * 1995-08-03 1997-03-12 Motorola, Inc. Semiconductor device having field oxide regions and a field implant and method of manufacturing the same
JP2919379B2 (ja) * 1996-08-29 1999-07-12 九州日本電気株式会社 半導体装置およびその製造方法
JP3340361B2 (ja) * 1997-10-01 2002-11-05 株式会社東芝 半導体装置及びその製造方法
DE19757609A1 (de) * 1997-12-23 1999-07-01 Siemens Ag Soi-mosfet

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4604790A (en) * 1985-04-01 1986-08-12 Advanced Micro Devices, Inc. Method of fabricating integrated circuit structure having CMOS and bipolar devices
JPH0821681B2 (ja) * 1986-06-18 1996-03-04 株式会社日立製作所 半導体集積回路装置の製造方法
US5065208A (en) * 1987-01-30 1991-11-12 Texas Instruments Incorporated Integrated bipolar and CMOS transistor with titanium nitride interconnections
US5119162A (en) * 1989-02-10 1992-06-02 Texas Instruments Incorporated Integrated power DMOS circuit with protection diode
JP2512216B2 (ja) * 1989-08-01 1996-07-03 松下電器産業株式会社 半導体装置の製造方法
US5107321A (en) * 1990-04-02 1992-04-21 National Semiconductor Corporation Interconnect method for semiconductor devices
JPH0824171B2 (ja) * 1990-05-02 1996-03-06 三菱電機株式会社 半導体記憶装置およびその製造方法
US5173438A (en) * 1991-02-13 1992-12-22 Micron Technology, Inc. Method of performing a field implant subsequent to field oxide fabrication by utilizing selective tungsten deposition to produce encroachment-free isolation
US5393691A (en) * 1993-07-28 1995-02-28 Taiwan Semiconductor Manufacturing Company Fabrication of w-polycide-to-poly capacitors with high linearity

Also Published As

Publication number Publication date
EP0615288A3 (en) 1996-09-11
EP0615288A2 (en) 1994-09-14
US5691564A (en) 1997-11-25
KR0166991B1 (ko) 1999-02-01
JP3462886B2 (ja) 2003-11-05
JPH06268057A (ja) 1994-09-22

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