KR940020565A - 반도체 집적회로(semiconductor integrated circuit) - Google Patents

반도체 집적회로(semiconductor integrated circuit) Download PDF

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Publication number
KR940020565A
KR940020565A KR1019940003086A KR19940003086A KR940020565A KR 940020565 A KR940020565 A KR 940020565A KR 1019940003086 A KR1019940003086 A KR 1019940003086A KR 19940003086 A KR19940003086 A KR 19940003086A KR 940020565 A KR940020565 A KR 940020565A
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South Korea
Prior art keywords
circuit
data
semiconductor integrated
bit line
data line
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KR1019940003086A
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English (en)
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KR0127263B1 (ko
Inventor
마사루 고야나기
츠요시 에토
Original Assignee
사토 후미오
가부시키가이샤 도시바(Kabushiki Kaisha Toshiba)
오카모토 세이시
도시바 마이크로일렉트로닉스 가부시키가이샤(Toshiba Micro-Electronics Corporation)
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Publication of KR940020565A publication Critical patent/KR940020565A/ko
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Publication of KR0127263B1 publication Critical patent/KR0127263B1/ko

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/10—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1048—Data bus control circuits, e.g. precharging, presetting, equalising
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/409—Read-write [R-W] circuits 
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/409—Read-write [R-W] circuits 
    • G11C11/4096—Input/output [I/O] data management or control circuits, e.g. reading or writing circuits, I/O drivers or bit-line switches 
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1051—Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1051—Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
    • G11C7/1069—I/O lines read out arrangements

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Databases & Information Systems (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Dram (AREA)

Abstract

본 발명은 DQ, /DQ 간에 진폭제한회로(101)를 설치하고, 이 회로(101)는 NMOS로 이루어지며 DQ에 소스, /DQ에 드레인이 접속되고, 차동증폭회로(309)의 동작기간에서 DQ, /DQ간의 전위치가 Vth가 되면 도통되도록 VG를 설정한다. VG는 회로(309)의 동작기간(전기간도 가능)에서 Vcc+Vth 이하로 한다. 감지동작에 지장이 없는 범위에서 VG가 Vcc+Vth에 가까운 만큼 DQ, /DQ간 전위치가 보다 작아지는 범위로 Tr이 도통되어 해당 진폭이 작아지게 된다.
DQ, /DQ의 진폭제한에 의해 이퀄라이즈 시간을 단축할 수 있고, DRAM 억세스의 고속화와 감지마진의 향상에 기여할 수 있다. 특히, NMOS 의 채용에 의하면 VG제어용의 회로가 바이어스 만으로 충분하도록 되어 간단하게 된다.

Description

반도체 집적회로(SEMICONDUCTOR INTEGRATED CIRCUIT)
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제1도는 본 발명의 1실시예에 따른 DRAM 독출회로의 구성을 나타낸 회로도,
제2도는 제1도에 나타낸 회로의 동작파형을 나타낸 타임챠트.

Claims (2)

  1. 복수의 DRAM(301)로 이루어진 셀매트릭스와, 각 셀매트릭스의 행어드레스 마다 설치된 워드선(WL), 상기 셀매트릭스의 열어드레스마다 설치된 비트선쌍(BL1, /BL1), 각 비트선쌍을 구성하는 제1, 제2비트선간의 전위치를 증폭하는 비트선차동증폭 회로(302), 상기 비트선쌍 복수조의 전하전송을 받는 데이터선쌍(DQ, /DQ), 상기 비트선쌍 복수조의 각 조마다 설치되면서, 각 비트선쌍 각조로부터 사이 데이터선쌍으로의 전하전송로를 개폐하기 위한 스위치회로(303), 상기 데이터선쌍을 구성하는 제1, 제2데이터선간의 전위차를 증폭하는 데이터선 차동증폭회로(309) 및, 상기 데이터선쌍을 구성하는 제1, 제2데이터선 중 한쪽에 소스가 접속되면서 다른쪽에 드레인이 접속되고, 상기 데이터선 차동증폭회로의 동작기간에 있어서 상기 제1, 제2데이터간의 전위차가 규제치가 되면 도통상태로 되도록 게이트전위가 설정된 트랜지스터(Tr)에 의해 형성되며, 해당 트랜지스터의 도통에 의해 상기 제1, 제2데이터선간의 진폭을 상기 규제치 이하로 제한하도록 기능하는 진폭제한회로(101)를 구비하여 구성된 것을 특징으로 하는 반도체 집적회로.
  2. 제1항에 있어서, 상기 진폭제한회로를 구성하는 트랜지스터로서 NMOS 트랜지스터를 구비하고 있는 것을 특징으로 하는 반도체 집적회로.
    ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임
KR1019940003086A 1993-02-23 1994-02-22 반도체 집적회로 KR0127263B1 (ko)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP3355893 1993-02-23
JP93-33558 1993-02-23

Publications (2)

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KR940020565A true KR940020565A (ko) 1994-09-16
KR0127263B1 KR0127263B1 (ko) 1997-12-29

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US (1) US5659512A (ko)
KR (1) KR0127263B1 (ko)

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Publication number Priority date Publication date Assignee Title
JP2825291B2 (ja) * 1989-11-13 1998-11-18 株式会社東芝 半導体記憶装置
JP3863968B2 (ja) * 1997-06-10 2006-12-27 株式会社ルネサステクノロジ 半導体記憶装置
US5930178A (en) * 1997-11-17 1999-07-27 International Business Machines Corporation Bitline voltage stabilization device and method
KR100295041B1 (ko) * 1998-02-28 2001-07-12 윤종용 프리차지제어회로를구비하는반도체장치및프리차지방법
TW419669B (en) * 1998-03-16 2001-01-21 Nippon Electric Co Semiconductor memory device
JPH11306758A (ja) * 1998-04-27 1999-11-05 Matsushita Electric Ind Co Ltd 半導体記憶装置
JP4338010B2 (ja) * 2002-04-22 2009-09-30 株式会社日立製作所 半導体集積回路装置
JP2004103116A (ja) * 2002-09-10 2004-04-02 Matsushita Electric Ind Co Ltd 半導体装置
US7085173B1 (en) * 2005-02-09 2006-08-01 International Business Machines Corporation Write driver circuit for memory array
JP5441272B2 (ja) 2011-01-28 2014-03-12 株式会社東芝 半導体記憶装置
US10658029B2 (en) * 2018-09-21 2020-05-19 Qualcomm Incorporated High bandwidth double-pumped memory

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KR900006293B1 (ko) * 1987-06-20 1990-08-27 삼성전자 주식회사 씨모오스 디램의 데이터 전송회로
JPH0817034B2 (ja) * 1988-10-24 1996-02-21 三菱電機株式会社 半導体記憶装置
JPH03160689A (ja) * 1989-11-17 1991-07-10 Nec Corp 半導体メモリ
JP2748053B2 (ja) * 1991-07-23 1998-05-06 三菱電機株式会社 半導体記憶装置

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US5659512A (en) 1997-08-19

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