KR930002852B1 - Multiplying circuit of galoa - Google Patents

Multiplying circuit of galoa Download PDF

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KR930002852B1
KR930002852B1 KR1019900023059A KR900023059A KR930002852B1 KR 930002852 B1 KR930002852 B1 KR 930002852B1 KR 1019900023059 A KR1019900023059 A KR 1019900023059A KR 900023059 A KR900023059 A KR 900023059A KR 930002852 B1 KR930002852 B1 KR 930002852B1
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data
galoa
multiplication
rom
circuit
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KR1019900023059A
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KR920013096A (en
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황정환
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주식회사 금성사
이헌조
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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/52—Multiplying; Dividing

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  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computational Mathematics (AREA)
  • Mathematical Analysis (AREA)
  • Mathematical Optimization (AREA)
  • Pure & Applied Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Error Detection And Correction (AREA)

Abstract

The circuit is for detecting and correctg the error caused during the signal process. When multiplying the data of X= x7α7 + x6α6 + x5α5 + x4α4 + x3α3 + x2α2 + x1α1 + x0α0 + and Y = y7α7 + y6α6 + y5α5 + y4α4 + y3α3 + y2α2 + y1α1 + y0α0, α is multiplied to Y and logical ANDing to get x0(Y), x1(Yα), x2(Yα2), x3(Yα3), x4(Yα4), x5(Yα5), x6(Yα6), x7(Yα7). These are EXORed to get the Z= x7(Yα7) + x6(Yα6) + x5(Yα5) + x4(Yα4) + x3(Yα3) + x2(Yα2) + x1(Yα1) + x0Y so that the GF(28) is multiplied.

Description

갈로아(Galoa) 체상의 승산회로Multiplication circuit on Galoa

제 1 도는 종래의 승산회로도.1 is a conventional multiplication circuit diagram.

제 2 도는 본 발명, 갈로아 체상의 승산회로도.2 is a multiplier circuit diagram of the present invention.

제 3 도는 제 2 도의 동작에 대한 개념도.3 is a conceptual diagram of the operation of FIG.

* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings

1, 2 : VE 변환롬 3 : 가산기1, 2: VE conversion ROM 3: Adder

4 : EV 변환롬4: EV conversion ROM

본 발명은 디지탈 신호처리에 관한 것으로, 특히 신호처리과정에서 발생하는 에러(Error)를 검출 및 정정하는데 적당하도록 한 갈로아(Galoa) 체상의 승산회로에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to digital signal processing, and more particularly, to a multiplier circuit on a Galoa body that is suitable for detecting and correcting errors occurring in signal processing.

일반적으로 사용되고 있는 갈로아(Galoa) 체상의 승산회로는 제 1 도에 도시한 바와 같이 a, βb와 같은 백터표시를 a, b와 같은 지수표현으로 변환하는 VE 변환롬(1, 2)과, 지수표현의 데이타를 가산하는 가산기(3)와, 지수형식의 데이타를 벡타표현으로 변환하여 출력하는 EV 변환롬(4)로 구성되어 있다.A multiplier circuit on a Galoa body that is generally used is shown in FIG. VE conversion roms (1, 2) for converting vector representations such as a and β b to exponential representations such as a and b, adders (3) to which the exponent representation data are added, and exponential form data as vector representations. It consists of the EV conversion ROM 4 which converts and outputs.

상기와 같이 구성한 종래의 회로에 대하여 그 동작을 설명하면 다음과 같다.The operation of the conventional circuit configured as described above is as follows.

갈로아 체상의 GF(2m)상의 원을 계산할 때에 X데이타가 X=Xm-1ㆍ m+1+Xm-2ㆍ m-2+Xm-3ㆍ m-3+…+Xㆍ+X0이라면 Z=XㆍY는 Z=XㆍY=Xm-1ㆍ(Yㆍ m-1)+Xm-2ㆍ(Yㆍ m-2)+…+Xㆍ(Yㆍ)+X0ㆍY가 되며 이와 같은 연산식은 에러정정시에 필요한 신드롬(Syndrom)의 생성 및 에러데이타의 위치를 검출하거나 에러데이타를 정정할 때에 적용되는 승산연산이 필요하다. 그러나 이러한 데이타의 승산을 할때에 일반적인 승산회로는 갈로아(Galoa) 체상의 원을 만족시키기 못하므로 곱하고자 하는 데이타를 벡터량으로 보고 그것을 지수표현으로 고친 다음 이를 가산하고 다시 벡터표현으로 변환한다. 즉 a와 b의 승산을 위해 먼저 상기 데이타를 VE 롬(1, 2)에 넣어서 a, b의 데이타로 변환시키고 가산기(3)에 넣어서 a+b를 얻은다음 다시 EV 롬에 넣어서 a+b를 구하여 a× b= a+b를 얻게되며 따라서 데이타의 곱셈을 지수로 표현하여 가산기(3)에서 더함으로써 승연산을 수행하였다.When calculating the circle of GF (2 m ) on the galloa body, the X data is X = Xm-1 m + 1 + Xm-2 m-2 + Xm-3 m-3 +... + X If + X0, Z = X ・ Y is Z = X ・ Y = Xm-1 · (Y m-1 ) + Xm-2 · (Y m-2 ) +... + X (Y This equation requires the generation of a syndrome required for error correction and a multiplication operation applied when detecting the position of error data or correcting the error data. However, when multiplying such data, the general multiplication circuit cannot satisfy the circle on the Galoa, so the data to be multiplied is regarded as a vector quantity, modified by an exponential representation, then added and converted back into a vector representation. In other words with a For multiplication of b , first put the above data into VE roms (1, 2) and convert it into data of a, b, and add it to adder (3) to get a + b, and then put it back into EV rom. Find a + b a × b = We get a + b and thus multiply by multiplying the data by adding them in the adder (3).

그러나 상기와 같은 방식으로 승연산을 수행할 경우에는 롬(ROM)이 3개나 필요하고 또 롬을 동작시키기 위한 클럭 펄스가 요구되는데 일반적으로 롬은 칩(Chip)으로 구현할 때에 많은 면적을 차지하게 되어 칩의 사이즈(Size)를 제한시키므로 집적화에 장애요소로 작용하게 된다.However, when multiplying is performed in the above manner, three ROMs are required and clock pulses are required to operate the ROM. Generally, a ROM takes a large area when implemented as a chip. Since the size of the chip is limited, it becomes an obstacle to integration.

따라서 본 발명은 상기와 같은 종래회로의 결함을 감안하여 게이트회로에 의해 X데이타와 Y데이타에 대한 승연산이 수행되도록 하여 집적도의 향상은 물론 연산속도를 증가시키도록 창안한 것으로 이를 상세히 설명하면 다음과 같다.Therefore, in view of the above-described defects of the conventional circuit, the present invention is designed to increase the integration speed as well as increase the operation speed by performing a multiplication operation on the X data and the Y data by the gate circuit. same.

제 2 도는 본 발명의 GF(28)상에서의 승연산회로도로서 그 구성 및 작용효과를 제 3 도를 통해 상세히 설명하면 다음과 같다.FIG. 2 is a multiplier circuit diagram on the GF 2 8 of the present invention.

즉, x7~x0의 데이타와 Y데이타에 대하여 앤드(AND) 및 배타적-오아(Exclusive-or) 연산을 통해 Z데이타를 얻으며 이때 상기 xi(i=0~7) 데이타는 연속적으로가 곱해져서 X=x7 7+x6 6+5 5+x4 4+x3 3+x2 2+x1 1+x0 0가 되며 따라서 Z=XㆍY=x7 7ㆍY+x6 6ㆍY+…+x0 0ㆍY가 된다. 그런데 상기의 지수표현 1(i=0~7)를 Y데이타와 묶으면 Z=XㆍY=x7(Yㆍ 7)+x6(Yㆍ 6)+x5(Yㆍ 5)+x4(Yㆍ 4)+x3(Yㆍ 3)+x2(Yㆍ 2)+x1(Yㆍ 1)+x0(Yㆍ 0)가 되어 x0~x7의 데이타가 앤드연산을 통해 Y데이타와 곱해질 때에 상기 Y데이타에(상수)가 연속적으로 곱해지며 이 데이타는 다시 배타적-오아(Exclusive-or) 연산으로 합해져서 상기와 같이 Z=XㆍY의 연산이 이루어지며 따라서 GF(28) 상에서의 모든 승산연산이 가능하게 된다.That is, Z data is obtained through AND and Exclusive-or operations on data of x7 to x0 and Y data, wherein the xi (i = 0 to 7) data is continuously Multiplied by X = x7 7 + x6 6 +5 5 + x4 4 + x3 3 + x2 2 + x1 1 + x0 0 , so Z = X, Y = x7 7 ㆍ Y + x6 6 ㆍ Y +.. + x0 0 ㆍ Y. By the way, the above index expression When 1 (i = 0 ~ 7) is combined with Y data, Z = X and Y = x7 (Y 7 ) + x 6 (Y 6 ) + x 5 (Y 5 ) + x 4 (Y 4 ) + x 3 (Y 3 ) + x 2 (Y 2 ) + x 1 (Y 1 ) + x 0 (Y 0 ) and the data of x0 to x7 is multiplied by the Y data through the AND operation. (Constant) is multiplied continuously and this data is summed up again as Exclusive-Or operation so that Z = X · Y operation as above, so all multiplication operations on GF (2 8 ) are possible. Done.

이상에서와 같이 본 발명은 VE롬과 EV롬을 사용하지 않고 게이트에 의해 승산기능을 수행함으로써 칩에서 롬이 차지하는 면적이 줄어 칩의 사이즈(Size)를 현저히 감소시키며 연산속도를 한층 향상시키는 효과가 있다.As described above, the present invention reduces the area occupied by the ROM in the chip without using the VE ROM and the EV ROM, thereby significantly reducing the size of the chip and further improving the operation speed. have.

Claims (1)

GF(28)상의 승산연산회로에 있어서, X=x7 7+x6 6+x5 5+x4 4+x3 3+x2 2+x1 1+x0 0의 데이타를 Y=y7 7+y6 6+y5 5+y4 4+y3 3+y2 2+y1 1+y0 0의 데이타와 승산연산을 할 때 Y에를 곱한 다음 앤드연산을 수행하여 x0(Y), x1(Yㆍ), x2(Yㆍ 2), x3(Yㆍ 3), x4(Yㆍ 4), x5(Yㆍ 5), x6(Yㆍ 6), x7(Yㆍ 7)을 만들고 이를 다시 배타적-오아(Exclusive-or) 연산에 의해 Z=x7(Yㆍ 7)+x6(Yㆍ 6)+x5(Yㆍ 5)+x4(Yㆍ 4)+3(Yㆍ 3)+x2(Yㆍ 2)+x1(Yㆍ 1)+x0ㆍY로 만들어서 CF(28)상의 승산연산이 수행되도록 구성한 것을 특징으로 하는 갈로아(Galoa) 체상의 승산회로.In the multiplication operation circuit on GF (2 8 ), X = x7 7 + x6 6 + x5 5 + x4 4 + x3 3 + x2 2 + x1 1 + x0 0 = Y7 7 + y6 6 + y5 5 + y4 4 + y3 3 + y2 2 + y1 1 + y0 Y when multiplying data with 0 Multiply by and perform an AND operation to x0 (Y), x1 (Y ), x2 (Y 2 ), x3 (Y 3 ), x4 (Y 4 ), x5 (Y 5 ), x6 (Y 6 ), x7 (Y 7 ), and again by an exclusive-or operation, Z = x7 (Y 7 ) + x 6 (Y 6 ) + x 5 (Y 5 ) + x 4 (Y 4 ) + 3 (Y 3 ) + x 2 (Y 2 ) + x 1 (Y 1 ) A multiplication circuit on a Galoa body, characterized in that the multiplication operation on CF (2 8 ) is made to be + x0 · Y.
KR1019900023059A 1990-12-31 1990-12-31 Multiplying circuit of galoa KR930002852B1 (en)

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