KR920013096A - Multiplication circuit on Galoa - Google Patents

Multiplication circuit on Galoa Download PDF

Info

Publication number
KR920013096A
KR920013096A KR1019900023059A KR900023059A KR920013096A KR 920013096 A KR920013096 A KR 920013096A KR 1019900023059 A KR1019900023059 A KR 1019900023059A KR 900023059 A KR900023059 A KR 900023059A KR 920013096 A KR920013096 A KR 920013096A
Authority
KR
South Korea
Prior art keywords
galoa
multiplication circuit
multiplication
circuit
multiplying
Prior art date
Application number
KR1019900023059A
Other languages
Korean (ko)
Other versions
KR930002852B1 (en
Inventor
황정환
Original Assignee
이헌조
주식회사 금성사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 이헌조, 주식회사 금성사 filed Critical 이헌조
Priority to KR1019900023059A priority Critical patent/KR930002852B1/en
Publication of KR920013096A publication Critical patent/KR920013096A/en
Application granted granted Critical
Publication of KR930002852B1 publication Critical patent/KR930002852B1/en

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/52—Multiplying; Dividing

Landscapes

  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computational Mathematics (AREA)
  • Mathematical Analysis (AREA)
  • Mathematical Optimization (AREA)
  • Pure & Applied Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Error Detection And Correction (AREA)

Abstract

내용 없음No content

Description

갈로아(Galoa)체상의 승산회로Multiplication circuit on Galoa

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제2도는 본 발명, 갈로아 체상의 승산회로도, 제3도는 제2도의 동작에 대한 개념도.2 is a multiplier circuit diagram of the present invention, a galoa body, and FIG. 3 is a conceptual diagram of the operation of FIG.

Claims (1)

GF(28)상의 승산연산회로에 있어서, X=x7α7+x6α6+x5α5+x4α4+x3α3+x2α2+x1α1+x0α0의 데이타를Y=y77+y6α6+y5α5+y4α4+y3α3+y2α2+y1α1+y0α0의 데이타와 승산연산을 할 때 Y에 α를 곱한 다음 앤드연산을 수행하여 x0(Y), x1(Yㆍα),x2(Yㆍα2),x3(Yㆍα2),x4(Yㆍα4),x5(Yㆍα5),x6(Yㆍα6),x7(Yㆍα7)을 만들고 이를 다시 배타적-오아(Exclusive-or) 연산에 의해 Z=x7(Yㆍα7)+x6(Yㆍα6)+x5(Yㆍα5)+x4(Yㆍα4)+x3(Yㆍα2)+x2(Yㆍα2)+x1(Yㆍα)+x1(Yㆍα1)+x1(Yㆍα1)+x0ㆍY로 만들어서 GF(28)상의 승산연산이 수행되도록 구성한 것을 특징으로 하는 갈로아(Galoa) 체상의 승산회로.In the multiplication operation circuit on GF (2 8 ), data of X = x7α 7 + x6α 6 + x5α 5 + x4α 4 + x3α 3 + x2α 2 + x1α 1 + x0α 0 are obtained as Y = y7 7 + y6α 6 + y5α 5 When multiplying + y4α 4 + y3α 3 + y2α 2 + y1α 1 + y0α 0 by multiplying Y by α and performing an AND operation, x0 (Y), x1 (Y · α), x2 (Y α 2 ), x 3 (Y · α 2 ), x 4 (Y · α 4 ), x 5 (Y · α 5 ), x6 (Y · α 6 ), x7 (Y · α 7 ) and this is again exclusive-oa Z = x7 (Y · α 7 ) + x6 (Y · α 6 ) + x5 (Y · α 5 ) + x4 (Y · α 4 ) + x3 (Y · α 2 ) + by (Exclusive-or) operation It is configured to perform multiplication operation on GF (2 8 ) by making x2 (Y · α 2 ) + x1 (Y · α) + x1 (Y · α 1 ) + x1 (Y · α 1 ) + x0 · Y Multiplication circuit on the Galoa body. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019900023059A 1990-12-31 1990-12-31 Multiplying circuit of galoa KR930002852B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019900023059A KR930002852B1 (en) 1990-12-31 1990-12-31 Multiplying circuit of galoa

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019900023059A KR930002852B1 (en) 1990-12-31 1990-12-31 Multiplying circuit of galoa

Publications (2)

Publication Number Publication Date
KR920013096A true KR920013096A (en) 1992-07-28
KR930002852B1 KR930002852B1 (en) 1993-04-12

Family

ID=19309389

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019900023059A KR930002852B1 (en) 1990-12-31 1990-12-31 Multiplying circuit of galoa

Country Status (1)

Country Link
KR (1) KR930002852B1 (en)

Also Published As

Publication number Publication date
KR930002852B1 (en) 1993-04-12

Similar Documents

Publication Publication Date Title
KR830008282A (en) Control method of electronic device
DE69332070D1 (en) Control circuit for Galois field
KR890017743A (en) Operation display circuit of switch
DE3680125D1 (en) METHOD AND DEVICE FOR EXECUTING AREA TRANSFORMATION IN A DIGITAL CIRCUIT.
KR920013981A (en) Scramble / Descramble Circuit
KR910002107A (en) Frequency characteristic correction circuit
KR920013096A (en) Multiplication circuit on Galoa
KR920001327A (en) Coefficient multiplication circuit
JPS5396630A (en) Multi-item input unit
JPS5365021A (en) Display unit
KR850700163A (en) Floating point code generation method and device
KR870006716A (en) Digital level detection circuit
JPS52140241A (en) Binary #-digit addition circuit
JPS5376627A (en) Multiple-unput keyboard circuit
KR920015737A (en) Operation circuit
KR920007363A (en) Syndrome Computation Circuit in Binary Code Hollers (BCH) Decoder
KR890003166A (en) C2 encoder parity generation circuit
JPS5383608A (en) Wave generator for electronic musical instruments
JPS52144253A (en) Flip-flop circuit
JPS52107721A (en) Information input terminal unit
SU570026A1 (en) Device for measuring time intervals
JPS52130522A (en) Electromagnetic couplig type data input unit
KR890008672A (en) Error detection prevention of EP ROM data
JPS57202153A (en) Pattern detecting circuit
JPS5667450A (en) Code generating circuit

Legal Events

Date Code Title Description
A201 Request for examination
G160 Decision to publish patent application
E701 Decision to grant or registration of patent right
GRNT Written decision to grant
FPAY Annual fee payment

Payment date: 20010330

Year of fee payment: 9

LAPS Lapse due to unpaid annual fee