KR920018903A - Semiconductor lead frame - Google Patents

Semiconductor lead frame Download PDF

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Publication number
KR920018903A
KR920018903A KR1019910004607A KR910004607A KR920018903A KR 920018903 A KR920018903 A KR 920018903A KR 1019910004607 A KR1019910004607 A KR 1019910004607A KR 910004607 A KR910004607 A KR 910004607A KR 920018903 A KR920018903 A KR 920018903A
Authority
KR
South Korea
Prior art keywords
lead
lead frame
chip
semiconductor lead
wire
Prior art date
Application number
KR1019910004607A
Other languages
Korean (ko)
Other versions
KR940002445B1 (en
Inventor
송영희
이국상
Original Assignee
김광호
삼성전자 주식회사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 김광호, 삼성전자 주식회사 filed Critical 김광호
Priority to KR1019910004607A priority Critical patent/KR940002445B1/en
Publication of KR920018903A publication Critical patent/KR920018903A/en
Application granted granted Critical
Publication of KR940002445B1 publication Critical patent/KR940002445B1/en

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/02—Containers; Seals
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/4826—Connecting between the body and an opposite side of the item with respect to the body

Landscapes

  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Wire Bonding (AREA)
  • Lead Frames For Integrated Circuits (AREA)

Abstract

내용 없음No content

Description

반도체 리이드 프레임Semiconductor lead frame

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제2도는 (가), (나)는 이 발명에 따른 리이드 프레임의 구조도이다.2 is a structural diagram of the lead frame according to the present invention.

Claims (1)

칩(21)상에 리이드(23)가 부착되어 칩(21)의 칩패드(21a)와 와이어 본딩되는 반도체 리이드 프레임에 있어서, 인너리이드(23a)의 폭을 줄이어 인너리이드(23a)간의 간격을 넓히고 상기 인너리이드(23a)에 복수의 와이어본딩부(23a-1), (23a-2)를 형성한 리이드(23)와, 상기 인너리이드(23a)의 주위로 형성되어 칩(21)을 지지하고 칩패드(21a)와 와이어 본딩 되는 보조리이드(25)가 상, 하측으로 대칭되게 형성됨을 특징으로 하는 반도체 리이드 프레임.In a semiconductor lead frame in which a lead 23 is attached to a chip 21 and wire-bonded with the chip pad 21a of the chip 21, the interval between the inner leads 23a is reduced by reducing the width of the inner lead 23a. The lead 23 is formed around the inner lead 23a, and the lead 23 having the plurality of wire bonding portions 23a-1 and 23a-2 formed on the inner lead 23a and the inner lead 23a. The auxiliary lead 25 which is supported and wire-bonded with the chip pad 21a is formed symmetrically upward and downward. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019910004607A 1991-03-23 1991-03-23 Semiconductor leadframe KR940002445B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019910004607A KR940002445B1 (en) 1991-03-23 1991-03-23 Semiconductor leadframe

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019910004607A KR940002445B1 (en) 1991-03-23 1991-03-23 Semiconductor leadframe

Publications (2)

Publication Number Publication Date
KR920018903A true KR920018903A (en) 1992-10-22
KR940002445B1 KR940002445B1 (en) 1994-03-24

Family

ID=19312422

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019910004607A KR940002445B1 (en) 1991-03-23 1991-03-23 Semiconductor leadframe

Country Status (1)

Country Link
KR (1) KR940002445B1 (en)

Also Published As

Publication number Publication date
KR940002445B1 (en) 1994-03-24

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