KR910015063A - 상보형 쌍극 트랜지스터 - Google Patents

상보형 쌍극 트랜지스터 Download PDF

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KR910015063A
KR910015063A KR1019910001012A KR910001012A KR910015063A KR 910015063 A KR910015063 A KR 910015063A KR 1019910001012 A KR1019910001012 A KR 1019910001012A KR 910001012 A KR910001012 A KR 910001012A KR 910015063 A KR910015063 A KR 910015063A
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epitaxial layer
bipolar transistor
conductivity
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에스. 나세르 모하마드
엠. 데사이 사우라비
에프. 보워스 데렉
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제랄드 오. 도노반
프리시전 모 노리딕스, 인코오포레이티드
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    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/06—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
    • H01L27/0611—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region
    • H01L27/0617—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region comprising components of the field-effect type
    • H01L27/0623—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region comprising components of the field-effect type in combination with bipolar transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/082—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including bipolar components only
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/74—Making of localized buried regions, e.g. buried collector layers, internal connections substrate contacts
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/761—PN junctions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8248—Combination of bipolar and field-effect technology
    • H01L21/8249—Bipolar and MOS technology
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/70—Bipolar devices
    • H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
    • H01L29/73—Bipolar junction transistors
    • H01L29/732—Vertical transistors
    • H01L29/7322—Vertical transistors having emitter-base and base-collector junctions leaving at the same surface of the body, e.g. planar transistor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/70—Bipolar devices
    • H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
    • H01L29/73—Bipolar junction transistors
    • H01L29/735—Lateral transistors

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  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Ceramic Engineering (AREA)
  • Bipolar Integrated Circuits (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Bipolar Transistors (AREA)

Abstract

내용 없음

Description

상보형 쌍극 트랜지스터
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제3도는 본 발명에 따라 형성된 상보형 쌍극 트랜지스터 구조물에서 도핑된 제1 및 제2 터브 분리 영역이 있는 초기의 기판을 도시한 단면도, 제4도는 매몰층이 제2터브 분리 영역위에 형성되어 있는 후기의 제조단계에서의 제3도의 구조물을 도시한 단면도, 제5도는 에피택셜층이 기판, 매몰층과 제1및 제2 터브 분리 영역위에 형성되어 있는 후속 제조단계에서의 제4도의 구조물을 도시한 단면도.

Claims (10)

  1. 제1전도율도 도핑된 반도체 기판(62)과; 상기 기판(62)의 상부면으로 연장하며 상기 제1 전도율과 반대의 제2 전도율로 도핑된 터브 분리영역(66)과; 상기 터브 분리영역(66)의 상부면으로 연장하며 상기 제1 전도율의 불순물로서 하나가 다른 하나의 불순물 보다 더 큰 열 확산율을 갖는 최소한 두 형태의 불순물을 갖는 매몰층(68)과; 상기 기판(62), 상기 터브 분리영역(66) 및 상기 매몰층(68)위에 성장되어 상기 제1 전도율로 도핑된 에피택셜층(70)과; 상기 에피택셜층(70)에 놓이며 상기 제2 전도율로 도핑한 도핑된 베이스 영역(94)과; 상기 베이스 영역(94)에 놓이며 상기 제1전도율로 도핑된 에미터영역(92)과; 상기 에피택셜층(70)에 놓이며 상기 제1전도율로 도핑된 콜렉터 영역(96,70)을 구비하는 것을 특징으로 하는 쌍극 트랜지스터 구조물.
  2. 제1항에 있어서, 상기 터브 분리영역(66)과 전기 접촉하여 상기 에피택셜층에 놓이며 상기 제2 전도율로 도핑된 수직형 분리 영역(82,84)을 추가로 구비하는 것을 특징으로 하는 쌍극 트랜지스터 구조물.
  3. 제1항에 있어서, 상기 최소한 두 형태의 불순물은 비소 또는 안티몬과 3가의 인이온으로서, 비소 또는 안티몬 불순물 이온의 초기 농도는 입방 센티미터당 약 1018-1019이온이고 3가 인 불순물 이온의 초기 농도는 입방센티미터당 약 5×1015-5×1016이온인 것을 특징으로 하는 쌍극 트랜지스터 구조물.
  4. 제1항에 있어서, 상기 터브 분리영역(66)과 상기 매몰층(68) 사이에 위치하며, 상기 제1전도율의 그레이드식 도핑을 갖는 단절연 영역(86)을 추가로 구비하는 것을 특징으로 하는 쌍극 트랜지스터 구조물.
  5. N-형 반도체기판(62)과, 상기 기판의 상부면으로 연장하는 제1의 p터브 분리영역(64)과; 상기 기판(62)및 상기 제1의 p터브 분리영역(64)위로 성장된 N-형 에피택셜층(70); 상기 에피택셜층(70)에 놓인 p-형 콜렉터 영역(80); 상기 p-형 콜렉터 영역(80)에 노인 N-형 베이스 영역(90); 및 상기 N-형 베이스 영역(90)에 놓인 P-형 에미터 영역(88)을 포함하는 PNP쌍극 트랜지스터 구조물과, 상기 기판(62)의 상부면으로 연장하는 제2의 p터브 분리 영역(66); 상기 제2의 p터브 분리영역(66)의 상부면으로 연장하는 N-형 매몰층(68); 상기 기판(62)과 상기 제2의 p터브 분리 영역(66)위에 성장된 N-형 에피택셜층(70); 상기 에피택셜층(70)에 놓인 P-형 베이스영역(84); 상기 에피택셜층(70)에 놓인 N-형 콜렉터 영역(96,70); 및 상기 베이스 영역(84)에 놓인 N-형 에미터영역(92)을 포함하는 NPN쌍극 트랜지스터 구조물을 구비하는 것을 특징으로 하는 상보형 쌍극 트랜지스터 구조물.
  6. N-형 에피택셜층(70)을 갖는 공통 기판(62)상에 상보형 P-채널 및 P-채널 금속 산화막 반도체(CMOS)트랜지스터를 동시에 갖는 상보형 PNP및 NPN쌍극 트랜지스터 제조방법에 있어서, 상기 에피택셜층(70)으로 의 P-형 불순물의 공통확산에 의해 N-채널 MOS트랜지스터에 대한 P-웰과 PNP쌍극 트랜지스터층에 대한 콜렉터 웰(80)을 형성하는 단계와, PNP쌍극 트랜지스터에 대한 상기 콜렉터 웰(80)내 에 베이스(83)및 에미터(90)를, NPN쌍극 트랜지스터에 대한 상기 에피택셜층(70) 내에 베이스(94), 에미터(92) 및 콜렉터(96)를 N-채널 MOS트랜지스터에 대한 상기 P-웰 내에 소스 및 드레인을, P-채널 MOS트랜지스터에 대한 상기 에피택셜층(70)내에 소스 및 드레인을 형성하는 단계를 구비하는 것을 특징으로 하는 상보 형 PNP 및 NPN쌍극 트랜지스터 제조방법.
  7. 제6항에 있어서, 상기 P-웰 및 콜렉터 웰(80) 확산과 공통인 P-형 불순물이 확산으로 NPN쌍극 트랜지스터 주위의 에피택셜층(70)에 P-형 분리 장벽(82,84)가 형성되는 것을 특징으로 하는 방법.
  8. 제6항에 있어서, 상기 P-채널 MOS트랜지스터의 소스 및 드레인과 상기 PNP 쌍극 트랜지스터의 에미터(88)는 P-형 불순물의 공통확산에 의해 형성되는 것을 특징으로 하는 방법.
  9. 제6항에 있어서, 상기 N-채널 MOS 트랜지스터의 소스 및 드레인과 상기 NPN 쌍극 트랜지스터의 에미터(92)는 N-형 불순물의 공통확산에 의해 형성되는 것을 특징으로 하는 방법.
  10. 제9항에 있어서, 상기 N-채널 MOS 트랜지스터에 대한 안내링과 상기 NPN 쌍극 트랜지스터의 베이스(94)는 P-형 불순물의 공통 확산에 의해 형성되며, 상기 NPN 쌍극 트랜지스터의 에미터(92)는 그 트랜지스터의 베이스(94)내에 형성되는 것을 특징으로 하는 방법.
    ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.
KR1019910001012A 1990-01-25 1991-01-22 상보형 쌍극 트랜지스터 KR930010119B1 (ko)

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US5268312A (en) * 1992-10-22 1993-12-07 Motorola, Inc. Method of forming isolated wells in the fabrication of BiCMOS devices
KR0157334B1 (ko) * 1993-11-17 1998-10-15 김광호 반도체 메모리 장치의 전압 승압회로
EP0788151A1 (en) * 1996-01-31 1997-08-06 Consorzio per la Ricerca sulla Microelettronica nel Mezzogiorno - CoRiMMe Method of fabricating junction-isolated semiconductor devices
US6410963B1 (en) * 2001-10-16 2002-06-25 Macronix International Co., Ltd. Electrostatic discharge protection circuits with latch-up prevention function
CN110767741B (zh) * 2019-10-17 2023-09-15 上海华力集成电路制造有限公司 Nmos管及其制造方法

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IT1214808B (it) * 1984-12-20 1990-01-18 Ates Componenti Elettron Tico e semiconduttore processo per la formazione di uno strato sepolto e di una regione di collettore in un dispositivo monoli
JPS61276359A (ja) * 1985-05-31 1986-12-06 Nec Corp 半導体装置およびその製造方法
IT1218230B (it) * 1988-04-28 1990-04-12 Sgs Thomson Microelectronics Procedimento per la formazione di un circuito integrato su un substrato di tipo n,comprendente transistori pnp e npn verticali e isolati fra loro

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