KR910007132A - 반도체장치의 제조방법 - Google Patents
반도체장치의 제조방법Info
- Publication number
- KR910007132A KR910007132A KR1019900014302A KR900014302A KR910007132A KR 910007132 A KR910007132 A KR 910007132A KR 1019900014302 A KR1019900014302 A KR 1019900014302A KR 900014302 A KR900014302 A KR 900014302A KR 910007132 A KR910007132 A KR 910007132A
- Authority
- KR
- South Korea
- Prior art keywords
- manufacturing
- semiconductor device
- semiconductor
- Prior art date
Links
- 238000004519 manufacturing process Methods 0.000 title 1
- 239000004065 semiconductor Substances 0.000 title 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
- H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
- H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
- H01L27/092—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
- H01L27/0928—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors comprising both N- and P- wells in the substrate, e.g. twin-tub
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/8238—Complementary field-effect transistors, e.g. CMOS
- H01L21/823892—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the wells or tubs, e.g. twin tubs, high energy well implants, buried implanted layers for lateral isolation [BILLI]
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10S148/00—Metal treatment
- Y10S148/01—Bipolar transistors-ion implantation
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Manufacturing & Machinery (AREA)
- Semiconductor Memories (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP1232904A JPH081930B2 (ja) | 1989-09-11 | 1989-09-11 | 半導体装置の製造方法 |
JP1-232904 | 1989-09-11 |
Publications (2)
Publication Number | Publication Date |
---|---|
KR910007132A true KR910007132A (ko) | 1991-04-30 |
KR940004454B1 KR940004454B1 (ko) | 1994-05-25 |
Family
ID=16946660
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
KR1019900014302A KR940004454B1 (ko) | 1989-09-11 | 1990-09-11 | 반도체장치의 제조방법 |
Country Status (5)
Country | Link |
---|---|
US (2) | US5460984A (ko) |
EP (1) | EP0417715B1 (ko) |
JP (1) | JPH081930B2 (ko) |
KR (1) | KR940004454B1 (ko) |
DE (1) | DE69031702T2 (ko) |
Families Citing this family (15)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2682425B2 (ja) * | 1993-12-24 | 1997-11-26 | 日本電気株式会社 | 半導体装置の製造方法 |
JPH0878776A (ja) * | 1994-09-06 | 1996-03-22 | Fuji Xerox Co Ltd | 半導体レーザ装置 |
US5573963A (en) * | 1995-05-03 | 1996-11-12 | Vanguard International Semiconductor Corporation | Method of forming self-aligned twin tub CMOS devices |
KR0146080B1 (ko) * | 1995-07-26 | 1998-08-01 | 문정환 | 반도체 소자의 트윈 웰 형성방법 |
DE19534784C1 (de) * | 1995-09-19 | 1997-04-24 | Siemens Ag | Halbleiter-Schaltungselement und Verfahren zu seiner Herstellung |
US5573962A (en) * | 1995-12-15 | 1996-11-12 | Vanguard International Semiconductor Corporation | Low cycle time CMOS process |
KR100189739B1 (ko) * | 1996-05-02 | 1999-06-01 | 구본준 | 반도체 기판에 삼중웰을 형성하는 방법 |
US5776816A (en) * | 1996-10-28 | 1998-07-07 | Holtek Microelectronics, Inc. | Nitride double etching for twin well align |
CN1067800C (zh) * | 1996-11-14 | 2001-06-27 | 联华电子股份有限公司 | 集成电路的制造方法 |
US6017787A (en) * | 1996-12-31 | 2000-01-25 | Lucent Technologies Inc. | Integrated circuit with twin tub |
DE19752848C2 (de) * | 1997-11-28 | 2003-12-24 | Infineon Technologies Ag | Elektrisch entkoppelter Feldeffekt-Transistor in Dreifach-Wanne und Verwendung desselben |
KR100263909B1 (ko) * | 1998-06-15 | 2000-09-01 | 윤종용 | 반도체 집적회로의 다중 웰 형성방법 |
FR2826507B1 (fr) * | 2001-06-21 | 2004-07-02 | St Microelectronics Sa | Procede de traitement de zones complementaires de la surface d'un substrat et produit semi-conducteur obtenu par ce procede |
JP6216142B2 (ja) * | 2012-05-28 | 2017-10-18 | キヤノン株式会社 | 半導体装置の製造方法 |
CN106653599B (zh) * | 2015-11-02 | 2021-03-16 | 中芯国际集成电路制造(上海)有限公司 | 半导体装置及其制造方法 |
Family Cites Families (13)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US3212162A (en) * | 1962-01-05 | 1965-10-19 | Fairchild Camera Instr Co | Fabricating semiconductor devices |
JPS5737877A (en) * | 1980-08-20 | 1982-03-02 | Seiko Epson Corp | Semiconductor device |
DE3149185A1 (de) * | 1981-12-11 | 1983-06-23 | Siemens AG, 1000 Berlin und 8000 München | Verfahren zur herstellung benachbarter mit dotierstoffionen implantierter wannen bei der herstellung von hochintegrierten komplementaeren mos-feldeffekttransistorschaltungen |
US4567644A (en) * | 1982-12-20 | 1986-02-04 | Signetics Corporation | Method of making triple diffused ISL structure |
JPS60105267A (ja) * | 1983-11-14 | 1985-06-10 | Toshiba Corp | 半導体装置の製造方法 |
JPS60138955A (ja) * | 1983-12-27 | 1985-07-23 | Toshiba Corp | 半導体装置の製造方法 |
JPS60194558A (ja) * | 1984-03-16 | 1985-10-03 | Hitachi Ltd | 半導体装置の製造方法 |
JPH0793282B2 (ja) * | 1985-04-15 | 1995-10-09 | 株式会社日立製作所 | 半導体装置の製造方法 |
EP0260271A1 (en) * | 1986-03-04 | 1988-03-23 | Motorola, Inc. | High/low doping profile for twin well process |
JPS63207169A (ja) * | 1987-02-24 | 1988-08-26 | Toshiba Corp | 半導体記憶装置及びその製造方法 |
US4795716A (en) * | 1987-06-19 | 1989-01-03 | General Electric Company | Method of making a power IC structure with enhancement and/or CMOS logic |
US5260226A (en) * | 1987-07-10 | 1993-11-09 | Kabushiki Kaisha Toshiba | Semiconductor device having different impurity concentration wells |
US4983534A (en) * | 1988-01-05 | 1991-01-08 | Nec Corporation | Semiconductor device and method of manufacturing the same |
-
1989
- 1989-09-11 JP JP1232904A patent/JPH081930B2/ja not_active Expired - Lifetime
-
1990
- 1990-09-10 US US07/580,319 patent/US5460984A/en not_active Expired - Lifetime
- 1990-09-11 KR KR1019900014302A patent/KR940004454B1/ko not_active IP Right Cessation
- 1990-09-11 EP EP90117452A patent/EP0417715B1/en not_active Expired - Lifetime
- 1990-09-11 DE DE69031702T patent/DE69031702T2/de not_active Expired - Fee Related
-
1997
- 1997-05-19 US US08/858,879 patent/US6011292A/en not_active Expired - Fee Related
Also Published As
Publication number | Publication date |
---|---|
EP0417715A1 (en) | 1991-03-20 |
US6011292A (en) | 2000-01-04 |
DE69031702T2 (de) | 1998-04-02 |
KR940004454B1 (ko) | 1994-05-25 |
JPH081930B2 (ja) | 1996-01-10 |
DE69031702D1 (de) | 1997-12-18 |
US5460984A (en) | 1995-10-24 |
JPH0397261A (ja) | 1991-04-23 |
EP0417715B1 (en) | 1997-11-12 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
A201 | Request for examination | ||
E902 | Notification of reason for refusal | ||
G160 | Decision to publish patent application | ||
E701 | Decision to grant or registration of patent right | ||
GRNT | Written decision to grant | ||
FPAY | Annual fee payment |
Payment date: 20100428 Year of fee payment: 17 |
|
EXPY | Expiration of term |