CN106653599B - 半导体装置及其制造方法 - Google Patents

半导体装置及其制造方法 Download PDF

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CN106653599B
CN106653599B CN201510733008.3A CN201510733008A CN106653599B CN 106653599 B CN106653599 B CN 106653599B CN 201510733008 A CN201510733008 A CN 201510733008A CN 106653599 B CN106653599 B CN 106653599B
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doped region
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CN106653599A (zh
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周飞
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Semiconductor Manufacturing International Shanghai Corp
Semiconductor Manufacturing International Beijing Corp
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Semiconductor Manufacturing International Beijing Corp
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Abstract

本发明公开了一种半导体装置及其制造方法，涉及半导体技术领域。其中，方法包括：提供包括半导体衬底和在衬底上的多个半导体鳍片的衬底结构；在各鳍片之间形成隔离区以至少基本填充满各鳍片之间的空间；对衬底结构的至少一部分进行第一掺杂，以形成至少部分地在衬底中且与多个鳍片中的一部分鳍片邻接或者交叠的阱区；去除隔离区的一部分以露出多个鳍片中各鳍片的至少一部分；对多个鳍片中的与阱区邻接或者交叠的第一组鳍片的每一个鳍片的至少一部分进行第二掺杂以形成第一掺杂区；对多个鳍片中的与第一组鳍片不同的第二组鳍片的每一个鳍片的至少一部分进行第三掺杂，以形成第二掺杂区；第一掺杂区具有与第二掺杂区不同、与阱区相同的导电类型。

Description

半导体装置及其制造方法
技术领域
本发明涉及半导体技术领域，尤其涉及半导体装置及其制造方法，更具体的，涉及一种鳍片式二极管及其制造方法。
背景技术
随着金属氧化物半导体场效应晶体管(Metal Oxide Semiconductor FieldEffect Transistor，MOSFET)关键尺寸的缩小，短沟道效应(Short Channel Effect，SCE)成为一个至关重要的问题。鳍式场效应晶体管(Fin Field Effect Transistor，FinFET)具有良好的栅控能力，能够有效地抑制短沟道效应。并且，FinFET降低了器件的随机掺杂波动(Random Dopant Fluctuation，RDF)，提高了器件的稳定性。因此，在小尺寸的半导体元件设计中通常采用FinFET器件。
静电放电(Electro-Static Discharge，ESD)现象对半导体器件来说是一个严重的问题，尤其是对于FinFET器件，由于器件的关键尺寸更小，器件更容易由于静电放电现象而失效。因此，ESD器件对于FinFET器件来说很关键。二极管类型的ESD器件通常包括栅控二极管和浅沟槽隔离(Shallow Trench Isolation，STI)二极管，但由于栅控二极管的寄生电容较大，因此，在高频应用中STI二极管具有更好的性能。
因此，期望提出一种适于FinFET制造工艺的鳍片式二极管，减轻或者避免FinFET器件受静电放电现象的影响。
发明内容
本公开的一个实施例的目的在于提出一种新颖的鳍片式二极管及其制造方法。
根据本公开的一个实施例，提供了一种半导体装置的制造方法，包括以下步骤：提供衬底结构，所述衬底结构包括半导体衬底和位于所述衬底上的多个半导体鳍片；在各个鳍片之间形成隔离区以至少基本填充满各个鳍片之间的空间；在所述填充步骤之后，对所述衬底结构的至少一部分进行第一掺杂，以形成阱区，所述阱区至少部分地在所述衬底中且与所述多个鳍片中的一部分鳍片邻接或者交叠；去除所述隔离区的一部分以露出所述多个鳍片中各鳍片的至少一部分；对所述多个鳍片中的与所述阱区邻接或者交叠的第一组鳍片的每一个鳍片的至少一部分进行第二掺杂，以形成第一掺杂区；以及对所述多个鳍片中的与所述第一组鳍片不同的第二组鳍片的每一个鳍片的至少一部分进行第三掺杂，以形成第二掺杂区；其中，所述第一掺杂区具有与所述第二掺杂区不同的导电类型，所述第一掺杂区具有与所述阱区相同的导电类型。
在一个实施方式中，所述阱区在所述衬底的一部分之上。
在一个实施方式中，所述对所述衬底结构的至少一部分进行第一掺杂的步骤包括：对所述衬底结构进行第一预掺杂，以形成位于所述衬底中且与所述多个鳍片中的一部分鳍片邻接的预掺杂区；对所述预掺杂区的一部分进行第二预掺杂，在所述预掺杂区中形成所述阱区，所述阱区在所述预掺杂区的一部分之上，其中所述阱区和所述预掺杂区具有不同的导电类型。
在一个实施方式中，所述第一掺杂区与所述阱区邻接；所述第二掺杂区与所述预掺杂区的其余部分邻接，并具有与所述其余部分相同的导电类型。
在一个实施方式中，所述对所述衬底结构的至少一部分进行第一掺杂的步骤包括：对所述衬底结构进行第一预掺杂，以形成与所述多个鳍片中的一部分鳍片交叠的预掺杂区；对所述预掺杂区的一部分进行第二预掺杂，在所述预掺杂区中形成所述阱区，所述阱区在所述预掺杂区的一部分之上，其中所述阱区和所述预掺杂区具有不同的导电类型。
在一个实施方式中，所述第一掺杂区与所述阱区邻接；并且所述第二掺杂区与所述预掺杂区的其余部分邻接，并具有与所述预掺杂区的其余部分相同的导电类型。
在一个实施方式中，所述第一掺杂区的掺杂浓度大于所述阱区的掺杂浓度；所述第二掺杂区的掺杂浓度大于所述预掺杂区的其余部分的掺杂浓度。
在一个实施方式中，所述阱区包括第一阱区和第二阱区，所述对所述衬底结构的至少一部分进行第一掺杂的步骤包括：对所述衬底结构进行第一预掺杂，以形成位于所述衬底中且与所述多个鳍片中的一部分鳍片邻接的预掺杂区；对所述预掺杂区的一部分进行第二预掺杂，在所述预掺杂区中形成第二阱区，所述第二阱区在所述预掺杂区的一部分之上，所述预掺杂区的其余部分作为第一阱区，其中所述第一阱区和所述第二阱区具有不同的导电类型。
在一个实施方式中，所述第一掺杂区与所述第二阱区邻接；所述第二掺杂区与所述第一阱区邻接，并具有与所述第一阱区相同的导电类型。
在一个实施方式中，所述提供衬底结构的步骤包括：提供初始衬底，所述初始衬底包括初始半导体层；在所述初始半导体层上形成图案化的硬掩模；以所述图案化的硬掩模为掩模对所述初始半导体层进行刻蚀，从而形成所述多个半导体鳍片。
在一个实施方式中，所述衬底结构还包括位于所述多个半导体鳍片上的硬掩模，所述方法还包括：去除所述多个半导体鳍片上的硬掩模。
在一个实施方式中，所述硬掩模包括缓冲层和在所述缓冲层上的硬掩模层。
在一个实施方式中，所述在各个鳍片之间形成隔离区包括：沉积隔离材料以填充各个鳍片之间的空间并覆盖所述鳍片；对所述隔离材料进行平坦化，以使隔离材料的顶表面与所述鳍片的顶表面基本齐平，从而在各个鳍片之间形成所述隔离区。
在一个实施方式中，所述方法还包括：在沉积隔离材料之前，在所述衬底和各个鳍片的表面形成衬垫层；在去除所述隔离区的一部分时，还去除所述隔离区的所述一部分的两侧的衬垫层，以露出所述多个鳍片中各鳍片的至少一部分。
在一个实施方式中，所述第一掺杂区的掺杂浓度大于所述阱区的掺杂浓度。
根据本公开的另一个实施例，提出一种半导体装置，包括：衬底结构，所述衬底结构包括半导体衬底和位于所述衬底上的多个半导体鳍片；第一掺杂区，至少部分地位于衬底中；第二掺杂区，至少部分地位于衬底中且在所述第一掺杂区的一部分之上，所述第一掺杂区与所述第二掺杂区具有不同的导电类型，所述第一掺杂区与所述第二掺杂区邻接并形成结，所述结的界面位于所述衬底中；位于所述第一掺杂区上的第一组半导体鳍片；位于所述第二掺杂区上的第二组半导体鳍片；其中，所述第一掺杂区与所述第一组鳍片具有相同的导电类型，所述第二掺杂区与所述第二组鳍片具有相同的导电类型。
在一个实施方式中，所述装置还包括：位于所述第一组半导体鳍片和所述第二组半导体鳍片中的各个鳍片之间的隔离区。
在一个实施方式中，所述第一组半导体鳍片包括掺杂浓度大于所述第一掺杂区的掺杂浓度的部分；所述第二组半导体鳍片包括掺杂浓度大于所述第二掺杂区的掺杂浓度的部分。
根据本公开的实施例，提供了与FinFET工艺兼容的半导体装置(鳍片式二极管)的制造方法，并且在形成阱区(例如第一阱区和第二阱区)时，是在隔离材料的平坦化工艺之后进行的掺杂，因此可以使得形成的阱区中的杂质分布更加均匀。另外，所形成的鳍片式二极管的一个实施例中，由于二极管中第一阱区和第二阱区邻接形成的结的界面位于衬底中，增大了ESD电流通过的面积，降低了二极管的导通电阻Ron。
通过以下参照附图对本公开的示例性实施例的详细描述，本公开的其它特征、方面及其优点将会变得清楚。
附图说明
附图构成本说明书的一部分，其描述了本公开的示例性实施例，并且连同说明书一起用于解释本发明的原理，在附图中：
图1是根据本公开一个实施例的半导体装置的制造方法的简化流程图；
图2A示出了根据本公开一个实施例的衬底结构的示意截面图；
图2B示出了根据本公开另一个实施例的衬底结构的示意截面图；
图3A和图3B示出了根据本公开一个实施例的形成图2A和图2B的衬底结构的工艺过程；
图4A-图4D示出了根据本公开不同实施例的在各个鳍片之间形成隔离区的工艺过程的示意截面图；
图5A-图5D示出了根据本公开不同实施例的对衬底结构的至少一部分进行第一掺杂后的示意截面图；
图6A-图6D示出了根据本公开不同实施例的去除隔离区的一部分后的示意截面图；
图7A-图7C示出了根据本公开不同实施例的形成第一掺杂区和第二掺杂区后的示意截面图；
图8A和图8B示出了根据本公开一个实施例的半导体装置的结构示意图。
具体实施方式
现在将参照附图来详细描述本公开的各种示例性实施例。应理解，除非另外具体说明，否则在这些实施例中阐述的部件和步骤的相对布置、数字表达式和数值不应被理解为对本发明范围的限制。
此外，应当理解，为了便于描述，附图中所示出的各个部件的尺寸并不必然按照实际的比例关系绘制，例如某些层的厚度或宽度可以相对于其他层有所夸大。
以下对示例性实施例的描述仅仅是说明性的，在任何意义上都不作为对本发明及其应用或使用的任何限制。
对于相关领域普通技术人员已知的技术、方法和装置可能不作详细讨论，但在适用这些技术、方法和装置情况下，这些技术、方法和装置应当被视为本说明书的一部分。
应注意，相似的标号和字母在下面的附图中表示类似项，因此，一旦某一项在一个附图中被定义或说明，则在随后的附图的说明中将不需要对其进行进一步讨论。
图1是根据本公开一个实施例的半导体装置的制造方法的简化流程图。如图1所示，在步骤101，提供衬底结构。图2A示出了根据本公开一个实施例的衬底结构的示意截面图。如图2A所示，该衬底结构包括半导体衬底201和位于衬底201上的多个半导体鳍片202，各个鳍片202之间具有空间203。图2B示出了根据本公开另一个实施例的衬底结构的示意截面图。如图2B所示，该衬底结构除了包括半导体衬底201和位于衬底201上的多个半导体鳍片202外，还包括位于各个半导体鳍片202上的硬掩模204。
图3A和图3B示出了根据本公开一个实施例的形成图2A和图2B的衬底结构的工艺过程。
如图3A所示，提供初始衬底，该初始衬底包括初始半导体层301，初始半导体层301例如可以是硅(Si)层、锗(Ge)层或其他元素半导体层，或者是砷化镓(GaAs)等化合物半导体层。然而本公开并不限于此。
如图3B所示，在初始半导体层301上形成图案化的硬掩模204。该硬掩模204例如可以是硅的氮化物、硅的氧化物、硅的氮氧化物等等。在某些实现方式中，可选地，硬掩模204还可以包括在初始半导体层301与硬掩模204之间的缓冲层(未示出)，例如硅的氧化物。该缓冲层的存在有利于硬掩模204与初始半导体层301之间的结合。
之后，以图案化的硬掩模204为掩模对初始半导体层301进行刻蚀，例如干法刻蚀，以形成半导体衬底201和位于衬底201上的多个半导体鳍片202，从而形成图2B所示的衬底结构。进一步地，可以通过额外的步骤将硬掩模204去除，从而形成图2A所示的衬底结构。
应明白，也可以根据现有的其他方式来形成上述衬底结构，在此不再赘述。
参见图1，在步骤103，在各个鳍片之间形成隔离区以至少基本填充满各个鳍片之间的空间。
下面结合图4A-图4D对不同实施例中形成隔离区的步骤进行说明。
如图4A所示，沉积隔离材料401以填充各个鳍片之间的空间203并覆盖各个鳍片202。例如，可以通过诸如流式化学气相沉积(Flowable Chemical Vapour Deposition,FCVD)的CVD技术等沉积隔离材料(例如电介质材料)来填充空间203并覆盖各个鳍片202。这里，如果鳍片202具有硬掩模204，则隔离材料401填充各个鳍片之间的空间并覆盖各个鳍片上的硬掩模204，如图4B所示。可选地，在沉积隔离材料401之前，还可以在衬底201和各个鳍片202的表面形成衬垫层(例如，通过热氧化形成薄的氧化硅层，未示出)，以修复在刻蚀形成鳍片时对衬底201和各个鳍片202造成的表面损伤。这里，各个鳍片的表面的衬垫层的一部分可能会在随后对隔离区的回刻蚀工艺中被去除。
如图4C所示，对隔离材料401进行平坦化，例如可以对隔离材料进行化学机械抛光，以使隔离材料401的顶表面与鳍片202的顶表面基本齐平，从而在各个鳍片202之间形成隔离区402。这里，如果鳍片202上具有硬掩模204，则对隔离材料401进行平坦化时也可以去除鳍片上的硬掩模204，从而使隔离材料401的顶表面与鳍片202的顶表面基本齐平。然而，应理解，也可以在适当时通过其它步骤来去除该硬掩模204。也就是说，平坦化工艺也可以使得隔离材料401的顶表面与硬掩模204的顶表面基本齐平，如图4D所示。
需要说明，在后续步骤105-步骤111的描述中，仅以不包括硬掩模204的情况(即图4C)为例进行说明。
继续参见图1，在步骤105，对衬底结构的至少一部分进行第一掺杂，以形成阱区。所述阱区至少部分地在所述衬底中，且与所述多个鳍片中的一部分鳍片邻接或者与之交叠，如图5A-5D所示。
图5A-图5D示出了根据本公开不同实施例的对衬底结构的至少一部分进行第一掺杂的示意截面图。
在一个实施例中，如图5A所示，对衬底结构中的衬底201进行第一掺杂(例如离子注入)以形成位于衬底201中的阱区501。这里，第一掺杂例如是N型掺杂，所形成的阱区501为N阱；或者，第一掺杂例如是P型掺杂，所形成的阱区501为P阱。示例性地，可以通过离子注入的方式形成N阱和P阱。例如，形成N阱的注入条件可以为：注入离子为磷离子、注入能量为120-180KeV，注入剂量为5.0×102-5.0×103atom/cm2。形成P阱的注入条件可以为：注入离子为硼离子，注入能量为40-80KeV，注入剂量为5.0×1012-1.0×1014atom/cm2。另外，在进行第一掺杂后，可以进行退火工艺，例如快速热退火RTA，以激活掺入的杂质。退火条件可以示例性的为：退火温度为950-1050℃,退火时间为5-20s。应理解，在前述掺杂和/或退火工艺中，掺入的杂质可能会存在于一部分鳍片(例如202)中或向鳍片202中扩散，从而使得形成的阱区501还包括鳍片202的一部分(如图5B所示)，也即阱区501可以与对应的鳍片202交叠。
在另一个实施例中，如图5C所示，可以首先对衬底结构进行第一预掺杂，以形成位于衬底中的阱区(这里，在不同实施例中其也可称为掺杂区或预掺杂区)501。然后，对预掺杂区501的一部分进行第二预掺杂，从而在预掺杂区501中形成阱区521，预掺杂区501的其余部分作为阱区511(这里，将阱区511也称为第一阱区，将阱区521也称为第二阱区)。这里，第一阱区511和第二阱区521具有不同的导电类型。例如，第一阱区511为N阱、第二阱区521为P阱，反之亦然。与上面类似地，在进行第一预掺杂和第二预掺杂后，可以进行退火工艺，例如RTA，以激活掺入的杂质。类似地，在某些实施例中，预掺杂区501、第一阱区511和第二阱区521每一个也可以包括对应鳍片202的至少一部分，也即与对应的鳍片交叠。
在又一个实施例中，如图5D所示，首先对衬底结构进行第一预掺杂，以形成延伸到鳍片中的预掺杂区501，这里的预掺杂区501包括衬底的一部分和对应的鳍片的一部分(参见图5B)或全部(参见图5D)。然后，对预掺杂区501的一部分进行第二预掺杂，在预掺杂区501中形成阱区521，预掺杂区501的其余部分作为阱区511，其中第一阱区511和第二阱区521具有不同的导电类型。例如，第一阱区511为N阱、第二阱区521为P阱，反之亦然。与上类似地，在进行第一预掺杂和第二预掺杂后，可以进行退火工艺，以激活掺入的杂质。
继续参见图1，在步骤107，去除隔离区的一部分以露出多个鳍片中各鳍片的至少一部分。
图6A-图6D示出了根据本公开不同实施例的去除隔离区的一部分后的示意截面图。如图6A-图6D(分别对应于图5A-图5D)所示，可以通过回刻蚀工艺去除隔离区402的一部分。这里，如果鳍片202的表面具有衬垫层，即隔离区301的两侧具有衬垫层，则在去除隔离区301的一部分时，还去除隔离区301的一部分的两侧的衬垫层，以露出多个鳍片中各鳍片的至少一部分。
继续参见图1，在步骤109，对多个鳍片中的与所述阱区邻接或者交叠的第一组鳍片的每一个鳍片的至少一部分进行第二掺杂，以形成第一掺杂区。在步骤111，对多个鳍片中的与第一组鳍片不同的第二组鳍片的每一个鳍片的至少一部分进行第三掺杂，以形成第二掺杂区；其中，第一掺杂区具有与第二掺杂区不同的导电类型。另外，如果鳍片上的硬掩模未被去除，则在进行第二掺杂和第三掺杂之前，可以先去除多个半导体鳍片上的硬掩模。替代地，在掺杂时也可以保留硬掩模以减少鳍片表面由于掺杂导致的损伤。可选地，在进行第二掺杂和第三掺杂之前，还可以在露出的鳍片的表面形成热氧化层。
下面结合图7A-图7C对不同实施例中形成第一掺杂区和第二掺杂区的过程进行介绍。上述的第二掺杂和第三掺杂可以通过离子注入的方式来进行。
如图7A所示，对多个鳍片中的第一组鳍片的每一个鳍片进行第二掺杂，以形成第一掺杂区202A；对多个鳍片中的与第一组鳍片不同的第二组鳍片的每一个鳍片进行第三掺杂，以形成第二掺杂区202B。这里，可以选择第二阱区521上的鳍片作为第一组鳍片，第一阱区511上的鳍片作为第二组鳍片。所形成的第一掺杂区202A与第二阱区521邻接，并具有与第二阱区521相同的导电类型；优选地，第一掺杂区202A的掺杂浓度大于第二阱区521的掺杂浓度。所形成的第二掺杂区202B与第一阱区511邻接，并具有与第一阱区511相同的导电类型；优选地，第二掺杂区202B的掺杂浓度大于第一阱区511的掺杂浓度。
如图7B所示，对多个鳍片中的第一组鳍片的每一个鳍片进行第二掺杂，以形成第一掺杂区202A；对多个鳍片中的与第一组鳍片不同的第二组鳍片的每一个鳍片进行第三掺杂，以形成第二掺杂区202B。这里，可以选择阱区521上的鳍片作为第一组鳍片，预掺杂区的其余部分511(该实施例中为衬底)上的鳍片作为第二组鳍片。所形成的第一掺杂区202A与阱区521邻接，并具有与阱区521相同的导电类型；优选地，第一掺杂区202A的掺杂浓度大于阱区521的掺杂浓度。所形成的第二掺杂区202B与预掺杂区的其余部分511邻接，并具有与预掺杂区的其余部分511相同的导电类型；优选地，第二掺杂区202B的掺杂浓度大于预掺杂区的其余部分511的掺杂浓度。
如图7C所示，该实施例中的阱区501包括衬底的一部分和每个鳍片的一部分或全部。第一阱区511包括衬底的一部分和第一组鳍片的每个鳍片的一部分或全部，第二阱区521包括衬底的一部分和第二组鳍片的一部分或全部。因此，当第一阱区511包括衬底的一部分和第一组鳍片的每个鳍片的全部时，所形成的第一掺杂区202A位于第一阱区511中；当第一阱区511包括衬底的一部分和第一组鳍片的每个鳍片的一部分时，所形成的第一掺杂区202A与第一阱区511邻接；并且第一掺杂区202A具有与第一阱区511相同的导电类型；优选地，第一掺杂区202A的掺杂浓度大于第一阱区511的掺杂浓度。类似地，当第一阱区521包括衬底的一部分和第二组鳍片的每个鳍片的全部时，所形成的第二掺杂区202B位于第二阱区521中；当第二阱区521包括衬底的一部分和第二组鳍片的每个鳍片的一部分时，所形成的第二掺杂区202B与第二阱区521邻接；并且第二掺杂区202B具有与第二阱区521相同的导电类型；优选地，第二掺杂区202B的掺杂浓度大于第二阱区521的掺杂浓度。
如上，提供了根据本公开一些实施例的半导体装置的制造方法。根据该方法，可以形成适于FinFET工艺的鳍片式二极管。特别地，由于在形成阱区(例如第一阱区和第二阱区)时，是在隔离材料的平坦化工艺之后进行的掺杂，因此可以使得形成的阱区中的杂质分布更加均匀。
下面参照图8A和图8B对本公开一个实施例的半导体装置的结构进行说明。如图8A所示，半导体装置包括：
衬底结构，该衬底结构半导体衬底801和位于衬底801上半导体鳍片802；
第一掺杂区803，至少部分地位于衬底801中；即，第一掺杂区803可以部分地位于衬底801中并与半导体鳍片交叠，也可以全部位于衬底801中；
第二掺杂区804，至少部分地位于衬底801中且在第一掺杂区803的一部分之上，第一掺杂区803与第二掺杂区804具有不同的导电类型，第一掺杂区803与第二掺杂区804邻接并形成结，结的界面位于衬底801中；
位于第一掺杂区803上的第一组半导体鳍片802A；位于第二掺杂区上的第二组半导体鳍片802B；其中，第一掺杂区803与第一组鳍片802A具有相同的导电类型，第二掺杂区804与第二组鳍片802B具有相同的导电类型。
图8A示出的第一掺杂区803与第二掺杂区804邻接的结的界面仅包括一个水平部分和一个竖直部分。而图8B示出的第一掺杂区803与第二掺杂区804邻接的结的界面还包括与竖直部分对应的另一个竖直部分，也即第二掺杂区804可以完全嵌入在第一掺杂区803中。由于半导体装置中的第一掺杂区和第二掺杂区邻接形成的结的界面位于衬底中，在半导体装置中作为鳍片式二极管时增大了ESD电流通过的面积，降低了二极管的导通电阻Ron。
优选地，半导体装置还可以包括：位于第一组半导体鳍片和第二组半导体鳍片中的各个鳍片之间的隔离区805，例如浅沟槽隔离(STI)区。
优选地，第一组半导体鳍片802A包括掺杂浓度大于第一掺杂区803的掺杂浓度的部分；第二组半导体鳍片802B包括掺杂浓度大于第二掺杂区804的掺杂浓度的部分。例如，整个第一组半导体鳍片802A的掺杂浓度大于第一掺杂区803的掺杂浓度，整个第二组半导体鳍片802B的掺杂浓度大于第二掺杂区804的掺杂浓度；或者第一组半导体鳍片802A的上半部的掺杂浓度大于第一掺杂区803的掺杂浓度，第二组半导体鳍片802B的上半部的掺杂浓度大于第二掺杂区804的掺杂浓度。
需要说明的是，上述第一掺杂区803和第二掺杂区804可以是两个导电类型不同的阱区，例如其中一个是N阱，另一个是P阱；或者第一掺杂区803为掺杂衬底，而第二掺杂区804是阱区，例如第一掺杂区803为P型衬底，而第二掺杂区804是N阱，或者第一掺杂区803为N型衬底，而第二掺杂区804是P阱。
至此，已经详细描述了根据本公开实施例的半导体装置(鳍片式二极管)及其制造方法。为了避免遮蔽本公开的构思，没有描述本领域所公知的一些细节，本领域技术人员根据上面的描述，完全可以明白如何实施这里公开的技术方案。另外，本说明书公开所教导的各实施例可以自由组合。本领域的技术人员应该理解，可以对上面说明的实施例进行多种修改而不脱离如所附权利要求限定的本公开的精神和范围。

Claims (12)

1.一种鳍片式二极管的制造方法，其特征在于，所述方法包括以下步骤：
提供衬底结构，所述衬底结构包括半导体衬底和位于所述衬底上的多个半导体鳍片；
在各个鳍片之间形成隔离区以填充满各个鳍片之间的空间，其中，所述隔离区的表面与各个鳍片的表面齐平；
在形成所述隔离区之后，对所述衬底结构的至少一部分进行第一掺杂，以形成阱区，所述阱区至少部分地在所述衬底中且与所述多个半导体鳍片中的一部分鳍片邻接或者交叠，进行所述第一掺杂包括：
对所述衬底结构进行第一预掺杂，以形成位于所述衬底中且与所述多个半导体鳍片中的一部分鳍片邻接或交叠的预掺杂区；
对所述预掺杂区的一部分进行第二预掺杂，以在所述预掺杂区中形成所述阱区，所述阱区位于所述预掺杂区的一部分之上，其中所述阱区和所述预掺杂区具有不同的导电类型；
去除所述隔离区的一部分以露出所述多个半导体鳍片中各鳍片的至少一部分；
对所述多个半导体鳍片中的与所述阱区邻接或者交叠的第一组鳍片的每一个鳍片的至少一部分进行第二掺杂，以形成第一掺杂区；以及
对所述多个半导体鳍片中的与所述第一组鳍片不同的第二组鳍片的每一个鳍片的至少一部分进行第三掺杂，以形成第二掺杂区；
其中，所述第一掺杂区具有与所述第二掺杂区不同的导电类型，所述第一掺杂区具有与所述阱区相同的导电类型。
2.根据权利要求1所述的方法，其特征在于，
所述阱区在所述衬底的一部分之上。
3.根据权利要求1所述的方法，其特征在于，
所述第一掺杂区与所述阱区邻接；
所述第二掺杂区与所述预掺杂区的其余部分邻接，并具有与所述其余部分相同的导电类型。
4.根据权利要求3所述的方法，其特征在于，
所述第一掺杂区的掺杂浓度大于所述阱区的掺杂浓度；
所述第二掺杂区的掺杂浓度大于所述预掺杂区的其余部分的掺杂浓度。
5.根据权利要求1所述的方法，其特征在于，所述阱区作为第二阱区，所述预掺杂区的其余部分作为第一阱区。
6.根据权利要求5所述的方法，其特征在于，
所述第一掺杂区与所述第二阱区邻接；
所述第二掺杂区与所述第一阱区邻接，并具有与所述第一阱区相同的导电类型。
7.根据权利要求1所述的方法，其特征在于，所述提供衬底结构的步骤包括：
提供初始衬底，所述初始衬底包括初始半导体层；
在所述初始半导体层上形成图案化的硬掩模；
以所述图案化的硬掩模为掩模对所述初始半导体层进行刻蚀，从而形成所述多个半导体鳍片。
8.根据权利要求1所述的方法，其特征在于，所述衬底结构还包括位于所述多个半导体鳍片上的硬掩模，
所述方法还包括：
去除所述多个半导体鳍片上的硬掩模。
9.根据权利要求8所述的方法，其特征在于，
所述硬掩模包括缓冲层和在所述缓冲层上的硬掩模层。
10.根据权利要求1所述的方法，其特征在于，所述在各个鳍片之间形成隔离区包括：
沉积隔离材料以填充各个鳍片之间的空间并覆盖所述鳍片；
对所述隔离材料进行平坦化，以使隔离材料的顶表面与所述鳍片的顶表面齐平，从而在各个鳍片之间形成所述隔离区。
11.根据权利要求10所述的方法，其特征在于，所述方法还包括：
在沉积隔离材料之前，在所述衬底和各个鳍片的表面形成衬垫层；
在去除所述隔离区的一部分时，还去除所述隔离区的所述一部分的两侧的衬垫层，以露出所述多个半导体鳍片中各鳍片的至少一部分。
12.根据权利要求1所述的方法，其特征在于，
所述第一掺杂区的掺杂浓度大于所述阱区的掺杂浓度。
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