KR910003825A - Mos fet의 제조방법 - Google Patents
Mos fet의 제조방법 Download PDFInfo
- Publication number
- KR910003825A KR910003825A KR1019900010408A KR900010408A KR910003825A KR 910003825 A KR910003825 A KR 910003825A KR 1019900010408 A KR1019900010408 A KR 1019900010408A KR 900010408 A KR900010408 A KR 900010408A KR 910003825 A KR910003825 A KR 910003825A
- Authority
- KR
- South Korea
- Prior art keywords
- insulating film
- forming
- nitride film
- manufacturing
- mos fet
- Prior art date
Links
- 238000004519 manufacturing process Methods 0.000 title claims 2
- 150000004767 nitrides Chemical class 0.000 claims 4
- 239000000758 substrate Substances 0.000 claims 3
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims 2
- 229920005591 polysilicon Polymers 0.000 claims 2
- 239000004065 semiconductor Substances 0.000 claims 2
- 239000011248 coating agent Substances 0.000 claims 1
- 238000000576 coating method Methods 0.000 claims 1
- 238000002955 isolation Methods 0.000 claims 1
- 230000003647 oxidation Effects 0.000 claims 1
- 238000007254 oxidation reaction Methods 0.000 claims 1
- 230000015572 biosynthetic process Effects 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
- H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Ceramic Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
Abstract
내용 없음.
Description
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제2도는 상기 실시예에 의해 제조된 MOS FET의 채널 긴쪽 방향의 단면도,
제3도는 상기 MOS FET의 채널 긴쪽 방향과 채널 폭 방향의 양단면을 포함하는 게이트 형성후의 사면도,
제4도는 상기 MOS FET의 배선전의 평면도.
Claims (1)
- (a) 기판상에 질화막을 형성하여 채널 형성면을 돌출시켜 블록부를 형성하는 공정과, (b) 상기 질화막과 상기 반도체 기판상의 블록부 표면 및 측면상부 이외의부분을 절연막으로 피복하는 공정과, (c) 이 절연막 미폭부의 상기 반도체 기판상의 볼록부 측면과 접합하도록 폴리실리콘을 형성하는 공정과, (d) 상기 폴리 실리콘을 열산화하여 소오스, 드레인 도전층상에 상기 볼록부 상부 질화막의 소오스, 드레인 도전층측 까지 절연막을 형성하고, 또한 소자분리를 행하는 공정과, (e)상기 질화막을 제거하여 채널면에 자기 정합적으로 게이트 절연막과 게이트 전극을 형성하는 공정으로 이루어진 MOS FET의 제조방법.※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP17717489 | 1989-07-11 | ||
| JP1-177174 | 1989-07-11 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| KR910003825A true KR910003825A (ko) | 1991-02-28 |
| KR960009991B1 KR960009991B1 (ko) | 1996-07-25 |
Family
ID=16026478
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| KR1019900010408A KR960009991B1 (ko) | 1989-07-11 | 1990-07-10 | Mos fet의 제조방법 |
Country Status (2)
| Country | Link |
|---|---|
| JP (1) | JPH03129742A (ko) |
| KR (1) | KR960009991B1 (ko) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100660337B1 (ko) * | 2005-12-28 | 2006-12-22 | 동부일렉트로닉스 주식회사 | 반도체 소자의 트랜지스터 형성방법 |
-
1990
- 1990-07-04 JP JP2176999A patent/JPH03129742A/ja active Pending
- 1990-07-10 KR KR1019900010408A patent/KR960009991B1/ko not_active IP Right Cessation
Also Published As
| Publication number | Publication date |
|---|---|
| JPH03129742A (ja) | 1991-06-03 |
| KR960009991B1 (ko) | 1996-07-25 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| A201 | Request for examination | ||
| E902 | Notification of reason for refusal | ||
| E902 | Notification of reason for refusal | ||
| G160 | Decision to publish patent application | ||
| E701 | Decision to grant or registration of patent right | ||
| GRNT | Written decision to grant | ||
| LAPS | Lapse due to unpaid annual fee |