KR910003825A - Manufacturing Method of MOS FET - Google Patents

Manufacturing Method of MOS FET Download PDF

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Publication number
KR910003825A
KR910003825A KR1019900010408A KR900010408A KR910003825A KR 910003825 A KR910003825 A KR 910003825A KR 1019900010408 A KR1019900010408 A KR 1019900010408A KR 900010408 A KR900010408 A KR 900010408A KR 910003825 A KR910003825 A KR 910003825A
Authority
KR
South Korea
Prior art keywords
insulating film
forming
nitride film
manufacturing
mos fet
Prior art date
Application number
KR1019900010408A
Other languages
Korean (ko)
Other versions
KR960009991B1 (en
Inventor
아스히데 우에노
Original Assignee
고스기 노부미쓰
오끼덴끼고오교 가부시끼가이샤
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 고스기 노부미쓰, 오끼덴끼고오교 가부시끼가이샤 filed Critical 고스기 노부미쓰
Publication of KR910003825A publication Critical patent/KR910003825A/en
Application granted granted Critical
Publication of KR960009991B1 publication Critical patent/KR960009991B1/en

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Ceramic Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)

Abstract

내용 없음.No content.

Description

MOS FET의 제조방법Manufacturing Method of MOS FET

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제2도는 상기 실시예에 의해 제조된 MOS FET의 채널 긴쪽 방향의 단면도,2 is a sectional view of a channel longitudinal direction of the MOS FET manufactured by the above embodiment,

제3도는 상기 MOS FET의 채널 긴쪽 방향과 채널 폭 방향의 양단면을 포함하는 게이트 형성후의 사면도,3 is a perspective view after gate formation including both end surfaces of a channel longitudinal direction and a channel width direction of the MOS FET;

제4도는 상기 MOS FET의 배선전의 평면도.4 is a plan view before wiring of the MOS FET.

Claims (1)

(a) 기판상에 질화막을 형성하여 채널 형성면을 돌출시켜 블록부를 형성하는 공정과, (b) 상기 질화막과 상기 반도체 기판상의 블록부 표면 및 측면상부 이외의부분을 절연막으로 피복하는 공정과, (c) 이 절연막 미폭부의 상기 반도체 기판상의 볼록부 측면과 접합하도록 폴리실리콘을 형성하는 공정과, (d) 상기 폴리 실리콘을 열산화하여 소오스, 드레인 도전층상에 상기 볼록부 상부 질화막의 소오스, 드레인 도전층측 까지 절연막을 형성하고, 또한 소자분리를 행하는 공정과, (e)상기 질화막을 제거하여 채널면에 자기 정합적으로 게이트 절연막과 게이트 전극을 형성하는 공정으로 이루어진 MOS FET의 제조방법.(a) forming a nitride film on the substrate to protrude a channel forming surface to form a block portion, (b) coating a portion other than the surface of the nitride film and the block portion on the semiconductor substrate and the upper surface portion with an insulating film; (c) forming polysilicon so as to be joined to the side surface of the convex portion on the semiconductor substrate of the insulating film unexpanded portion; (d) the source of the convex portion upper nitride film on the source and drain conductive layer by thermal oxidation of the polysilicon; A method of manufacturing an MOS FET comprising the steps of forming an insulating film up to the drain conductive layer side, and further performing element isolation, and (e) removing the nitride film to form a gate insulating film and a gate electrode in a self-aligned manner on the channel surface. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019900010408A 1989-07-11 1990-07-10 Field effect transistor manufacturing process KR960009991B1 (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP1-177174 1989-07-11
JP17717489 1989-07-11

Publications (2)

Publication Number Publication Date
KR910003825A true KR910003825A (en) 1991-02-28
KR960009991B1 KR960009991B1 (en) 1996-07-25

Family

ID=16026478

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019900010408A KR960009991B1 (en) 1989-07-11 1990-07-10 Field effect transistor manufacturing process

Country Status (2)

Country Link
JP (1) JPH03129742A (en)
KR (1) KR960009991B1 (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100660337B1 (en) * 2005-12-28 2006-12-22 동부일렉트로닉스 주식회사 Method for forming transistor of semiconductor device

Also Published As

Publication number Publication date
KR960009991B1 (en) 1996-07-25
JPH03129742A (en) 1991-06-03

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