KR910003504A - 디지탈 신호 처리 회로 - Google Patents
디지탈 신호 처리 회로 Download PDFInfo
- Publication number
- KR910003504A KR910003504A KR1019900011519A KR900011519A KR910003504A KR 910003504 A KR910003504 A KR 910003504A KR 1019900011519 A KR1019900011519 A KR 1019900011519A KR 900011519 A KR900011519 A KR 900011519A KR 910003504 A KR910003504 A KR 910003504A
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- KR
- South Korea
- Prior art keywords
- data
- bit
- input
- bits
- signal processing
- Prior art date
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Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
- G06F7/60—Methods or arrangements for performing computations using a digital non-denominational number representation, i.e. number representation without radix; Computing devices using combinations of denominational and non-denominational quantity representations, e.g. using difunction pulse trains, STEELE computers, phase computers
- G06F7/72—Methods or arrangements for performing computations using a digital non-denominational number representation, i.e. number representation without radix; Computing devices using combinations of denominational and non-denominational quantity representations, e.g. using difunction pulse trains, STEELE computers, phase computers using residue arithmetic
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
- G06F11/14—Error detection or correction of the data by redundancy in operation
- G06F11/1497—Details of time redundant execution on a single processing unit
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
- G06F11/08—Error detection or correction by redundancy in data representation, e.g. by using checking codes
- G06F11/10—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
- G06F11/1008—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices
- G06F11/1012—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices using codes or arrangements adapted for a specific type of error
- G06F11/104—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices using codes or arrangements adapted for a specific type of error using arithmetic codes, i.e. codes which are preserved during operation, e.g. modulo 9 or 11 check
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
- G06F7/60—Methods or arrangements for performing computations using a digital non-denominational number representation, i.e. number representation without radix; Computing devices using combinations of denominational and non-denominational quantity representations, e.g. using difunction pulse trains, STEELE computers, phase computers
- G06F7/72—Methods or arrangements for performing computations using a digital non-denominational number representation, i.e. number representation without radix; Computing devices using combinations of denominational and non-denominational quantity representations, e.g. using difunction pulse trains, STEELE computers, phase computers using residue arithmetic
- G06F7/729—Methods or arrangements for performing computations using a digital non-denominational number representation, i.e. number representation without radix; Computing devices using combinations of denominational and non-denominational quantity representations, e.g. using difunction pulse trains, STEELE computers, phase computers using residue arithmetic using representation by a residue number system
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M7/00—Conversion of a code where information is represented by a given sequence or number of digits to a code where the same, similar or subset of information is represented by a different sequence or number of digits
- H03M7/14—Conversion to or from non-weighted codes
- H03M7/18—Conversion to or from residue codes
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- Computational Mathematics (AREA)
- Mathematical Analysis (AREA)
- Mathematical Optimization (AREA)
- Pure & Applied Mathematics (AREA)
- Quality & Reliability (AREA)
- Mathematical Physics (AREA)
- Computing Systems (AREA)
- Analogue/Digital Conversion (AREA)
- Compression, Expansion, Code Conversion, And Decoders (AREA)
- Error Detection And Correction (AREA)
- Measurement And Recording Of Electrical Phenomena And Electrical Characteristics Of The Living Body (AREA)
Abstract
내용 없음.
Description
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제2도는 본 발명에 따른 디지탈 필터 장치의 구성을 도시한 블럭선도,
제3A 및 3B도는 제2도에서 도시된 디지탈 필터 장치에서 고장 진단 모드의 동작을 도시하는 파형선도,
제5도는 제2도에서 도시된 디지탈 필터 장치에서 디코더의 구성에 대한 실시예를 도시한 블럭선도.
Claims (5)
- 2진 코드로 구성된 입력 데이타를 처리하기 위한 디지탈 신호 처리 장치에서, RNS 계수들중 선택된 개수의 배수인 변환된 값으로 상기 입력 디지탈 데이타를 변환하는 변환수단, 상기 입력 디지탈 데이타 또는 상기 변환된 데이타중 하나 이상을 선택하는 선택 수단, 상기 선택 수단의 출력이 제공되며 상기 RNS 계수에 대한 잉여 데이타를 발생하도록 적합되어 있는RNS 엔코딩 수단, 및 처리된 데이타를 발생하기 위해 상기 잉여 데이타를 처리하는 처리 수단을 구비하여 이루어지는 디지탈 신호 처리 장치.
- 제1항에 있어서, 상기 처리 수단은 디지탈 필터 수단을 구비하는 디지탈 신호 처리 장치.
- 제1항에 있어서, 상기 입력 변환 수단은 m-비트 2진 코드 데이타 및 n-비트 제어 데이타가 진입되며 내부에 (m+n)비트 변환표 데이타가 기록되어 있는 ROM으로 구성되는 디지탈 신호 처리 장치.
- 제1항에 있어서, 상기 입력 변환 수단은 (m1+m2)비트 2진 코드 데이타중 상기 m1비트 데이타와 n비트 제어 데이타가 입력으로서 진입하며 내부에 (m1+n)비트 변환표가 기록되어 있는 ROM으로 구성되는 상위 비트 변환부와, 상기(m1+m2)비트 2진 코드 데이타의 하단 m2비트 데이타와 n비트 제어 데이타가 입력으로서 진입하며 내부에는 (m2+n)비트 변환표 데이타가 기록되어 있는 하단 비트 변환부를 구비하는 디지탈 신호 처리 장치.
- 디지탈 데이타의 MSB로부터 소정 수의 비트로 구성된 유효 데이타를 라운딩하는 데이타 처리 회로에서 소정 수의 비트로 구성된 멀티-엘리먼트 M순열 노이즈를 발생하는 노이즈 발생 수단, 상기 노이즈 발생 수단으로부터의 멀티-엘리먼트 M순열 노이즈를 상기 디지탈 데이타의 상기 소정 수의 비트 이하의 비트로 구성된 분수 데이타의 MSB로부터 소정 수의 비트에 가산하는 제1가산기 수단, 상기 제1가산기 수단의 출력으로부터 캐리 데이타를 발생하는 수단, 및 상기 캐리 데이타를 상기 유효 데이타의 LSB에 가산하는 제2가산기 수단을 구비하여 이루어지는 데이타 처리 회로.※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP1-197593 | 1989-07-29 | ||
JP1197593A JP2930325B2 (ja) | 1989-07-29 | 1989-07-29 | ディジタル信号処理回路 |
Publications (2)
Publication Number | Publication Date |
---|---|
KR910003504A true KR910003504A (ko) | 1991-02-27 |
KR100248448B1 KR100248448B1 (ko) | 2000-03-15 |
Family
ID=16377068
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
KR1019900011519A KR100248448B1 (ko) | 1989-07-29 | 1990-07-28 | 디지탈 신호 처리 회로 |
Country Status (5)
Country | Link |
---|---|
US (1) | US5117383A (ko) |
EP (1) | EP0411504B1 (ko) |
JP (1) | JP2930325B2 (ko) |
KR (1) | KR100248448B1 (ko) |
DE (1) | DE69032382T2 (ko) |
Families Citing this family (14)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5987487A (en) * | 1996-03-11 | 1999-11-16 | Cirrus Logic, Inc. | Methods and apparatus for the processing of digital signals |
US5892632A (en) * | 1996-11-18 | 1999-04-06 | Cirrus Logic, Inc. | Sampled amplitude read channel employing a residue number system FIR filter in an adaptive equalizer and in interpolated timing recovery |
US7523151B1 (en) | 2000-05-12 | 2009-04-21 | The Athena Group, Inc. | Method and apparatus for performing computations using residue arithmetic |
KR20020069591A (ko) * | 2001-02-26 | 2002-09-05 | 디브이테크놀로지 | 모듈로 머젠수 아날로그 디지트 병렬 승산기 및 그 기술의응용방법 |
JP2008282178A (ja) * | 2007-05-09 | 2008-11-20 | Toshiba Corp | 産業用コントローラ |
WO2013002727A1 (en) * | 2011-06-30 | 2013-01-03 | Nanyang Technological University | A system for rns based analoq-to-diqital conversion and inner product computation |
US9026506B2 (en) * | 2012-04-02 | 2015-05-05 | University Of North Texas | System and method for multi-residue multivariate data compression |
US9081608B2 (en) * | 2012-05-19 | 2015-07-14 | Digital System Research Inc. | Residue number arithmetic logic unit |
US9712185B2 (en) * | 2012-05-19 | 2017-07-18 | Olsen Ip Reserve, Llc | System and method for improved fractional binary to fractional residue converter and multipler |
US10296292B2 (en) * | 2016-10-20 | 2019-05-21 | Advanced Micro Devices, Inc. | Dynamic variable precision computation |
IT201700008949A1 (it) * | 2017-01-27 | 2018-07-27 | St Microelectronics Srl | Procedimento di funzionamento di reti neurali, rete, apparecchiatura e prodotto informatico corrispondenti |
US10387122B1 (en) | 2018-05-04 | 2019-08-20 | Olsen Ip Reserve, Llc | Residue number matrix multiplier |
US10992314B2 (en) | 2019-01-21 | 2021-04-27 | Olsen Ip Reserve, Llc | Residue number systems and methods for arithmetic error detection and correction |
CA3158143A1 (en) * | 2019-12-16 | 2021-06-24 | Mitsubishi Electric Corporation | Filter device |
Family Cites Families (15)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
GB1353213A (en) * | 1971-09-27 | 1974-05-15 | Rosemount Eng Co Ltd | Digital data processing equipment and to control systems using digital data processing |
US4041284A (en) * | 1976-09-07 | 1977-08-09 | The United States Of America As Represented By The Secretary Of The Navy | Signal processing devices using residue class arithmetic |
JPS56158525A (en) * | 1980-05-12 | 1981-12-07 | Nec Corp | Circulation type digital filter |
GB2077008B (en) * | 1980-05-21 | 1985-02-06 | Slechta Jiri | Mathematical convergency in digital computers |
US4589084A (en) * | 1983-05-16 | 1986-05-13 | Rca Corporation | Apparatus for symmetrically truncating two's complement binary signals as for use with interleaved quadrature signals |
SU1166116A1 (ru) * | 1984-01-13 | 1985-07-07 | Институт математики и механики АН КазССР | Устройство дл обнаружени ошибок в слабоарифметическом коде системы остаточных классов |
EP0166563A3 (en) * | 1984-06-21 | 1987-07-15 | Texas Instruments Incorporated | Residue number system universal digital filter |
US4598266A (en) * | 1984-09-24 | 1986-07-01 | Gte Communications Systems Corporation | Modulo adder |
US4831576A (en) * | 1986-05-06 | 1989-05-16 | Yamaha Corporation | Multiplier circuit |
US4949293A (en) * | 1987-09-25 | 1990-08-14 | Kabushiki Kaisha Toshiba | Method and apparatus for computing residue with respect to arbitrary modulus |
JPH0199325A (ja) * | 1987-10-12 | 1989-04-18 | Sony Corp | エンコーダ回路 |
JP2699358B2 (ja) * | 1987-11-12 | 1998-01-19 | ソニー株式会社 | デコーダ回路 |
FR2622713A1 (fr) * | 1987-10-30 | 1989-05-05 | Thomson Csf | Circuit de calcul utilisant une arithmetique residuelle |
JPH01120111A (ja) * | 1987-11-02 | 1989-05-12 | Yokogawa Electric Corp | ディジタルフィルタ |
US4910699A (en) * | 1988-08-18 | 1990-03-20 | The Boeing Company | Optical computer including parallel residue to binary conversion |
-
1989
- 1989-07-29 JP JP1197593A patent/JP2930325B2/ja not_active Expired - Fee Related
-
1990
- 1990-07-24 US US07/556,430 patent/US5117383A/en not_active Expired - Lifetime
- 1990-07-27 EP EP90114488A patent/EP0411504B1/en not_active Expired - Lifetime
- 1990-07-27 DE DE69032382T patent/DE69032382T2/de not_active Expired - Fee Related
- 1990-07-28 KR KR1019900011519A patent/KR100248448B1/ko not_active IP Right Cessation
Also Published As
Publication number | Publication date |
---|---|
EP0411504A2 (en) | 1991-02-06 |
DE69032382T2 (de) | 1998-10-08 |
EP0411504B1 (en) | 1998-06-10 |
KR100248448B1 (ko) | 2000-03-15 |
DE69032382D1 (de) | 1998-07-16 |
US5117383A (en) | 1992-05-26 |
JPH0360509A (ja) | 1991-03-15 |
JP2930325B2 (ja) | 1999-08-03 |
EP0411504A3 (en) | 1993-02-03 |
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