KR890012380A - 전자 소자 패키지 및 제조방법 - Google Patents

전자 소자 패키지 및 제조방법 Download PDF

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Publication number
KR890012380A
KR890012380A KR1019880017869A KR880017869A KR890012380A KR 890012380 A KR890012380 A KR 890012380A KR 1019880017869 A KR1019880017869 A KR 1019880017869A KR 880017869 A KR880017869 A KR 880017869A KR 890012380 A KR890012380 A KR 890012380A
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KR
South Korea
Prior art keywords
lead
base end
electronic device
distal end
leads
Prior art date
Application number
KR1019880017869A
Other languages
English (en)
Other versions
KR970006531B1 (ko
Inventor
티.린 폴
비.맥새인 마이클
지.비글러 챨즈
에이.고쯔 죤
Original Assignee
빈센스 죠셉 로너
모토로라 인코포레이티드
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 빈센스 죠셉 로너, 모토로라 인코포레이티드 filed Critical 빈센스 죠셉 로너
Publication of KR890012380A publication Critical patent/KR890012380A/ko
Application granted granted Critical
Publication of KR970006531B1 publication Critical patent/KR970006531B1/ko

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/50—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor for integrated circuit devices, e.g. power bus, number of leads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L21/6835—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/68—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for positioning, orientation or alignment
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T29/00—Metal working
    • Y10T29/49—Method of mechanical manufacture
    • Y10T29/49002—Electrical device making
    • Y10T29/49004—Electrical device making including measuring or testing of device or component part
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T29/00—Metal working
    • Y10T29/49—Method of mechanical manufacture
    • Y10T29/49002—Electrical device making
    • Y10T29/49117—Conductor or circuit manufacturing
    • Y10T29/49121—Beam lead frame or beam lead device
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T29/00—Metal working
    • Y10T29/49—Method of mechanical manufacture
    • Y10T29/49002—Electrical device making
    • Y10T29/49117—Conductor or circuit manufacturing
    • Y10T29/49169—Assembling electrical component directly to terminal or elongated conductor
    • Y10T29/49171—Assembling electrical component directly to terminal or elongated conductor with encapsulating
    • Y10T29/49172—Assembling electrical component directly to terminal or elongated conductor with encapsulating by molding of insulating material

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Lead Frames For Integrated Circuits (AREA)
  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)

Abstract

내용 없음.

Description

전자 소자 패키지 및 제조방법
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제2도는 본 발명의 한 형태로 이용될 수 있는 몰드의 간단한 투시도.
제3도는 제2도의 몰드를 이용하여 만든 본 발명의 전자 소자 패키지 실시예의 3/4 사시도.
제4도는 본 발명의 패키지에 대한 다른 변형의 캐리어 구조와 조화된 리드 프레임의 말단부에 대한 단면도.

Claims (2)

  1. 캐리어 구조를 가진 전자 소자 패키지에 있어서, 전자 소자 결합 영역 주변에서 결합 영역 근처의 기부 단부, 결합 영역에서 떨어진 말단부 및 기부 단부와 말단부 사이의 중간 부분을 가진 각 리드로 다수의 리드를 구비하는 리드 프레임과, 리드 프레임에서 리드이 기부 단부에 결합된 전자 소자와, 각각의 리드에 대해 기부 단부의 적어도 일부분 및 전자 소자에 걸쳐 제1재료로 구성된 패키지 본체와, 적어도 몇몇의 리드에 대해 말단부의 적어도 일부분에 걸쳐 제2재료가 제1재료와 다른 재료로 구성된 캐리어 구조를 구비하며, 리드에 대한 중간 부분의 적어도 일부분이 어떤 재료로 덮여지지 않고 노출되어 있는 것을 특징으로 하는 캐리어 구조를 가진 전자 소자 패키지.
  2. 키리어 구조를 가진 전자 소자 패키지를 제조하는 방법에 있어서, 전자 소자 결함 영역 주변에서 결합 영역 근처의 기부 단부, 결합영역에서 떨어진 말단부 및 기부 단부와 말단부 사이의 중간 부분을 가진 각 리드로 다수의 리드를 구비하는 리드 프레임을 제공하는 단계와, 리드 프레임에서 리드의 기부 단부에 결합된 전자 소자 결합하는 단계와, 각각의 리드에 대해 기부 단부의 적어도 일부분 및 전자 소자에 걸쳐 제1재료로 구성된 패키지 본체를 제공하는 단계와, 적어도 몇몇의 리드에 대해 말단부의 적어도 일부분에 걸쳐 제2재료가 제1재료와 다른 재료로 구성된 캐리어 구조를 제공하는 단계를 구비하며, 리드에 대한 중간 부분의 적어도 일부분이 어떤 재료로 덮여지지 않고 노출되어 있는 것을 특징으로 하는 캐리어 구조를 가진 전자 소자 패키지 제조방법.
    ※참고사항 : 최초출원 내용에 의하여 공개하는 것임.
KR1019880017869A 1988-01-04 1988-12-30 전자 소자 패키지 및 제조방법 KR970006531B1 (ko)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US07/141,013 US4837184A (en) 1988-01-04 1988-01-04 Process of making an electronic device package with peripheral carrier structure of low-cost plastic
US141,013 1988-01-04

Publications (2)

Publication Number Publication Date
KR890012380A true KR890012380A (ko) 1989-08-26
KR970006531B1 KR970006531B1 (ko) 1997-04-29

Family

ID=22493764

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019880017869A KR970006531B1 (ko) 1988-01-04 1988-12-30 전자 소자 패키지 및 제조방법

Country Status (7)

Country Link
US (1) US4837184A (ko)
JP (1) JP2553924B2 (ko)
KR (1) KR970006531B1 (ko)
GB (1) GB2213640B (ko)
HK (1) HK87795A (ko)
MY (1) MY103475A (ko)
SG (1) SG30558G (ko)

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Also Published As

Publication number Publication date
US4837184A (en) 1989-06-06
SG30558G (en) 1995-09-18
HK87795A (en) 1995-06-09
JP2553924B2 (ja) 1996-11-13
GB2213640B (en) 1992-03-18
KR970006531B1 (ko) 1997-04-29
GB8829795D0 (en) 1989-02-15
MY103475A (en) 1993-06-30
GB2213640A (en) 1989-08-16
JPH01206658A (ja) 1989-08-18

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