KR890005895A - 2중확산형 mosfet - Google Patents
2중확산형 mosfet Download PDFInfo
- Publication number
- KR890005895A KR890005895A KR1019880012751A KR880012751A KR890005895A KR 890005895 A KR890005895 A KR 890005895A KR 1019880012751 A KR1019880012751 A KR 1019880012751A KR 880012751 A KR880012751 A KR 880012751A KR 890005895 A KR890005895 A KR 890005895A
- Authority
- KR
- South Korea
- Prior art keywords
- semiconductor regions
- semiconductor
- regions
- outer periphery
- insulating layer
- Prior art date
Links
- 238000009792 diffusion process Methods 0.000 title claims 3
- 239000004065 semiconductor Substances 0.000 claims description 22
- 239000000758 substrate Substances 0.000 claims description 3
- 239000012535 impurity Substances 0.000 claims 2
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims 1
- 239000010410 layer Substances 0.000 description 4
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- 239000011229 interlayer Substances 0.000 description 1
- 230000003071 parasitic effect Effects 0.000 description 1
- 230000001681 protective effect Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
- H01L29/0692—Surface layout
- H01L29/0696—Surface layout of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42372—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out
- H01L29/4238—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out characterised by the surface lay-out
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
- Semiconductor Integrated Circuits (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
Abstract
내용 없음
Description
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제4도는 제1도의 패턴평면도의 일부를 나타낸 평면도.
제5도는 본 발명의 1실시예에 따른 MOSFET의 패턴 평면도.
제6도는 제5도의 B-B'선에 따른 단면도.
* 도면의 주요부분에 대한 부호의 설명
10 : N형 실리콘기판 11, 21 : N형 에피텍셜층
12, 23 : P형 저저항영역 13, 24 : 챈널부 베이스영역
14, 25 : N형 소오스영역 15, 27 : 게이트절연층
16, 28 : 게이트전극 17, 29 : 개구부
18, 31 : 소오스전극 19, 33 : 드레인전극
Q : 트랜지스터 Rb : 기생저항
20 : N형 실리콘반도체층, 반도체형 기판 26 : 표면영역
30 : 층간절연층 32 : 표면보호막
Claims (3)
- 병행하는 제1 및 제2평면(21,20)을 갖추고 제1도전형 불순물이 도우프된 반도체기체(22)와, 이 반도체기체(22)의 제1평면(21)에 그물형상으로 분산되어 형성되면서 바깥둘레와 4군데 모서리부분이 둥글게 형성된 거의 정방형의 형상을 갖는 복수의 제2도전형 제1반도체영역(23), 상기 복수의 각 제1반도체영역(23)을 에워싸도록 형성되면서 각각의 깊이가 각 제1반도체영역(23)의 깊이보다도 얕게 되어 있으며 각각의 바깥둘레가 상기 각 제1반도체영역(23)과 대응되는 형상을 갖추고 각각의 바깥둘레로부터 상기 각 제1반도체영역(23)의 바깥둘레까지의 평면거리가 각 제1반도체영역(23)의 전체 주위에서 균일하도록 설정되어 있는 복수의 제2도전형 제2반도체영역 (24), 상기 제1평면(21)상에 형성된 복수의 각 제1 및 제2반도체영역(23,24)의 각각에 형성되어 있고 각각의 깊이가 각 제1 및 제2반도체영역(23,24)의 깊이보다도 얕으며 또한 그 바깥둘레가 각 제2반도체영역(24)의 바깥둘레로부터 일정거리 만큼 안쪽에 존재하고 있는 복수의 제1도전형 소오스영역(25), 상기 복수의 각 소오스영역(25)의 바깥둘레와 각 제2반도체영역(24)의 바깥둘레간에 규정되고 상기 각 제2반도체영역 (24)으로 이루어지는 복수의 챈널영역(26), 상기 각 제1 및 제2반도체영역(23,24)을 에워싸고 또한 상기 복수의 챈널영역(26)상을 덮도록 상기 각 제1 및 제2반도체영역(23,24)간에 그물형상으로 확장되어 형성된 게이트절연층(27), 상기 게이트절연층(27)상에 퇴적되는 그물형상의 게이트전극(28), 상기 복수의 각 제1도전형의 소오스영역(25)과 각 제1반도체영역(23)에 접속되도록 상기 제1평면(21)상에 형성된 공통소오스전극(31) 및, 상기 반도체기체(22)의 제2평면(20)에 접속되는 드레인전극(33)을 구비하여 이루어진 2중확산형 MOSFET.
- 제1항에 있어서, 상기 복수의 각 제1반도체영역(23)의 불순물농도가 상기 복수의 각 제2반도체영역(24)의 불순물 농도보다도 높게 되어 있는 것을 특징으로 하는 2중확산형 MOSFET.
- 제1항에 있어서, 게이트절연층(27)이 산화물로 이루어지고, 상기 게이트전극 (28)이 다결정실릴콘으로 이루어진 것을 특징으로 하는 2중확산형 MOSFET.※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP62-246013 | 1987-09-30 | ||
JP62246013A JPS6489465A (en) | 1987-09-30 | 1987-09-30 | Double-diffusion type mos field effect transistor |
Publications (2)
Publication Number | Publication Date |
---|---|
KR890005895A true KR890005895A (ko) | 1989-05-17 |
KR910008714B1 KR910008714B1 (ko) | 1991-10-19 |
Family
ID=17142161
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
KR1019880012751A KR910008714B1 (ko) | 1987-09-30 | 1988-09-30 | 2중확산형 mosfet |
Country Status (3)
Country | Link |
---|---|
EP (1) | EP0310047A3 (ko) |
JP (1) | JPS6489465A (ko) |
KR (1) | KR910008714B1 (ko) |
Families Citing this family (12)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP0492991B1 (en) * | 1990-12-21 | 1999-06-23 | SILICONIX Incorporated | Method of fabricating double diffused integrated MOSFET cells |
US5404040A (en) * | 1990-12-21 | 1995-04-04 | Siliconix Incorporated | Structure and fabrication of power MOSFETs, including termination structures |
JP3240896B2 (ja) * | 1995-11-21 | 2001-12-25 | 富士電機株式会社 | Mos型半導体素子 |
DE19832327A1 (de) | 1997-07-31 | 1999-02-04 | Siemens Ag | Halbleiterstruktur auf Basis von Silizium-Carbid-Material mit mehreren elektrisch unterschiedlichen Teilgebieten |
US9484451B2 (en) | 2007-10-05 | 2016-11-01 | Vishay-Siliconix | MOSFET active area and edge termination area charge balance |
JP5687128B2 (ja) * | 2011-05-06 | 2015-03-18 | 三菱電機株式会社 | 半導体装置およびその製造方法 |
US9431249B2 (en) | 2011-12-01 | 2016-08-30 | Vishay-Siliconix | Edge termination for super junction MOSFET devices |
US9614043B2 (en) | 2012-02-09 | 2017-04-04 | Vishay-Siliconix | MOSFET termination trench |
US9842911B2 (en) | 2012-05-30 | 2017-12-12 | Vishay-Siliconix | Adaptive charge balanced edge termination |
US9508596B2 (en) | 2014-06-20 | 2016-11-29 | Vishay-Siliconix | Processes used in fabricating a metal-insulator-semiconductor field effect transistor |
US9887259B2 (en) | 2014-06-23 | 2018-02-06 | Vishay-Siliconix | Modulated super junction power MOSFET devices |
EP3183754A4 (en) | 2014-08-19 | 2018-05-02 | Vishay-Siliconix | Super-junction metal oxide semiconductor field effect transistor |
Family Cites Families (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4639762A (en) * | 1984-04-30 | 1987-01-27 | Rca Corporation | MOSFET with reduced bipolar effects |
JPS6180859A (ja) * | 1984-09-28 | 1986-04-24 | Hitachi Ltd | パワ−mosfet |
-
1987
- 1987-09-30 JP JP62246013A patent/JPS6489465A/ja active Pending
-
1988
- 1988-09-28 EP EP88116031A patent/EP0310047A3/en not_active Withdrawn
- 1988-09-30 KR KR1019880012751A patent/KR910008714B1/ko not_active IP Right Cessation
Also Published As
Publication number | Publication date |
---|---|
JPS6489465A (en) | 1989-04-03 |
KR910008714B1 (ko) | 1991-10-19 |
EP0310047A3 (en) | 1990-01-31 |
EP0310047A2 (en) | 1989-04-05 |
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