KR850005009A - 엣칭 방법 - Google Patents

엣칭 방법 Download PDF

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Publication number
KR850005009A
KR850005009A KR1019840007505A KR840007505A KR850005009A KR 850005009 A KR850005009 A KR 850005009A KR 1019840007505 A KR1019840007505 A KR 1019840007505A KR 840007505 A KR840007505 A KR 840007505A KR 850005009 A KR850005009 A KR 850005009A
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South Korea
Prior art keywords
etching method
etching
solid material
ions
injected
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KR1019840007505A
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English (en)
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히테오 스나미
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미쓰다 가쓰시게
가부시기 가이샤 히다찌 세이사꾸쇼
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Publication of KR850005009A publication Critical patent/KR850005009A/ko

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    • CCHEMISTRY; METALLURGY
    • C23COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23FNON-MECHANICAL REMOVAL OF METALLIC MATERIAL FROM SURFACE; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL; MULTI-STEP PROCESSES FOR SURFACE TREATMENT OF METALLIC MATERIAL INVOLVING AT LEAST ONE PROCESS PROVIDED FOR IN CLASS C23 AND AT LEAST ONE PROCESS COVERED BY SUBCLASS C21D OR C22F OR CLASS C25
    • C23F1/00Etching metallic material by chemical means
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    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
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    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26Bombardment with radiation
    • H01L21/263Bombardment with radiation with high-energy radiation
    • H01L21/265Bombardment with radiation with high-energy radiation producing ion implantation
    • H01L21/26506Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors
    • H01L21/26513Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors of electrically active species
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    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/30604Chemical etching
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    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/3065Plasma etching; Reactive-ion etching
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    • H01L21/30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
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    • H01L21/3105After-treatment
    • H01L21/311Etching the insulating layers by chemical or physical means
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    • H01L21/30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
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    • H01L21/30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321After treatment
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    • H01L21/30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
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    • H01L21/32136Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only using plasmas
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    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
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    • H01L21/30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
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    • H01L21/768Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Power Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Chemical & Material Sciences (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • General Chemical & Material Sciences (AREA)
  • High Energy & Nuclear Physics (AREA)
  • Plasma & Fusion (AREA)
  • Health & Medical Sciences (AREA)
  • Toxicology (AREA)
  • Inorganic Chemistry (AREA)
  • Materials Engineering (AREA)
  • Mechanical Engineering (AREA)
  • Metallurgy (AREA)
  • Organic Chemistry (AREA)
  • Drying Of Semiconductors (AREA)
  • Weting (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • ing And Chemical Polishing (AREA)

Abstract

내용 없음

Description

엣칭 방법
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제1도는 본 발명의 실시예 1에 기재하는 방법에 의한 1예의 단면도,
제2도는 엣칭 특성을 도시한 도면,
제3도는 실시예 1의 방법에 의한 엣칭 구멍의 단면의 1예를 도시한 도면.

Claims (3)

  1. 접속한 이온 빔에 의해 1종 혹은 2종 이상의 이온을 고체 재료에 주입하고, 그 후 주입 이온과 그 농도에 의해서 엣칭 속도가 틀리는 차리법으로 해당 고체재료를 가공하는 엣칭방법.
  2. 상기 엣칭 방법에 있어서, 상기 차리법은 까스를 사용하는 드라이 엣칭법을 특징으로 하는 특허청구의 범위 제1항 기재의 엣칭법.
  3. 상기 엣칭 방법에 있어서, 상기 차리법은 용액을 사용한 습식 엣칭법을 특징으로 하는 특허청구의 범위 제1항 기재의 엣칭법.
    ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.
KR1019840007505A 1983-12-16 1984-11-29 엣칭 방법 KR850005009A (ko)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP58-236167 1983-12-16
JP58236167A JPS60128622A (ja) 1983-12-16 1983-12-16 エツチング法

Publications (1)

Publication Number Publication Date
KR850005009A true KR850005009A (ko) 1985-08-19

Family

ID=16996758

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019840007505A KR850005009A (ko) 1983-12-16 1984-11-29 엣칭 방법

Country Status (3)

Country Link
EP (1) EP0148448A3 (ko)
JP (1) JPS60128622A (ko)
KR (1) KR850005009A (ko)

Families Citing this family (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61135151A (ja) * 1984-12-05 1986-06-23 Mitsubishi Electric Corp 半導体記憶装置
US4748103A (en) * 1986-03-21 1988-05-31 Advanced Power Technology Mask-surrogate semiconductor process employing dopant protective region
JP2810444B2 (ja) * 1988-10-02 1998-10-15 キヤノン株式会社 結晶材料の微細加工方法
US5106764A (en) * 1989-04-10 1992-04-21 At&T Bell Laboratories Device fabrication
US5026437A (en) * 1990-01-22 1991-06-25 Tencor Instruments Cantilevered microtip manufacturing by ion implantation and etching
JP3333560B2 (ja) * 1992-10-23 2002-10-15 リコーエレメックス株式会社 シリコン基板のエッチング方法
US6309975B1 (en) 1997-03-14 2001-10-30 Micron Technology, Inc. Methods of making implanted structures
DE19837395C2 (de) 1998-08-18 2001-07-19 Infineon Technologies Ag Verfahren zur Herstellung eines eine strukturierte Isolationsschicht enthaltenden Halbleiterbauelements
WO2001032554A2 (en) * 1999-11-02 2001-05-10 Standard Mems, Inc. Microscopic scale forming method by selective etching of a doped substrate
DE10329389B4 (de) * 2003-06-30 2006-05-04 Advanced Micro Devices, Inc., Sunnyvale Verfahren zur Kompensierung von Ätzratenungleichförmigkeiten mittels Ionenimplantation
JP2006239787A (ja) * 2005-03-01 2006-09-14 National Institute Of Advanced Industrial & Technology 微細構造作製方法及び装置
WO2007082745A1 (en) * 2006-01-18 2007-07-26 Universite Catholique De Louvain Selective etching for semiconductor devices
EP2144117A1 (en) * 2008-07-11 2010-01-13 The Provost, Fellows and Scholars of the College of the Holy and Undivided Trinity of Queen Elizabeth near Dublin Process and system for fabrication of patterns on a surface
JP6281420B2 (ja) * 2014-06-10 2018-02-21 富士通セミコンダクター株式会社 半導体装置の製造方法
US20160380067A1 (en) 2015-06-23 2016-12-29 Globalfoundries Inc. Shaped terminals for a bipolar junction transistor

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE2554638A1 (de) * 1975-12-04 1977-06-16 Siemens Ag Verfahren zur erzeugung definierter boeschungswinkel bei einer aetzkante
US4377437A (en) * 1981-05-22 1983-03-22 Bell Telephone Laboratories, Incorporated Device lithography by selective ion implantation

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Publication number Publication date
JPS60128622A (ja) 1985-07-09
EP0148448A2 (en) 1985-07-17
EP0148448A3 (en) 1987-08-12

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