US20160380067A1 - Shaped terminals for a bipolar junction transistor - Google Patents
Shaped terminals for a bipolar junction transistor Download PDFInfo
- Publication number
- US20160380067A1 US20160380067A1 US14/747,385 US201514747385A US2016380067A1 US 20160380067 A1 US20160380067 A1 US 20160380067A1 US 201514747385 A US201514747385 A US 201514747385A US 2016380067 A1 US2016380067 A1 US 2016380067A1
- Authority
- US
- United States
- Prior art keywords
- emitter
- layer
- concentration
- base layer
- device structure
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Abandoned
Links
- 238000000034 method Methods 0.000 claims abstract description 28
- 238000004519 manufacturing process Methods 0.000 claims abstract description 11
- 229910052732 germanium Inorganic materials 0.000 claims description 51
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical group [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 claims description 51
- 239000000758 substrate Substances 0.000 claims description 30
- 230000007423 decrease Effects 0.000 claims description 13
- 229910000577 Silicon-germanium Inorganic materials 0.000 claims description 9
- 238000005530 etching Methods 0.000 claims description 8
- LEVVHYCKPQWKOP-UHFFFAOYSA-N [Si].[Ge] Chemical compound [Si].[Ge] LEVVHYCKPQWKOP-UHFFFAOYSA-N 0.000 claims description 7
- 239000000463 material Substances 0.000 description 33
- 239000004065 semiconductor Substances 0.000 description 30
- 239000013078 crystal Substances 0.000 description 11
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 10
- 239000002019 doping agent Substances 0.000 description 10
- 239000000203 mixture Substances 0.000 description 7
- 230000001419 dependent effect Effects 0.000 description 6
- 239000003989 dielectric material Substances 0.000 description 5
- 238000003672 processing method Methods 0.000 description 5
- 239000000377 silicon dioxide Substances 0.000 description 5
- 229910052581 Si3N4 Inorganic materials 0.000 description 4
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 4
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 4
- 229910052710 silicon Inorganic materials 0.000 description 4
- 239000010703 silicon Substances 0.000 description 4
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 4
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 description 3
- KWYUFKZDYYNOTN-UHFFFAOYSA-M Potassium hydroxide Chemical compound [OH-].[K+] KWYUFKZDYYNOTN-UHFFFAOYSA-M 0.000 description 3
- 229910052799 carbon Inorganic materials 0.000 description 3
- 238000002955 isolation Methods 0.000 description 3
- 230000000737 periodic effect Effects 0.000 description 3
- 238000001020 plasma etching Methods 0.000 description 3
- 235000012239 silicon dioxide Nutrition 0.000 description 3
- 125000006850 spacer group Chemical group 0.000 description 3
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 2
- 229910052796 boron Inorganic materials 0.000 description 2
- 239000005380 borophosphosilicate glass Substances 0.000 description 2
- 239000007795 chemical reaction product Substances 0.000 description 2
- 239000000470 constituent Substances 0.000 description 2
- 238000001312 dry etching Methods 0.000 description 2
- 238000002513 implantation Methods 0.000 description 2
- 238000005468 ion implantation Methods 0.000 description 2
- 239000000615 nonconductor Substances 0.000 description 2
- 230000002093 peripheral effect Effects 0.000 description 2
- 239000000047 product Substances 0.000 description 2
- 238000000927 vapour-phase epitaxy Methods 0.000 description 2
- VHUUQVKOLVNVRT-UHFFFAOYSA-N Ammonium hydroxide Chemical compound [NH4+].[OH-] VHUUQVKOLVNVRT-UHFFFAOYSA-N 0.000 description 1
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 1
- 229910045601 alloy Inorganic materials 0.000 description 1
- 239000000956 alloy Substances 0.000 description 1
- 229910052787 antimony Inorganic materials 0.000 description 1
- WATWJIUSRGPENY-UHFFFAOYSA-N antimony atom Chemical compound [Sb] WATWJIUSRGPENY-UHFFFAOYSA-N 0.000 description 1
- 229910052785 arsenic Inorganic materials 0.000 description 1
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 description 1
- 239000000919 ceramic Substances 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 239000013067 intermediate product Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 210000003739 neck Anatomy 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 229910052698 phosphorus Inorganic materials 0.000 description 1
- 239000011574 phosphorus Substances 0.000 description 1
- 229910021332 silicide Inorganic materials 0.000 description 1
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 230000007704 transition Effects 0.000 description 1
- 238000003631 wet chemical etching Methods 0.000 description 1
- 238000001039 wet etching Methods 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42304—Base electrodes for bipolar transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/0821—Collector regions of bipolar transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
- H01L21/30604—Chemical etching
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
- H01L21/30604—Chemical etching
- H01L21/30608—Anisotropic liquid etching
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0642—Isolation within the component, i.e. internal isolation
- H01L29/0649—Dielectric regions, e.g. SiO2 regions, air gaps
- H01L29/0653—Dielectric regions, e.g. SiO2 regions, air gaps adjoining the input or output region of a field-effect device, e.g. the source or drain region
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/0804—Emitter regions of bipolar transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/1004—Base region of bipolar transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66234—Bipolar junction transistors [BJT]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66234—Bipolar junction transistors [BJT]
- H01L29/66242—Heterojunction transistors [HBT]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/70—Bipolar devices
- H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
- H01L29/73—Bipolar junction transistors
- H01L29/732—Vertical transistors
- H01L29/7325—Vertical transistors having an emitter-base junction leaving at a main surface and a base-collector junction leaving at a peripheral surface of the body, e.g. mesa planar transistor
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/70—Bipolar devices
- H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
- H01L29/73—Bipolar junction transistors
- H01L29/737—Hetero-junction transistors
- H01L29/7371—Vertical transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66234—Bipolar junction transistors [BJT]
- H01L29/66272—Silicon vertical transistors
Definitions
- the invention relates generally to semiconductor devices and integrated circuit fabrication and, in particular, to fabrication methods and device structures for a bipolar junction transistor.
- Bipolar junction transistors may be found, among other end uses, in high-frequency and high-power applications.
- bipolar junction transistors may find specific end uses in amplifiers for wireless communications systems and mobile devices, switches, and oscillators.
- Bipolar junction transistors may also be used in high-speed logic circuits.
- Bipolar junction transistors are three-terminal electronic devices that include an emitter, an intrinsic base, and a collector defined by regions of different semiconductor materials. In the device structure, the intrinsic base situated between the emitter and collector.
- An NPN bipolar junction transistor may include n-type semiconductor material regions constituting the emitter and collector, and a region of p-type semiconductor material constituting the intrinsic base.
- a PNP bipolar junction transistor includes p-type semiconductor material regions constituting the emitter and collector, and a region of n-type semiconductor material constituting the intrinsic base. In operation, the base-emitter junction is forward biased and the base-collector junction is reverse biased. The collector-emitter current may be controlled by the base-emitter voltage.
- a method for fabricating a device structure.
- An emitter layer is formed on a base layer and etched to form an emitter of the device structure.
- the emitter layer has a concentration of an element that varies as a function of the thickness of the emitter layer.
- the etch rate of the emitter layer varies as a function of the concentration of the element such that the emitter has a variable width over the thickness of the emitter layer.
- a device structure for a bipolar junction transistor.
- the device structure includes a base layer and an emitter on the base layer,.
- the emitter has a height and a concentration of an element that varies as a function of the height.
- the emitter has a width that varies as a function of the height in relation to the concentration of the element.
- FIG. 1 is a cross-sectional view of a portion of a substrate at an initial fabrication stage of a processing method for fabricating a device structure in accordance with an embodiment of the invention.
- FIG. 2 is a cross-sectional view of the substrate portion of FIG. 1 at a subsequent fabrication stage of the processing method.
- FIG. 3A is a diagrammatic view of a germanium concentration profile in the base layer and the emitter layer.
- FIG. 3B is an enlarged view of a portion of FIG. 2 .
- FIG. 4 is a cross-sectional view of the substrate portion of FIG. 2 at a subsequent fabrication stage of the processing method.
- FIG. 5A is a diagrammatic view similar to FIG. 3A showing a germanium concentration profile in the base layer and the emitter layer in accordance with an alternative embodiment of the invention.
- FIG. 5B is an enlarged view similar to FIG. 3B of an emitter in accordance with an alternative embodiment of the invention in which the emitter is formed using the emitter layer with the germanium concentration profile of FIG. 5A .
- FIG. 6A is a diagrammatic view similar to FIG. 3A showing a germanium concentration profile in the base layer and the emitter layer in accordance with an alternative embodiment of the invention.
- FIG. 6B is an enlarged view similar to FIG. 3B of an emitter in accordance with an alternative embodiment of the invention in which the emitter is formed using the emitter layer with the germanium concentration profile of FIG. 6A .
- a substrate 11 used to form a device structure for a bipolar junction transistor comprises a single-crystal semiconductor material usable to form the devices of an integrated circuit.
- the substrate 11 may be comprised of a wafer of a monocrystalline silicon-containing material, such as a single-crystal silicon wafer, or a device layer of a silicon-on-insulator wafer.
- the semiconductor material constituting the substrate 11 may comprise an electrically-active dopant that alters its electrical properties and may also include an optional epitaxial layer at its top surface 11 a.
- the substrate 11 may comprise an n-type dopant from Group V of the Periodic Table (e.g., phosphorus (P), arsenic (As), or antimony (Sb)) in a concentration that is effective to impart n-type conductivity.
- Group V of the Periodic Table e.g., phosphorus (P), arsenic (As), or antimony (Sb)
- P phosphorus
- As arsenic
- Sb antimony
- a layer stack including a base layer 13 and an emitter layer 15 is formed on the substrate 11 .
- the base layer 13 is located on the top surface 11 a of substrate 11
- the emitter layer 15 is located on a top surface of the base layer 13 .
- the base layer 13 and emitter layer 15 may each include a germanium content and the germanium content of the emitter layer 15 may be tailored such that the sidewalls of the emitter subsequently formed from the emitter layer 15 can be shaped, when etched, to impart a shape to the emitter.
- the base layer 13 may be comprised of a different semiconductor material than the collector 14 and may have an opposite conductivity type from the collector 14 .
- the base layer 13 may be comprised of a semiconductor material, such as silicon-germanium (SiGe) in an alloy with a content of silicon (Si) ranging from 95 atomic percent to 50 atomic percent and a content of germanium (Ge) ranging from 5 atomic percent to 50 atomic percent.
- the germanium content of the base layer 13 may be graded and/or stepped across the thickness of base layer 13 .
- the semiconductor material of the base layer 13 may further comprise a dopant, such as a p-type dopant selected from Group III of the Periodic Table (e.g., boron) in a concentration that is effective to impart p-type conductivity and, optionally, carbon (C) to suppress the outdiffusion of the p-type dopant.
- a dopant such as a p-type dopant selected from Group III of the Periodic Table (e.g., boron) in a concentration that is effective to impart p-type conductivity and, optionally, carbon (C) to suppress the outdiffusion of the p-type dopant.
- the base layer 13 may be formed using a low temperature epitaxial (LTE) growth process, such as vapor phase epitaxy (VPE) conducted at a growth temperature ranging from 400° C. to 850° C.
- LTE low temperature epitaxial
- VPE vapor phase epitaxy
- Single crystal semiconductor material e.g., single crystal silicon and/or single crystal silicon germanium
- the base layer 13 may have an epitaxial relationship with the single crystal semiconductor material of the substrate 11 in which the crystal structure and orientation of the substrate 11 operates as a template to establish the crystal structure and orientation of the base layer 13 during growth.
- the emitter layer 15 may be comprised of a semiconductor material, such as silicon-germanium (SiGe) including silicon (Si) and germanium (Ge) in a composition with a silicon content ranging from 95 atomic percent to 50 atomic percent and a germanium content ranging from 5 atomic percent to 50 atomic percent, or SiGe:C with a composition having up to 10 percent carbon.
- the emitter layer 15 may comprise a dopant, such as a p-type dopant selected from Group III of the Periodic Table (e.g., boron) in a concentration that is effective to impart p-type conductivity and, optionally, carbon (C) to suppress the outdiffusion of the p-type dopant.
- a dopant such as a p-type dopant selected from Group III of the Periodic Table (e.g., boron) in a concentration that is effective to impart p-type conductivity and, optionally, carbon (C) to suppress the outdiffusion of the
- the semiconductor material of the emitter layer 15 may be formed by the same growth process used to deposit the base layer 13 .
- Epitaxial growth is a process by which the single-crystal semiconductor material of the emitter layer 15 is deposited on the single-crystal semiconductor material of the base layer 13 and in which the crystallographic structure of the single-crystal material of the base layer 13 is reproduced in the semiconductor material of the emitter layer 15 .
- the semiconductor material constituting the emitter layer 15 will acquire the crystal orientation and crystal structure of single crystal semiconductor material of the base layer 13 , which serves as a template for growth of the emitter layer 15 .
- the base layer 13 and the emitter layer 15 each include a germanium concentration in their respective semiconductor compositions that varies as a function of vertical position (i.e., the z-direction in FIG. 3A ) relative to the top surface 11 a of the substrate 11 .
- the horizontal dashed lines overlaid on the germanium concentration profile in FIG. 3A indicate the respective transitions in vertical position in the device structure 10 from the substrate 11 to the base layer 13 and from the base layer 13 to the emitter layer 15 for a device structure 10 in which the thickness of the base layer 13 is equal to three times the thickness of the emitter layer 15 .
- the germanium concentration in the base layer 13 varies over its thickness.
- the germanium concentration in the base layer 13 may vary across the layer thickness.
- the germanium concentration increases initially with increasing distance from the substrate 11 , plateaus at a peak concentration over the majority of its thickness, and then decreases with increasing distance from the substrate 11 .
- the germanium concentration for vertical positions Z over the remainder of the thickness of the base layer 13 may be small negligible.
- the germanium concentration in the base layer 13 may have a graded or stepped appearance that differs from the representative trapezoidal appearance.
- the emitter layer 15 is located above the base layer 13 with increasing vertical position in FIG. 3A relative to the top surface 11 a of the substrate 11 .
- the emitter layer 15 includes a concentration of germanium that varies with vertical position Z. In the representative concentration profile, the germanium concentration of the emitter layer 15 increases from a location near its bottom surface (i.e., the interface with the base layer 13 ) and reaches a peak concentration near its top surface. The decrease in the germanium concentration may be linear. The peak concentration of germanium in the emitter layer 15 is less than the peak concentration of germanium in the base layer 13 .
- the variation in the germanium concentration in the emitter layer 15 is employed to cause a variation in lateral etch rate with the result that the emitter formed from the emitter layer 15 has non-vertical (i.e., inclined) sidewalls.
- the emitter layer 15 may include implantation damage to its constituent semiconductor material and/or implantation-doping of its semiconductor material that augment the varying germanium concentration to alter etch rate and, thereby, the profile for the sidewalls of the emitter. Similar to the germanium concentration profile, the damage or doping may be likewise non-uniform over the thickness of the emitter layer 15 .
- a hardmask layer 17 is located on a top surface of the emitter layer 15 .
- the hardmask layer 17 is comprised of a material that etches selective to the material of the emitter layer 15 .
- the hardmask layer 17 may be comprised of a dielectric material, such as silicon dioxide.
- a device structure 10 for a bipolar junction transistor is formed from the layers 13 , 15 and the substrate 11 by etching trenches 18 , 20 that extend to a shallow depth beneath the top surface 11 a of the substrate 11 .
- the trenches 18 , 20 may be formed by a dry etching process (e.g., reactive-ion etching (RIE)), a wet chemical etching process, or a combination of wet and dry etching processes conducted in one or more steps using one or more etch chemistries.
- RIE reactive-ion etching
- the trenches 18 , 20 are formed in alignment with openings in the hardmask layer 17 .
- a section of the base layer 12 is positioned between the trenches 18 , 20 and includes an intrinsic base 28 of the device structure 10 .
- a section of the emitter layer 15 is positioned between the trenches 18 , 20 and defines an emitter 16 of the device structure 10 .
- One of the etching processes causes the base layer 13 to be undercut so that the substrate 11 is replaced by cavities located beneath peripheral sections 34 , 36 of the base layer 13 .
- the trenches 18 , 20 are subsequently used to form trench isolation regions filled with dielectric material.
- the emitter layer 15 is also narrowed by the etching processes in that the emitter layer 15 is also undercut relative to the hardmask layer 17 .
- the emitter layer 15 is narrowed to a greater extent than the base layer 13 due to the lower concentration of germanium in its constituent semiconductor material, which results in an increased etch rate so that the emitter layer 15 etches selective to (i.e., at a higher etch rate than) the base layer 13 .
- An exemplary composition-sensitive etchant that etches the semiconductor material of emitter layer 15 with a higher etch rate than the semiconductor material of the base layer 13 is an ammonia hydroxide-based or a potassium hydroxide-based chemical etchant.
- the shape of the emitter 16 and the profile for its sidewalls 25 , 27 result from the variation in germanium concentration over the thickness of the emitter layer 15 and the resulting composition-dependent etch rate that varies as a function of the germanium concentration over the height of the emitter 16 .
- the emitter 16 Due to the compositional-dependent etch rate, the emitter 16 is characterized by a width that varies as a function of height H (i.e., the thickness of the emitter layer 15 ) in coordination with the variation in germanium concentration.
- the variation in the germanium concentration is linear over the height H of the emitter 16 .
- the implantation damage and/or doping of the semiconductor material of the emitter layer 15 may be used to alter etch rates and determine, at least in part, the profile of the sidewalls 25 , 27 and the shape of the emitter 16 .
- the emitter 16 includes sidewalls 25 , 27 that are separated by a narrower width W 1 at the top surface used to contact the emitter 16 and by wider width W 2 at a bottom surface defining an interface with the base layer 13 .
- Width W 1 is greater than width W 2 such that the width narrows over the height H of the emitter 16 in a direction from the top surface of the emitter 16 toward the interface with the intrinsic base 28 . Due to the linear variation in the germanium concentration in the representative embodiment, the width of the emitter 16 linearly varies over the height H from width W 1 to width W 2 to produce the trapezoidal shape.
- the collector 14 may be comprised of a section of the material of the substrate 11 located between the trenches 18 , 20 and may contain a concentration of an n-type dopant in a concentration that is effective to impart n-type conductivity.
- the dopant concentration of the collector 14 may be elevated to enhance its electrical conductivity by ion implantation or the growth of a doped epitaxial layer at the top surface 11 a of the substrate 11 .
- the collector contacts 22 , 24 are separated laterally from the collector 14 by the trenches 18 , 20 .
- a sub-collector 26 extends laterally from the collector 14 beneath the trenches 18 , 20 to couple the collector 14 with the collector contacts 22 , 24 .
- the collector contacts 22 , 24 and sub-collector 26 are also comprised of the semiconductor material of the substrate 11 and have the same conductivity type as the semiconductor material comprising the collector 14 .
- the device structure 10 which is characterized by a vertical architecture, includes the emitter 16 , the collector 14 , and the intrinsic base 28 positioned between the emitter 16 and collector 14 .
- the intrinsic base 28 is coextensive with the collector 14 along an interface or junction 30
- the emitter 16 is coextensive with the intrinsic base 28 along another interface or junction 32 .
- Sections 34 , 36 of the base layer 13 which are peripheral to the intrinsic base 28 , may collectively define an extrinsic base 38 that is coupled with the intrinsic base 28 .
- the sections 34 , 36 of the base layer 13 defining the extrinsic base 38 at least partially overhang the trenches 18 , 20 and the trench isolation regions subsequently formed in the trenches 18 , 20 .
- the device structure 10 may be characterized as a heterojunction bipolar transistor (HBT) if two or all three of the collector 14 , the emitter 16 , and the intrinsic base 28 are comprised of semiconductor materials with different bandgaps.
- HBT heterojunction bipolar transistor
- a dielectric layer 40 is located on the exposed surfaces of the base layer 13 , the emitter 16 , and the substrate 11 , and a dielectric layer 42 is located on the dielectric layer 40 .
- the dielectric layers 40 , 42 may be comprised of different electrical insulator characterized by a dielectric constant (e.g., a permittivity) characteristic of a dielectric material.
- the dielectric layer 40 may be comprised of silicon dioxide (SiO 2 ) deposited using a rapid thermal process or formed by thermal oxidation
- dielectric layer 42 may be comprised of an electrical insulator, such as silicon nitride (Si 3 N 4 ), that is conformally deposited by chemical vapor deposition.
- a directional anisotropic etching process such as RIE, is used to preferentially remove the dielectric layer 42 from horizontal surfaces, such as the top surface 12 a of the base layer 13 , and partially horizontal surfaces, such as the inclined surfaces inside the trenches 18 , 20 .
- Spacers 43 are formed from the dielectric layers 40 , 42 on the sidewalls 23 , 25 of the emitter 16 by the preferential removal of the dielectric layer 42 .
- the sections 34 , 36 of base layer 13 defining the extrinsic base 38 are not covered by the emitter 16 and the spacers 43 , and project laterally from the intrinsic base 28 that is covered by the emitter 16 and the spacers 43 .
- These sections 34 , 36 which are used to contact the covered intrinsic base 28 , may be modified by ion implantation to increase their electrical conductivity.
- the dielectric layer 40 is removed from the horizontal surfaces to expose the top surface of the emitter 16 , the top surfaces of the collector contacts 22 , 24 , and the top surface of sections 34 , 36 of the base layer 13 .
- a silicide layer 56 is formed on these top surfaces and may be subsequently used in the process flow to contact the extrinsic base 38 , collector contacts 22 , 24 , and the emitter 16 .
- MOL processing which includes formation of a dielectric layer 60 , contacts 62 , 63 , 64 , and wiring, follows to define a local interconnect structure.
- Contacts 62 are coupled with the collector contacts 22 , 24
- contacts 63 are coupled with the extrinsic base 38
- contacts 64 are coupled with the emitter 16 .
- Candidate inorganic dielectric materials for the dielectric layer 60 may include, but are not limited to, borophosphosilicate glass (BPSG), silicon dioxide (SiO 2 ), silicon nitride (Si 3 N 4 ), fluorine-doped silicon glass (FSG), and combinations of these and other dielectric materials.
- Dielectric layer 60 may be deposited by any number of techniques including, but not limited to, sputtering, spin-on application, or CVD. Portions of the dielectric layer 60 may at least partially fill the trenches 18 , 20 to define trench isolation regions 66 , 68 that laterally flank the collector 14 .
- BEOL processing follows, which includes formation of additional dielectric layers, via plugs, and wiring for an interconnect structure coupled by the local interconnect structure with the device structure 10 , as well as other similar contacts for additional device structures like device structure 10 and CMOS transistors that may be included in other circuitry fabricated on the substrate 11 .
- an emitter 70 has a different shape than emitter 16 .
- the emitter 70 has a trapezoidal shape that is inverted relative to the trapezoidal shape of emitter 16 .
- the emitter 70 (and the emitter layer 15 used to form the emitter 70 ) includes a concentration of germanium that varies with vertical position Z.
- the germanium concentration of the emitter 70 reaches a peak concentration at a location near its bottom surface and decreases with vertical position Z from the peak concentration to lesser concentration in a direction toward its top surface.
- the decrease in germanium concentration may be linear.
- the shape of the emitter 70 results from the variation in germanium concentration over the thickness of the emitter layer 15 and the resulting composition-dependent etch rate that varies as a function of the germanium concentration.
- the emitter 70 is characterized by a width that varies as a function of height H (i.e., the thickness of the emitter layer 15 ) in coordination with the variation in germanium concentration.
- the variation in the germanium concentration is linear over the height H of the emitter 70 .
- the emitter 70 is characterized by a width that varies as a function of height H over the thickness of the emitter layer 15 .
- the sidewalls 23 , 25 of the emitter 70 are inclined at an angle relative to a surface normal of the substrate 11 such that the emitter 70 tapers from a larger width to a smaller width with increasing distance from the intrinsic base 28 .
- the sidewalls 25 , 27 of the emitter 16 are separated by a width W 3 at the top surface used to contact the emitter 70 and by a width W 4 at a bottom surface defining an interface with the intrinsic base 28 .
- Width W 4 is greater than width W 3 such that the emitter 70 has a trapezoidal shape that narrows in a direction from its top surface toward its bottom surface. Due to the linear variation in the germanium concentration in the representative embodiment, the width of the emitter 70 linearly varies over the height H from width W 3 to width W 4 to produce the inverted trapezoidal shape.
- an emitter 72 has a different shape than emitter 16 or emitter 70 .
- the emitter 72 has a bi-tapered shape that necks down from maximum widths W 5 at the top surface and W 7 at the bottom surface to a minimum width W 6 at a location between the top and bottom surfaces (e.g., equidistant in the representative embodiment from the location between the top and bottom surfaces).
- the emitter 72 comprises abutting trapezoids that taper from larger widths W 5 , W 7 to a smaller width W 6 .
- the emitter 72 (and the emitter layer 15 used to form the emitter 72 ) includes a concentration of germanium that varies with vertical position Z.
- the germanium concentration of the emitter 72 decreases from a peak concentration at a location near its bottom surface, decreases from peak concentration at a location near its top surface, and reaches a minimum concentration at location between the top and bottom surfaces.
- the decrease in germanium concentration may be linear.
- the shape of the emitter 72 results from the variation in germanium concentration over the thickness of the emitter layer 15 and the resulting composition-dependent etch rate that varies as a function of the germanium concentration.
- the emitter 72 is characterized by a width that varies as a function of height H (i.e., the thickness of the emitter layer 15 ) in coordination with the variation in germanium concentration.
- the germanium concentration over the height H of the emitter 72 decreases linearly from the peak concentration at the top surface toward a minimum concentration between the top and bottom surfaces and decreases from the peak concentration the bottom surface toward the minimum concentration between the top and bottom surfaces.
- the emitter 72 is characterized by a width that varies as a function of height H over the thickness of the emitter layer 15 . Specifically, the emitter 72 tapers from a wider width W 5 at each of its top and bottom surfaces to a narrower width W 6 between the top and bottom surfaces. Width W 4 is greater than width W 3 such that the emitter 72 has a trapezoidal shape that narrows in a direction from its top surface toward its bottom surface. Due to the linear variation in the germanium concentration in the representative embodiment, the width of the emitter 72 linearly varies over the height H from width W 5 to width W 6 over each of its abutting trapezoidal shapes.
- the methods as described above are used in the fabrication of integrated circuit chips.
- the resulting integrated circuit chips can be distributed by the fabricator in raw wafer form (e.g., as a single wafer that has multiple unpackaged chips), as a bare die, or in a packaged form.
- the chip is mounted in a single chip package (e.g., a plastic carrier, with leads that are affixed to a motherboard or other higher level carrier) or in a multichip package (e.g., a ceramic carrier that has either or both surface interconnections or buried interconnections).
- the chip is then integrated with other chips, discrete circuit elements, and/or other signal processing devices as part of either (a) an intermediate product, such as a motherboard, or (b) an end product.
- the end product can be any product that includes integrated circuit chips, ranging from toys and other low-end applications to advanced computer products having a display, a keyboard or other input device, and a central processor.
- a feature may be “connected” or “coupled” to or with another element may be directly connected or coupled to the other element or, instead, one or more intervening elements may be present.
- a feature may be “directly connected” or “directly coupled” to another element if intervening elements are absent.
- a feature may be “indirectly connected” or “indirectly coupled” to another element if at least one intervening element is present.
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Ceramic Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Chemical & Material Sciences (AREA)
- Chemical Kinetics & Catalysis (AREA)
- General Chemical & Material Sciences (AREA)
- Bipolar Transistors (AREA)
Abstract
Description
- The invention relates generally to semiconductor devices and integrated circuit fabrication and, in particular, to fabrication methods and device structures for a bipolar junction transistor.
- Bipolar junction transistors may be found, among other end uses, in high-frequency and high-power applications. In particular, bipolar junction transistors may find specific end uses in amplifiers for wireless communications systems and mobile devices, switches, and oscillators. Bipolar junction transistors may also be used in high-speed logic circuits. Bipolar junction transistors are three-terminal electronic devices that include an emitter, an intrinsic base, and a collector defined by regions of different semiconductor materials. In the device structure, the intrinsic base situated between the emitter and collector. An NPN bipolar junction transistor may include n-type semiconductor material regions constituting the emitter and collector, and a region of p-type semiconductor material constituting the intrinsic base. A PNP bipolar junction transistor includes p-type semiconductor material regions constituting the emitter and collector, and a region of n-type semiconductor material constituting the intrinsic base. In operation, the base-emitter junction is forward biased and the base-collector junction is reverse biased. The collector-emitter current may be controlled by the base-emitter voltage.
- Improved fabrication methods and device structures are needed for a bipolar junction transistor.
- In an embodiment of the invention, a method is provided for fabricating a device structure. An emitter layer is formed on a base layer and etched to form an emitter of the device structure. The emitter layer has a concentration of an element that varies as a function of the thickness of the emitter layer. The etch rate of the emitter layer varies as a function of the concentration of the element such that the emitter has a variable width over the thickness of the emitter layer.
- In an embodiment of the invention, a device structure is provided for a bipolar junction transistor. The device structure includes a base layer and an emitter on the base layer,. The emitter has a height and a concentration of an element that varies as a function of the height. The emitter has a width that varies as a function of the height in relation to the concentration of the element.
- The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate various embodiments of the invention and, together with a general description of the invention given above and the detailed description of the embodiments given below, serve to explain the embodiments of the invention.
-
FIG. 1 is a cross-sectional view of a portion of a substrate at an initial fabrication stage of a processing method for fabricating a device structure in accordance with an embodiment of the invention. -
FIG. 2 is a cross-sectional view of the substrate portion ofFIG. 1 at a subsequent fabrication stage of the processing method. -
FIG. 3A is a diagrammatic view of a germanium concentration profile in the base layer and the emitter layer. -
FIG. 3B is an enlarged view of a portion ofFIG. 2 . -
FIG. 4 is a cross-sectional view of the substrate portion ofFIG. 2 at a subsequent fabrication stage of the processing method. -
FIG. 5A is a diagrammatic view similar toFIG. 3A showing a germanium concentration profile in the base layer and the emitter layer in accordance with an alternative embodiment of the invention. -
FIG. 5B is an enlarged view similar toFIG. 3B of an emitter in accordance with an alternative embodiment of the invention in which the emitter is formed using the emitter layer with the germanium concentration profile ofFIG. 5A . -
FIG. 6A is a diagrammatic view similar toFIG. 3A showing a germanium concentration profile in the base layer and the emitter layer in accordance with an alternative embodiment of the invention. -
FIG. 6B is an enlarged view similar toFIG. 3B of an emitter in accordance with an alternative embodiment of the invention in which the emitter is formed using the emitter layer with the germanium concentration profile ofFIG. 6A . - With reference to
FIG. 1 and in accordance with an embodiment of the invention, asubstrate 11 used to form a device structure for a bipolar junction transistor comprises a single-crystal semiconductor material usable to form the devices of an integrated circuit. For example, thesubstrate 11 may be comprised of a wafer of a monocrystalline silicon-containing material, such as a single-crystal silicon wafer, or a device layer of a silicon-on-insulator wafer. The semiconductor material constituting thesubstrate 11 may comprise an electrically-active dopant that alters its electrical properties and may also include an optional epitaxial layer at itstop surface 11 a. Thesubstrate 11 may comprise an n-type dopant from Group V of the Periodic Table (e.g., phosphorus (P), arsenic (As), or antimony (Sb)) in a concentration that is effective to impart n-type conductivity. - A layer stack including a
base layer 13 and anemitter layer 15 is formed on thesubstrate 11. Thebase layer 13 is located on thetop surface 11 a ofsubstrate 11, and theemitter layer 15 is located on a top surface of thebase layer 13. Thebase layer 13 andemitter layer 15 may each include a germanium content and the germanium content of theemitter layer 15 may be tailored such that the sidewalls of the emitter subsequently formed from theemitter layer 15 can be shaped, when etched, to impart a shape to the emitter. - The
base layer 13 may be comprised of a different semiconductor material than thecollector 14 and may have an opposite conductivity type from thecollector 14. Thebase layer 13 may be comprised of a semiconductor material, such as silicon-germanium (SiGe) in an alloy with a content of silicon (Si) ranging from 95 atomic percent to 50 atomic percent and a content of germanium (Ge) ranging from 5 atomic percent to 50 atomic percent. The germanium content of thebase layer 13 may be graded and/or stepped across the thickness ofbase layer 13. The semiconductor material of thebase layer 13 may further comprise a dopant, such as a p-type dopant selected from Group III of the Periodic Table (e.g., boron) in a concentration that is effective to impart p-type conductivity and, optionally, carbon (C) to suppress the outdiffusion of the p-type dopant. - The
base layer 13 may be formed using a low temperature epitaxial (LTE) growth process, such as vapor phase epitaxy (VPE) conducted at a growth temperature ranging from 400° C. to 850° C. Single crystal semiconductor material (e.g., single crystal silicon and/or single crystal silicon germanium) is epitaxially grown or deposited by low temperature epitaxial growth on thetop surface 11 a ofsubstrate 11. Thebase layer 13 may have an epitaxial relationship with the single crystal semiconductor material of thesubstrate 11 in which the crystal structure and orientation of thesubstrate 11 operates as a template to establish the crystal structure and orientation of thebase layer 13 during growth. - The
emitter layer 15 may be comprised of a semiconductor material, such as silicon-germanium (SiGe) including silicon (Si) and germanium (Ge) in a composition with a silicon content ranging from 95 atomic percent to 50 atomic percent and a germanium content ranging from 5 atomic percent to 50 atomic percent, or SiGe:C with a composition having up to 10 percent carbon. Theemitter layer 15 may comprise a dopant, such as a p-type dopant selected from Group III of the Periodic Table (e.g., boron) in a concentration that is effective to impart p-type conductivity and, optionally, carbon (C) to suppress the outdiffusion of the p-type dopant. The semiconductor material of theemitter layer 15 may be formed by the same growth process used to deposit thebase layer 13. Epitaxial growth is a process by which the single-crystal semiconductor material of theemitter layer 15 is deposited on the single-crystal semiconductor material of thebase layer 13 and in which the crystallographic structure of the single-crystal material of thebase layer 13 is reproduced in the semiconductor material of theemitter layer 15. During epitaxial growth, the semiconductor material constituting theemitter layer 15 will acquire the crystal orientation and crystal structure of single crystal semiconductor material of thebase layer 13, which serves as a template for growth of theemitter layer 15. - As best shown in
FIG. 3A , thebase layer 13 and theemitter layer 15 each include a germanium concentration in their respective semiconductor compositions that varies as a function of vertical position (i.e., the z-direction inFIG. 3A ) relative to thetop surface 11 a of thesubstrate 11. The horizontal dashed lines overlaid on the germanium concentration profile inFIG. 3A indicate the respective transitions in vertical position in thedevice structure 10 from thesubstrate 11 to thebase layer 13 and from thebase layer 13 to theemitter layer 15 for adevice structure 10 in which the thickness of thebase layer 13 is equal to three times the thickness of theemitter layer 15. - The germanium concentration in the
base layer 13 varies over its thickness. In the representative embodiment, the germanium concentration in thebase layer 13 may vary across the layer thickness. The germanium concentration increases initially with increasing distance from thesubstrate 11, plateaus at a peak concentration over the majority of its thickness, and then decreases with increasing distance from thesubstrate 11. The germanium concentration for vertical positions Z over the remainder of the thickness of thebase layer 13 may be small negligible. Alternatively, the germanium concentration in thebase layer 13 may have a graded or stepped appearance that differs from the representative trapezoidal appearance. - The
emitter layer 15 is located above thebase layer 13 with increasing vertical position inFIG. 3A relative to thetop surface 11 a of thesubstrate 11. Theemitter layer 15 includes a concentration of germanium that varies with vertical position Z. In the representative concentration profile, the germanium concentration of theemitter layer 15 increases from a location near its bottom surface (i.e., the interface with the base layer 13) and reaches a peak concentration near its top surface. The decrease in the germanium concentration may be linear. The peak concentration of germanium in theemitter layer 15 is less than the peak concentration of germanium in thebase layer 13. As discussed hereinbelow, the variation in the germanium concentration in theemitter layer 15 is employed to cause a variation in lateral etch rate with the result that the emitter formed from theemitter layer 15 has non-vertical (i.e., inclined) sidewalls. - In an alternative embodiment, the
emitter layer 15 may include implantation damage to its constituent semiconductor material and/or implantation-doping of its semiconductor material that augment the varying germanium concentration to alter etch rate and, thereby, the profile for the sidewalls of the emitter. Similar to the germanium concentration profile, the damage or doping may be likewise non-uniform over the thickness of theemitter layer 15. - A
hardmask layer 17 is located on a top surface of theemitter layer 15. Thehardmask layer 17 is comprised of a material that etches selective to the material of theemitter layer 15. Thehardmask layer 17 may be comprised of a dielectric material, such as silicon dioxide. - With reference to
FIGS. 2, 3B in which like reference numerals refer to like features inFIG. 1 and at a subsequent fabrication stage of the processing method, adevice structure 10 for a bipolar junction transistor is formed from thelayers substrate 11 by etchingtrenches top surface 11 a of thesubstrate 11. Thetrenches trenches hardmask layer 17. A section of thebase layer 12 is positioned between thetrenches intrinsic base 28 of thedevice structure 10. A section of theemitter layer 15 is positioned between thetrenches emitter 16 of thedevice structure 10. One of the etching processes causes thebase layer 13 to be undercut so that thesubstrate 11 is replaced by cavities located beneath peripheral sections 34, 36 of thebase layer 13. Thetrenches - The
emitter layer 15 is also narrowed by the etching processes in that theemitter layer 15 is also undercut relative to thehardmask layer 17. Generally, theemitter layer 15 is narrowed to a greater extent than thebase layer 13 due to the lower concentration of germanium in its constituent semiconductor material, which results in an increased etch rate so that theemitter layer 15 etches selective to (i.e., at a higher etch rate than) thebase layer 13. An exemplary composition-sensitive etchant that etches the semiconductor material ofemitter layer 15 with a higher etch rate than the semiconductor material of thebase layer 13 is an ammonia hydroxide-based or a potassium hydroxide-based chemical etchant. At the conclusion of the etching processes, a section of theemitter layer 15 defining theemitter 16 is centrally located over thebase layer 13. - The shape of the
emitter 16 and the profile for itssidewalls 25, 27 result from the variation in germanium concentration over the thickness of theemitter layer 15 and the resulting composition-dependent etch rate that varies as a function of the germanium concentration over the height of theemitter 16. Due to the compositional-dependent etch rate, theemitter 16 is characterized by a width that varies as a function of height H (i.e., the thickness of the emitter layer 15) in coordination with the variation in germanium concentration. In the representative embodiment, the variation in the germanium concentration is linear over the height H of theemitter 16. In an alternative embodiment, the implantation damage and/or doping of the semiconductor material of theemitter layer 15 may be used to alter etch rates and determine, at least in part, the profile of thesidewalls 25, 27 and the shape of theemitter 16. - The
emitter 16 includes sidewalls 25, 27 that are separated by a narrower width W1 at the top surface used to contact theemitter 16 and by wider width W2 at a bottom surface defining an interface with thebase layer 13. Width W1 is greater than width W2 such that the width narrows over the height H of theemitter 16 in a direction from the top surface of theemitter 16 toward the interface with theintrinsic base 28. Due to the linear variation in the germanium concentration in the representative embodiment, the width of theemitter 16 linearly varies over the height H from width W1 to width W2 to produce the trapezoidal shape. - The
collector 14 may be comprised of a section of the material of thesubstrate 11 located between thetrenches collector 14 may be elevated to enhance its electrical conductivity by ion implantation or the growth of a doped epitaxial layer at thetop surface 11 a of thesubstrate 11. Thecollector contacts collector 14 by thetrenches collector 14 beneath thetrenches collector 14 with thecollector contacts collector contacts substrate 11 and have the same conductivity type as the semiconductor material comprising thecollector 14. - The
device structure 10, which is characterized by a vertical architecture, includes theemitter 16, thecollector 14, and theintrinsic base 28 positioned between theemitter 16 andcollector 14. Theintrinsic base 28 is coextensive with thecollector 14 along an interface orjunction 30, and theemitter 16 is coextensive with theintrinsic base 28 along another interface orjunction 32. Sections 34, 36 of thebase layer 13, which are peripheral to theintrinsic base 28, may collectively define an extrinsic base 38 that is coupled with theintrinsic base 28. In the representative device structure, the sections 34, 36 of thebase layer 13 defining the extrinsic base 38 at least partially overhang thetrenches trenches device structure 10 may be characterized as a heterojunction bipolar transistor (HBT) if two or all three of thecollector 14, theemitter 16, and theintrinsic base 28 are comprised of semiconductor materials with different bandgaps. - A
dielectric layer 40 is located on the exposed surfaces of thebase layer 13, theemitter 16, and thesubstrate 11, and adielectric layer 42 is located on thedielectric layer 40. The dielectric layers 40, 42 may be comprised of different electrical insulator characterized by a dielectric constant (e.g., a permittivity) characteristic of a dielectric material. In one embodiment, thedielectric layer 40 may be comprised of silicon dioxide (SiO2) deposited using a rapid thermal process or formed by thermal oxidation, anddielectric layer 42 may be comprised of an electrical insulator, such as silicon nitride (Si3N4), that is conformally deposited by chemical vapor deposition. A directional anisotropic etching process, such as RIE, is used to preferentially remove thedielectric layer 42 from horizontal surfaces, such as thetop surface 12 a of thebase layer 13, and partially horizontal surfaces, such as the inclined surfaces inside thetrenches Spacers 43 are formed from thedielectric layers sidewalls emitter 16 by the preferential removal of thedielectric layer 42. - With reference to
FIG. 4 in which like reference numerals refer to like features inFIG. 2 and at a subsequent fabrication stage of the processing method, the sections 34, 36 ofbase layer 13 defining the extrinsic base 38 are not covered by theemitter 16 and thespacers 43, and project laterally from theintrinsic base 28 that is covered by theemitter 16 and thespacers 43. These sections 34, 36, which are used to contact the coveredintrinsic base 28, may be modified by ion implantation to increase their electrical conductivity. - The
dielectric layer 40 is removed from the horizontal surfaces to expose the top surface of theemitter 16, the top surfaces of thecollector contacts base layer 13. Asilicide layer 56 is formed on these top surfaces and may be subsequently used in the process flow to contact the extrinsic base 38,collector contacts emitter 16. - Middle-of-line (MOL) processing, which includes formation of a
dielectric layer 60,contacts Contacts 62 are coupled with thecollector contacts contacts 63 are coupled with the extrinsic base 38, andcontacts 64 are coupled with theemitter 16. Candidate inorganic dielectric materials for thedielectric layer 60 may include, but are not limited to, borophosphosilicate glass (BPSG), silicon dioxide (SiO2), silicon nitride (Si3N4), fluorine-doped silicon glass (FSG), and combinations of these and other dielectric materials.Dielectric layer 60 may be deposited by any number of techniques including, but not limited to, sputtering, spin-on application, or CVD. Portions of thedielectric layer 60 may at least partially fill thetrenches collector 14. - Back-end-of-line (BEOL) processing follows, which includes formation of additional dielectric layers, via plugs, and wiring for an interconnect structure coupled by the local interconnect structure with the
device structure 10, as well as other similar contacts for additional device structures likedevice structure 10 and CMOS transistors that may be included in other circuitry fabricated on thesubstrate 11. - With reference to
FIGS. 5A, 5B in which like reference numerals refer to like features inFIGS. 2, 3B and in accordance with an alternative embodiment of the invention, anemitter 70 has a different shape thanemitter 16. Specifically, theemitter 70 has a trapezoidal shape that is inverted relative to the trapezoidal shape ofemitter 16. - The emitter 70 (and the
emitter layer 15 used to form the emitter 70) includes a concentration of germanium that varies with vertical position Z. In the representative profile, the germanium concentration of theemitter 70 reaches a peak concentration at a location near its bottom surface and decreases with vertical position Z from the peak concentration to lesser concentration in a direction toward its top surface. The decrease in germanium concentration may be linear. The shape of theemitter 70 results from the variation in germanium concentration over the thickness of theemitter layer 15 and the resulting composition-dependent etch rate that varies as a function of the germanium concentration. Due to the compositional-dependent etch rate, theemitter 70 is characterized by a width that varies as a function of height H (i.e., the thickness of the emitter layer 15) in coordination with the variation in germanium concentration. In the representative embodiment, the variation in the germanium concentration is linear over the height H of theemitter 70. - Due to the compositional-based variation in the etch rate, the
emitter 70 is characterized by a width that varies as a function of height H over the thickness of theemitter layer 15. Specifically, thesidewalls emitter 70 are inclined at an angle relative to a surface normal of thesubstrate 11 such that theemitter 70 tapers from a larger width to a smaller width with increasing distance from theintrinsic base 28. Thesidewalls 25, 27 of theemitter 16 are separated by a width W3 at the top surface used to contact theemitter 70 and by a width W4 at a bottom surface defining an interface with theintrinsic base 28. Width W4 is greater than width W3 such that theemitter 70 has a trapezoidal shape that narrows in a direction from its top surface toward its bottom surface. Due to the linear variation in the germanium concentration in the representative embodiment, the width of theemitter 70 linearly varies over the height H from width W3 to width W4 to produce the inverted trapezoidal shape. - With reference to
FIGS. 6A, 6B in which like reference numerals refer to like features inFIGS. 2, 3B and in accordance with an alternative embodiment of the invention, anemitter 72 has a different shape thanemitter 16 oremitter 70. Specifically, theemitter 72 has a bi-tapered shape that necks down from maximum widths W5 at the top surface and W7 at the bottom surface to a minimum width W6 at a location between the top and bottom surfaces (e.g., equidistant in the representative embodiment from the location between the top and bottom surfaces). Theemitter 72 comprises abutting trapezoids that taper from larger widths W5, W7 to a smaller width W6. - The emitter 72 (and the
emitter layer 15 used to form the emitter 72) includes a concentration of germanium that varies with vertical position Z. In the representative profile, the germanium concentration of theemitter 72 decreases from a peak concentration at a location near its bottom surface, decreases from peak concentration at a location near its top surface, and reaches a minimum concentration at location between the top and bottom surfaces. The decrease in germanium concentration may be linear. The shape of theemitter 72 results from the variation in germanium concentration over the thickness of theemitter layer 15 and the resulting composition-dependent etch rate that varies as a function of the germanium concentration. Due to the compositional-dependent etch rate, theemitter 72 is characterized by a width that varies as a function of height H (i.e., the thickness of the emitter layer 15) in coordination with the variation in germanium concentration. In the representative embodiment, the germanium concentration over the height H of theemitter 72 decreases linearly from the peak concentration at the top surface toward a minimum concentration between the top and bottom surfaces and decreases from the peak concentration the bottom surface toward the minimum concentration between the top and bottom surfaces. - Due to the compositional-based variation in the etch rate, the
emitter 72 is characterized by a width that varies as a function of height H over the thickness of theemitter layer 15. Specifically, theemitter 72 tapers from a wider width W5 at each of its top and bottom surfaces to a narrower width W6 between the top and bottom surfaces. Width W4 is greater than width W3 such that theemitter 72 has a trapezoidal shape that narrows in a direction from its top surface toward its bottom surface. Due to the linear variation in the germanium concentration in the representative embodiment, the width of theemitter 72 linearly varies over the height H from width W5 to width W6 over each of its abutting trapezoidal shapes. - The methods as described above are used in the fabrication of integrated circuit chips. The resulting integrated circuit chips can be distributed by the fabricator in raw wafer form (e.g., as a single wafer that has multiple unpackaged chips), as a bare die, or in a packaged form. In the latter case, the chip is mounted in a single chip package (e.g., a plastic carrier, with leads that are affixed to a motherboard or other higher level carrier) or in a multichip package (e.g., a ceramic carrier that has either or both surface interconnections or buried interconnections). In any case, the chip is then integrated with other chips, discrete circuit elements, and/or other signal processing devices as part of either (a) an intermediate product, such as a motherboard, or (b) an end product. The end product can be any product that includes integrated circuit chips, ranging from toys and other low-end applications to advanced computer products having a display, a keyboard or other input device, and a central processor.
- A feature may be “connected” or “coupled” to or with another element may be directly connected or coupled to the other element or, instead, one or more intervening elements may be present. A feature may be “directly connected” or “directly coupled” to another element if intervening elements are absent. A feature may be “indirectly connected” or “indirectly coupled” to another element if at least one intervening element is present.
- The descriptions of the various embodiments of the present invention have been presented for purposes of illustration, but are not intended to be exhaustive or limited to the embodiments disclosed. Many modifications and variations will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the described embodiments. The terminology used herein was chosen to best explain the principles of the embodiments, the practical application or technical improvement over technologies found in the marketplace, or to enable others of ordinary skill in the art to understand the embodiments disclosed herein.
Claims (20)
Priority Applications (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US14/747,385 US20160380067A1 (en) | 2015-06-23 | 2015-06-23 | Shaped terminals for a bipolar junction transistor |
US15/626,241 US10170553B2 (en) | 2015-06-23 | 2017-06-19 | Shaped terminals for a bipolar junction transistor |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US14/747,385 US20160380067A1 (en) | 2015-06-23 | 2015-06-23 | Shaped terminals for a bipolar junction transistor |
Related Child Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US15/626,241 Division US10170553B2 (en) | 2015-06-23 | 2017-06-19 | Shaped terminals for a bipolar junction transistor |
Publications (1)
Publication Number | Publication Date |
---|---|
US20160380067A1 true US20160380067A1 (en) | 2016-12-29 |
Family
ID=57602855
Family Applications (2)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US14/747,385 Abandoned US20160380067A1 (en) | 2015-06-23 | 2015-06-23 | Shaped terminals for a bipolar junction transistor |
US15/626,241 Active US10170553B2 (en) | 2015-06-23 | 2017-06-19 | Shaped terminals for a bipolar junction transistor |
Family Applications After (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US15/626,241 Active US10170553B2 (en) | 2015-06-23 | 2017-06-19 | Shaped terminals for a bipolar junction transistor |
Country Status (1)
Country | Link |
---|---|
US (2) | US20160380067A1 (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20220336646A1 (en) * | 2021-04-14 | 2022-10-20 | Globalfoundries U.S. Inc. | Bipolar transistor with elevated extrinsic base and methods to form same |
Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7687887B1 (en) * | 2006-12-01 | 2010-03-30 | National Semiconductor Corporation | Method of forming a self-aligned bipolar transistor structure using a selectively grown emitter |
Family Cites Families (14)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US3892606A (en) | 1973-06-28 | 1975-07-01 | Ibm | Method for forming silicon conductive layers utilizing differential etching rates |
JPS60128622A (en) | 1983-12-16 | 1985-07-09 | Hitachi Ltd | Etching method |
CA1218956A (en) * | 1986-01-28 | 1987-03-10 | Thomas Abraham | Process for plasma etching polysilicon to produce rounded profile islands |
US4954457A (en) | 1988-10-31 | 1990-09-04 | International Business Machines Corporation | Method of making heterojunction bipolar transistors |
JPH0567626A (en) | 1991-09-06 | 1993-03-19 | Nec Corp | Manufacture of semiconductor device |
EP1137073A1 (en) | 2000-03-24 | 2001-09-26 | Infineon Technologies AG | Heterojunction bipolar transistor having a T-shaped emitter contact and method of making the same |
JP2002231818A (en) | 2001-02-02 | 2002-08-16 | Nec Yamagata Ltd | Semiconductor integrated circuit |
US6858485B2 (en) | 2003-05-07 | 2005-02-22 | International Business Machines Corporation | Method for creation of a very narrow emitter feature |
US7180159B2 (en) * | 2004-07-13 | 2007-02-20 | Texas Instruments Incorporated | Bipolar transistor having base over buried insulating and polycrystalline regions |
US7317215B2 (en) | 2004-09-21 | 2008-01-08 | International Business Machines Corporation | SiGe heterojunction bipolar transistor (HBT) |
US7579252B2 (en) | 2005-09-30 | 2009-08-25 | Microsemi Corporation | Self aligned process for BJT fabrication |
US7294869B2 (en) * | 2006-04-04 | 2007-11-13 | International Business Machines Corporation | Silicon germanium emitter |
US7888745B2 (en) * | 2006-06-21 | 2011-02-15 | International Business Machines Corporation | Bipolar transistor with dual shallow trench isolation and low base resistance |
CN103050521B (en) * | 2012-05-23 | 2015-02-04 | 上海华虹宏力半导体制造有限公司 | Collector region lead-out structure for SiGe heterojunction bipolar transistor (HBT) device, and manufacturing method for collector region lead-out structure |
-
2015
- 2015-06-23 US US14/747,385 patent/US20160380067A1/en not_active Abandoned
-
2017
- 2017-06-19 US US15/626,241 patent/US10170553B2/en active Active
Patent Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7687887B1 (en) * | 2006-12-01 | 2010-03-30 | National Semiconductor Corporation | Method of forming a self-aligned bipolar transistor structure using a selectively grown emitter |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20220336646A1 (en) * | 2021-04-14 | 2022-10-20 | Globalfoundries U.S. Inc. | Bipolar transistor with elevated extrinsic base and methods to form same |
US11588043B2 (en) * | 2021-04-14 | 2023-02-21 | Globalfoundries U.S. Inc. | Bipolar transistor with elevated extrinsic base and methods to form same |
Also Published As
Publication number | Publication date |
---|---|
US10170553B2 (en) | 2019-01-01 |
US20170288033A1 (en) | 2017-10-05 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US9583569B2 (en) | Profile control over a collector of a bipolar junction transistor | |
US9543403B2 (en) | Bipolar junction transistor with multiple emitter fingers | |
US9368608B1 (en) | Heterojunction bipolar transistor with improved performance and breakdown voltage | |
US9570564B2 (en) | Self-aligned emitter-base bipolar junction transistor with reduced base resistance and base-collector capacitance | |
US20160380088A1 (en) | Bipolar junction transistors with a buried dielectric region in the active device region | |
US9553145B2 (en) | Lateral bipolar junction transistors on a silicon-on-insulator substrate with a thin device layer thickness | |
US10777668B2 (en) | Bipolar junction transistors with a self-aligned emitter and base | |
US10367083B2 (en) | Compact device structures for a bipolar junction transistor | |
US10446644B2 (en) | Device structures for a silicon-on-insulator substrate with a high-resistance handle wafer | |
US10211090B2 (en) | Transistor with an airgap for reduced base-emitter capacitance and method of forming the transistor | |
CN106257629B (en) | The bipolar junction transistor referred to biconial emitter | |
US9608096B1 (en) | Implementing stress in a bipolar junction transistor | |
US10134880B2 (en) | Self-aligned bipolar junction transistors with a base grown in a dielectric cavity | |
US9356097B2 (en) | Method of forming a bipolar transistor with maskless self-aligned emitter | |
US11217685B2 (en) | Heterojunction bipolar transistor with marker layer | |
US11152467B2 (en) | Extrinsic base doping for bipolar junction transistors | |
US10170553B2 (en) | Shaped terminals for a bipolar junction transistor | |
US10217852B1 (en) | Heterojunction bipolar transistors with a controlled undercut formed beneath the extrinsic base | |
CN107026196B (en) | Bipolar junction transistor with extrinsic device region without trench isolation | |
TWI711117B (en) | Heterojunction bipolar transistors and method of forming the same | |
US10818772B2 (en) | Heterojunction bipolar transistors with an inverted crystalline boundary in the base layer | |
US11777019B2 (en) | Lateral heterojunction bipolar transistor with improved breakdown voltage and method | |
US20210066474A1 (en) | Self-aligned base and emitter for a bipolar junction transistor | |
CN115799327A (en) | Bipolar junction transistor including a portion of a base layer inside a cavity of a dielectric layer | |
CN116314305A (en) | Lateral bipolar junction transistor including stress layer and method |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
AS | Assignment |
Owner name: INTERNATIONAL BUSINESS MACHINES CORPORATION, NEW Y Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:CAMILLO-CASTILLO, RENATA;LIU, QIZHI;PEKARIK, JOHN J.;REEL/FRAME:035884/0329 Effective date: 20150622 |
|
AS | Assignment |
Owner name: GLOBALFOUNDRIES U.S. 2 LLC, NEW YORK Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:INTERNATIONAL BUSINESS MACHINES CORPORATION;REEL/FRAME:037409/0869 Effective date: 20151028 |
|
AS | Assignment |
Owner name: GLOBALFOUNDRIES INC., CAYMAN ISLANDS Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:GLOBALFOUNDRIES U.S. 2 LLC;GLOBALFOUNDRIES U.S. INC.;SIGNING DATES FROM 20151208 TO 20151214;REEL/FRAME:037542/0087 |
|
STCB | Information on status: application discontinuation |
Free format text: ABANDONED -- FAILURE TO RESPOND TO AN OFFICE ACTION |
|
AS | Assignment |
Owner name: GLOBALFOUNDRIES U.S. INC., NEW YORK Free format text: RELEASE BY SECURED PARTY;ASSIGNOR:WILMINGTON TRUST, NATIONAL ASSOCIATION;REEL/FRAME:056987/0001 Effective date: 20201117 |