KR850003641A - 샘플신호의 절사오차의 보상방법 및 장치 - Google Patents

샘플신호의 절사오차의 보상방법 및 장치 Download PDF

Info

Publication number
KR850003641A
KR850003641A KR1019840006773A KR840006773A KR850003641A KR 850003641 A KR850003641 A KR 850003641A KR 1019840006773 A KR1019840006773 A KR 1019840006773A KR 840006773 A KR840006773 A KR 840006773A KR 850003641 A KR850003641 A KR 850003641A
Authority
KR
South Korea
Prior art keywords
signal
compensating
negative
truncation
digital
Prior art date
Application number
KR1019840006773A
Other languages
English (en)
Other versions
KR900008410B1 (ko
Inventor
에리크 다알그비스트 잉게마르 (외 1)
Original Assignee
얀 스텐베르그, 벵트 겜스토오프
테레포오낙티이에보라겟트 엘엠 엘리크썬
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 얀 스텐베르그, 벵트 겜스토오프, 테레포오낙티이에보라겟트 엘엠 엘리크썬 filed Critical 얀 스텐베르그, 벵트 겜스토오프
Publication of KR850003641A publication Critical patent/KR850003641A/ko
Application granted granted Critical
Publication of KR900008410B1 publication Critical patent/KR900008410B1/ko

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/06—Arrangements for sorting, selecting, merging, or comparing data on individual record carriers
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
    • H03H17/00—Networks using digital techniques
    • H03H17/02—Frequency selective networks
    • H03H17/0219—Compensation of undesirable effects, e.g. quantisation noise, overflow
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
    • H03H17/00—Networks using digital techniques
    • H03H17/02—Frequency selective networks
    • H03H17/04—Recursive filters
    • H03H17/0461—Quantisation; Rounding; Truncation; Overflow oscillations or limit cycles eliminating measures
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/499—Denomination or exception handling, e.g. rounding or overflow
    • G06F7/49942—Significance control
    • G06F7/49947—Rounding
    • G06F7/49984—Rounding away from zero

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Mathematical Physics (AREA)
  • General Engineering & Computer Science (AREA)
  • Mathematical Optimization (AREA)
  • Pure & Applied Mathematics (AREA)
  • Mathematical Analysis (AREA)
  • Computing Systems (AREA)
  • Computational Mathematics (AREA)
  • Analogue/Digital Conversion (AREA)
  • Dc Digital Transmission (AREA)
  • Detection And Prevention Of Errors In Transmission (AREA)
  • Interface Circuits In Exchanges (AREA)
  • Transmission Systems Not Characterized By The Medium Used For Transmission (AREA)
  • Complex Calculations (AREA)
  • Noise Elimination (AREA)
  • Radar Systems Or Details Thereof (AREA)
  • Electronic Switches (AREA)
  • Reduction Or Emphasis Of Bandwidth Of Signals (AREA)
  • Facsimile Image Signal Circuits (AREA)
  • Digital Transmission Methods That Use Modulated Carrier Waves (AREA)
  • Optical Communication System (AREA)
  • Cable Transmission Systems, Equalization Of Radio And Reduction Of Echo (AREA)
  • Error Detection And Correction (AREA)
  • Data Exchanges In Wide-Area Networks (AREA)
  • Apparatus For Radiation Diagnosis (AREA)
  • Analysing Materials By The Use Of Radiation (AREA)

Abstract

내용 없음

Description

샘플신호의 절사오차의 보상방법 및 장치
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제4도 및 제5도는 본 발명에 따른 방법을 표시하게 기도된 제1도 및 제2도의 도표에 대응하는 도표. 제6도는 본 발명에 따른 방법의 생각할 수 있는 실현의 블록도.

Claims (4)

  1. 신호가 주어진 영 레벨에 대하여 정 또는 부로 되어있는 주어진 비트의 수를 가진 디지틀신호로, 디지틀필터에서 절사 특히 절대치 절사가 일어나는 오차에 대한 보상방법에 있어서, 신호가 정일 때 정의 제1의 치(et)가 그 신호에 가해지고, 이 치는 평균절사오차에 대응하고, 신호가 부일 때 부의 제2의 치가 그 신호에 가해지는 것을 특징으로 하는 생플신호의 절사오차의 보상방법.
  2. 제1항에 있어서, 상기 제1 및 제2의 치(+et및 -et)는 양이 같은 것.
  3. 제1 및 제2항에 있어서, 상기 치는 디지틀신호가 영일 때 디지틀신호에 가해지지 않는 것.
  4. 제1항 내지 제3항에 따른 방법을 수행하기 위한 장치에 있어서, 기억하는 기억유닛(3)을 가지고, 그의 양출력이 제1의 정 및 제2의 부의 치(+et및 -et)를 송신하고, 디지틀필터(1)에 적용되는 샘플신호의 극성을 감지하기 위한 감지유닛(4)과 가산회로(2)의 제1입력에 연결되는 스위칭유닛(5)을 가지고 가산회로의 제2 입력이 상기 신호를 수신하고, 그의 출력이 필터(1)의 입력에 연결되는 것을 특징으로 하는 샘플신호의 절사오차의 보상장치.
    ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.
KR1019840006773A 1983-11-24 1984-10-30 샘플 신호의 절단오차의 보상방법 및 장치 KR900008410B1 (ko)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
SE8306483-2 1983-11-24
SE8306483A SE440300B (sv) 1983-11-24 1983-11-24 Forfarande for att i en samplad signal kompensera for trunkeringsfel samt anordning for utforande av forfarandet

Publications (2)

Publication Number Publication Date
KR850003641A true KR850003641A (ko) 1985-06-20
KR900008410B1 KR900008410B1 (ko) 1990-11-20

Family

ID=20353446

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019840006773A KR900008410B1 (ko) 1983-11-24 1984-10-30 샘플 신호의 절단오차의 보상방법 및 장치

Country Status (22)

Country Link
US (1) US4750146A (ko)
EP (1) EP0162076B1 (ko)
KR (1) KR900008410B1 (ko)
AT (1) ATE30653T1 (ko)
AU (1) AU569928B2 (ko)
BR (1) BR8407181A (ko)
CA (1) CA1248603A (ko)
DE (1) DE3467275D1 (ko)
DK (1) DK162868C (ko)
ES (1) ES8601596A1 (ko)
FI (1) FI82795C (ko)
GR (1) GR80983B (ko)
IE (1) IE55857B1 (ko)
IN (1) IN161619B (ko)
IT (1) IT1177290B (ko)
MX (1) MX156872A (ko)
MY (1) MY100565A (ko)
NO (1) NO167348C (ko)
PT (1) PT79474B (ko)
SE (1) SE440300B (ko)
WO (1) WO1985002508A1 (ko)
YU (1) YU45678B (ko)

Families Citing this family (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH01169627A (ja) * 1987-12-25 1989-07-04 Toshiba Corp 高精度加算装置
JP2957183B2 (ja) * 1988-07-29 1999-10-04 日本電気株式会社 巡回型ディジタルフィルタ
JP3199371B2 (ja) * 1990-07-30 2001-08-20 松下電器産業株式会社 丸め装置
JPH04332215A (ja) * 1991-05-08 1992-11-19 Matsushita Electric Ind Co Ltd オフセット除去装置
JP3103914B2 (ja) * 1992-08-21 2000-10-30 ソニー株式会社 データの丸め処理回路およびデータの復元回路
US5493343A (en) * 1994-12-28 1996-02-20 Thomson Consumer Electronics, Inc. Compensation for truncation error in a digital video signal decoder
US5696710A (en) * 1995-12-29 1997-12-09 Thomson Consumer Electronics, Inc. Apparatus for symmetrically reducing N least significant bits of an M-bit digital signal
US6240431B1 (en) * 1998-10-31 2001-05-29 Hewlett-Packard Company Decompression of limited range floating point numbers
US6253222B1 (en) * 1998-10-31 2001-06-26 Hewlett-Packard Company Compression of limited range floating point numbers
US6401107B1 (en) * 1999-11-03 2002-06-04 Motorola, Inc. Method and processor for reducing computational error in a processor having no rounding support
US9450601B1 (en) 2015-04-02 2016-09-20 Microsoft Technology Licensing, Llc Continuous rounding of differing bit lengths

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3891837A (en) * 1972-07-03 1975-06-24 Drew E Sunstein Digital linearity and bias error compensating by adding an extra bit
US4195350A (en) * 1978-06-19 1980-03-25 Cbs Inc. Method and apparatus for eliminating deadband in digital recursive filters
US4282581A (en) * 1979-10-15 1981-08-04 Sperry Corporation Automatic overflow/imminent overflow detector
US4280196A (en) * 1979-11-14 1981-07-21 Hewlett-Packard Company Correction of zero drift, gain drift, and distortion errors in analog storage devices
US4589084A (en) * 1983-05-16 1986-05-13 Rca Corporation Apparatus for symmetrically truncating two's complement binary signals as for use with interleaved quadrature signals

Also Published As

Publication number Publication date
DK335385D0 (da) 1985-07-23
NO167348C (no) 1991-10-23
IT1177290B (it) 1987-08-26
DE3467275D1 (en) 1987-12-10
IT8423695A1 (it) 1986-05-22
MX156872A (es) 1988-10-06
PT79474B (en) 1986-08-05
IN161619B (ko) 1988-01-02
FI852458L (fi) 1985-06-20
GR80983B (en) 1984-11-29
AU569928B2 (en) 1988-02-25
IE842975L (en) 1985-05-24
WO1985002508A1 (en) 1985-06-06
EP0162076A1 (en) 1985-11-27
YU45678B (sh) 1992-07-20
US4750146A (en) 1988-06-07
SE8306483D0 (sv) 1983-11-24
NO854118L (no) 1985-10-24
CA1248603A (en) 1989-01-10
DK162868B (da) 1991-12-16
KR900008410B1 (ko) 1990-11-20
SE440300B (sv) 1985-07-22
EP0162076B1 (en) 1987-11-04
FI82795C (sv) 1991-04-10
ATE30653T1 (de) 1987-11-15
DK162868C (da) 1992-05-04
SE8306483L (sv) 1985-05-25
MY100565A (en) 1990-11-15
FI82795B (fi) 1990-12-31
BR8407181A (pt) 1985-11-05
ES537892A0 (es) 1985-10-16
PT79474A (en) 1984-12-01
YU197584A (en) 1987-10-31
IE55857B1 (en) 1991-01-30
FI852458A0 (fi) 1985-06-20
AU3613184A (en) 1985-06-13
ES8601596A1 (es) 1985-10-16
NO167348B (no) 1991-07-15
DK335385A (da) 1985-07-23
IT8423695A0 (it) 1984-11-22

Similar Documents

Publication Publication Date Title
Temme Uniform asymptotic expansions of the incomplete gamma functions and the incomplete beta function
KR830008558A (ko) 파형변환회로(波形變換回路)
KR830007002A (ko) 디지탈 신호 처리장치
KR850003641A (ko) 샘플신호의 절사오차의 보상방법 및 장치
KR880011803A (ko) 메모리 장치
KR830007001A (ko) 디지탈 신호 처리장치
KR910017881A (ko) 디지탈 보간 회로
KR850004838A (ko) 신호 검출장치
KR900015024A (ko) 상관연산장치
KR860004349A (ko) 시이퀀스 제어기의 프로세스 입출력장치
KR840001410A (ko) 프로그램 가능 논리장치
KR890012220A (ko) 부호변환회로
KR920015738A (ko) 가산회로
KR910005570A (ko) 프로그래머블 서브프레임 방식의 pwm회로
KR830008221A (ko) 수치제어장치
KR840002797A (ko) 신호처리용 다단접속된 rom
KR970055599A (ko) 전송 데이타 정형 장치
KR970022805A (ko) 로그의 근사값 계산방법 및 회로
KR870006716A (ko) 디지탈 레벨 검출 회로
KR920003769A (ko) 서라운드 제어회로
RU2001107011A (ru) Способ и устройство для сжатия сигналов в формате с фиксированной запятой без введения смещения
KR840006090A (ko) 제 산 회 로
KR890015602A (ko) 자기 기록 장치
KR900016857A (ko) 클리어 블루회로
KR860002212A (ko) 디지탈 비디오 신호 지연장치

Legal Events

Date Code Title Description
A201 Request for examination
E902 Notification of reason for refusal
E902 Notification of reason for refusal
G160 Decision to publish patent application
E701 Decision to grant or registration of patent right
GRNT Written decision to grant
FPAY Annual fee payment

Payment date: 19970812

Year of fee payment: 10

LAPS Lapse due to unpaid annual fee