KR850001097B1 - Semiconductor manufacturing method - Google Patents

Semiconductor manufacturing method Download PDF

Info

Publication number
KR850001097B1
KR850001097B1 KR1019830000047A KR830000047A KR850001097B1 KR 850001097 B1 KR850001097 B1 KR 850001097B1 KR 1019830000047 A KR1019830000047 A KR 1019830000047A KR 830000047 A KR830000047 A KR 830000047A KR 850001097 B1 KR850001097 B1 KR 850001097B1
Authority
KR
South Korea
Prior art keywords
thin film
polycrystalline silicon
diffusion
layer
emitter
Prior art date
Application number
KR1019830000047A
Other languages
Korean (ko)
Other versions
KR840003532A (en
Inventor
지유철
이용군
Original Assignee
한국전자 주식회사
정세능
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 한국전자 주식회사, 정세능 filed Critical 한국전자 주식회사
Priority to KR1019830000047A priority Critical patent/KR850001097B1/en
Publication of KR840003532A publication Critical patent/KR840003532A/en
Application granted granted Critical
Publication of KR850001097B1 publication Critical patent/KR850001097B1/en

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/22—Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities

Abstract

POCL3 is doped onto a polycrystalline silicon layer (3), into which an impurity is injected to form a resisting layer. Simultaneously, the impurity of the polycrystalline silicon layer is diffused to form an emitter region (4). The P2O5 layer on the silicon layer is removed, and metallic electrodes (6) are placed to manufacture a semiconducting, high-frequency element.

Description

고주파 반도체 소자의 제조방법Manufacturing method of high frequency semiconductor device

제1(a)도,제1도(b)도는 본 발명에 의한 반도체소자의 계략도 및 단면도.1 (a) and 1 (b) are schematic and cross-sectional views of a semiconductor device according to the present invention.

제2도는 일반적인 고주파용 반도체 소자의 단면도.2 is a cross-sectional view of a general high frequency semiconductor device.

제3도는 다결정 규소박막을 이용한 종래이 반도체 소자 단면예시도.3 is a cross-sectional view of a conventional semiconductor device using a polycrystalline silicon thin film.

제4도는 불순물을 주입한 다결정 규소박막을 이용한 반도체소자의 단면 예시도.4 is a cross-sectional view of a semiconductor device using a polycrystalline silicon thin film implanted with impurities.

제5(a)도-제5(d)는 본 발명의 제조방법을 설명하기 위한 예시도.5 (a) to 5 (d) is an exemplary view for explaining the manufacturing method of the present invention.

본 발명은 불순믈이 주입된 다결정규소박막을 확산원으로 사용한 고주파용 반도체소자의 제조방법에 관한 것이다.The present invention relates to a method for manufacturing a high frequency semiconductor device using a polysilicon thin film implanted with impurities as a diffusion source.

반도체의 주파수 특성은 확산깊이가 얇을수록 양호해지나 전극형성용 금속박막과 반도체간 열융착시 금속침투(Metal spike) 현상이 발생하여 서로 다른 전극간에 단락이 생기는데 이의 방지를 위해 다결정규소박막을 전극용금속 박막과 반도체 사이에 도포시키는 것이 일반적이다.The thinner the diffusion depth is, the better the frequency characteristics of the semiconductor become, but the metal spike phenomenon occurs during thermal fusion between the electrode thin film and the semiconductor to form a short circuit between the different electrodes. It is common to apply between a molten metal thin film and a semiconductor.

본 발명은 전극간의 단락방지로 사용되는 다결정 규소박막 형성시에 에미터 확산용 불순물을 주입시켜 이것을 반도체장치의 에미터 영역 형성물질로 사용되는 다결정 규소박막에 불순물을 주입시켜 금속과다결정 규소간접저항을 낮춰주어 초고주파 특성의 반도체 장치를 실현할 수 있는 방법이다.In the present invention, an impurity for emitter diffusion is implanted when forming a polycrystalline silicon thin film used for short-circuit prevention between electrodes, and an impurity is implanted into a polycrystalline silicon thin film used as an emitter region forming material of a semiconductor device. It is possible to realize a semiconductor device with ultra-high frequency characteristics by lowering the voltage.

N형 클렉터(1)에 사진 식각법을 사용하여 베이스 확산창을 열고 P형의 베이스 불순물(붕소)을 열확산시키면 베이스(2)가 형성된다.The base 2 is formed by opening a base diffusion window on the N-type selector 1 by thermal diffusion of a base type impurity (boron) of P type.

이때 확산 깊이는 고주파 특성을 내기위해서 10,000도A 미만으로 해야한다.At this time, the depth of diffusion should be less than 10,000 degrees A for high frequency characteristics.

제1도는 베이스(2)위에 에미터(4)용 확산창을 만들어 에메터용 불순물을 베이스 확산 깊이의 1/2정도로 열확산시킨 다음 전극용 금속과 베이스, 에미터의 전기적 접합을 위해 창을 열어 전극을 형성시킨 것을 보여준 것이다. (6). 전극금속과 반도체간 접촉저항은 반도체 특성의 중요한 요소로서 이의 최소화는 필수조건이다. 이를 위해 보통은 450-500도 C에서 열처리를 하여 반도체와 금속간 합금을 시키는데, 제2도는 전극 금속이 수천 Å 깊이의 에미터(4) 확산층을 지나 베이스(2)와 단락되어버린 경우(8)를 나타낸 것을 보여준 것이다.1 shows a diffusion window for the emitter 4 on the base 2, thermally diffuses the impurities for the emitter to about half the depth of the base diffusion, and then opens the window for electrical bonding between the electrode metal and the base and emitter. To show that formed. (6). The contact resistance between the electrode metal and the semiconductor is an important element of the semiconductor characteristics, and minimization thereof is an essential condition. To this end, heat treatment is usually performed at 450-500 degrees C to form an alloy between the semiconductor and the metal. In FIG. 2, when the electrode metal is shorted with the base 2 through the emitter 4 diffusion layer having a depth of several thousand Å (8) ) Is shown.

제3도는 전극금속과 단락을 방지하기 위하여 얇고 순수한 다결정 규소박막(9)을 전극금속(6)과 반도체 에미터(4) 사이에 도포하여 금속침투 방지층으로 사용한 종래 반도체 소자의 단면이다.3 is a cross-sectional view of a conventional semiconductor device in which a thin and pure polycrystalline silicon thin film 9 is applied between the electrode metal 6 and the semiconductor emitter 4 and used as a metal penetration prevention layer in order to prevent a short circuit.

이러한 방법은 에미터까지 열확산법으로 형성시킨후 저 압기상성장법(LP.CVD)에 의해 다결정 규소박막을 입히고 사진 식각법에 의해 금속전극 접촉 부위만 남기고 제거시킨후 금속증착을 하고 열처리를 통해 제조되므로 초고주파용에 실제로 많이 사용되고 있으나 순수한 다결정 규소박막은 거의 부도체(insulator)에 가까워 금속전극과 합금을 시켜도 접촉저항이 너무 높은 단점이 있다.This method is formed by thermal diffusion method up to the emitter, and then a polycrystalline silicon thin film is deposited by low pressure vapor phase growth (LP.CVD), and only the metal electrode contact area is removed by photolithography, followed by metal deposition and heat treatment. Because it is manufactured, it is actually widely used for ultra-high frequency, but pure polycrystalline silicon thin film is almost insulator, so there is a disadvantage that the contact resistance is too high even when alloyed with a metal electrode.

제4도는 제3도의 방법을 개산하여 콜랙터(1)에 베이스(2)를 형성시킨 다음 에미터용 차을 먼저 열고 저압기상 성장법(LP.CVD)에 의해 불순물을 주입시킨 다결정 규소박막(3)을 3,000-5,000Å 입힌 다음 사진식각법에 의해 에미터 부분만 남기고 막을 제거시키고 확산을 시키면(4)가 다음식의 형태로 확산된다.4 is a polycrystalline silicon thin film 3 in which a base 2 is formed in the collector 1 by estimating the method of FIG. After coating 3,000-5,000 다음, the film is removed and diffused (4), leaving only the emitter portion by photolithography.

Figure kpo00002
Figure kpo00002

N0=다결정 규소박막 내의 불순물 농N 0 = concentration of impurities in the polycrystalline silicon thin film

D1=다결정 규소박막 내의 확산계수도D 1 = Diffusion coefficient in polycrystalline silicon thin film

D2=반도체규소 기판증의 확산계수D 2 = Diffusion Coefficient of Semiconductor Silicon Substrate

k=편석계수=

Figure kpo00003
k = segregation coefficient
Figure kpo00003

환산을 한 다결정 규소박막위에 전극용 금속을 도포(6)시키고 열처리를 하면 전극용 금속(6)과 불순물 주입다결정규소 박막(3) 사이에 합금이 일어나고 확산된 에미터에 전혀 손상을 입히지 않게되어 신뢰성이 우수해지나 불순물주입 다결정규소(6)의 두께가 부위마다 일정하게 유지되지 않고 열처리 온도의 불륜일성과 높은 저항을 갖는 다결정규소와 합금되지 않고 남은 부분때문에 부위마다 다르게 되어 제2도의 경우보다 접촉저항이 크게 나타난다.When the electrode metal is applied (6) on the converted polycrystalline silicon thin film and heat-treated, an alloy is formed between the electrode metal (6) and the impurity-injected polysilicon thin film (3) and no damage is caused to the diffused emitter at all. Although the reliability is excellent, the thickness of the impurity-injected polysilicon 6 is not kept constant from site to site, and is not alloyed with polycrystalline silicon having unevenness in heat treatment temperature and high resistance. Contact resistance is large.

여기서 본 발명은 이런한 접촉저항을 개선하기 위하여 에미터(4) 확산형성시 불순물을 주입한 다결정 규소위에 Pmcl3를 도포시켜서 다결정규소의 표면농도를 1021atom/cm3이상이 되게하여 이 위에 전극용 금속을 합금시켜 다결정규소층의 접촉저항이 훨씬 줄어들게 하였다.In order to improve such contact resistance, the present invention applies Pmcl 3 to polycrystalline silicon implanted with impurities during diffusion formation of the emitter 4 so that the surface concentration of polycrystalline silicon becomes 10 21 atom / cm 3 or more. The metal for the electrode was alloyed to reduce the contact resistance of the polysilicon layer even further.

제5(a)도-제5(d)는 본 발명의 실시예이다.5 (a) to 5 (d) are embodiments of the present invention.

제1공정1st process

제5(a)도는 n형의 애피탁샬규소기판(Epitaxial Sillicon Wafer)을 콜랙터(1)로 해서 P형불순물(붕소)을 확산시켜 베이스(2)를 형성한다.In FIG. 5 (a), the base 2 is formed by diffusing a P-type impurity (boron) using an n-type epitaxial silicon substrate (Epitaxial Sillicon Wafer) as the collector 1.

제2공정2nd process

제5(b)도는 에미터 확산원겸 금속합금층으로 사용되는 불순물이 주입된 다결정 규소(3)를 형성시킨 공정이다. 이때 5,000도C 정도의 다결정 규소박막을 저압기상 성장법(LP.CVD)에 의해서 형성하며, 확산이 진행되지 않는 700도C 정도에서 실판(SiH4)을 열분해하여 얻을 수 있다.FIG. 5 (b) is a step in which the polycrystalline silicon 3 into which the impurity used as an emitter diffusion source and a metal alloy layer was implanted was formed. In this case, a polysilicon thin film of about 5,000 ° C. is formed by low pressure vapor phase growth (LP.CVD), and it can be obtained by thermal decomposition of the plate (SiH 4 ) at about 700 ° C. where diffusion does not proceed.

불순물은 인(P)과 비소(As)를 사용할 수 있으나 비소(As)쪽이 다결정 규소박막의 균일성 면에서 3배 이상 질이 좋고 비교적 저온인 1,000도 C에서도 높은 표면농도를 얻을 수 있으며 확산속도가 느려 열처리 공정이 씌워진다.As impurities, phosphorus (P) and arsenic (As) may be used, but arsenic (As) is more than three times better in terms of uniformity of polysilicon thin film, and high surface concentration can be obtained even at a relatively low temperature of 1,000 degrees C. The speed is slow and the heat treatment process is covered.

제3공정3rd process

제5(c)도는 1,000도C의 온도에서 불순물이 주입된 다결정 규소박막(3) 위에 5-20도C의 Pocl3용액을 N2캐리어(Carrier)개스와 함께 보내 산소(O4)와 혼합시켜 반도체 표면에 도포시키므로 불순물주입 다결정 규소박막의 표면농도를 1021atam/cm3이상으로 만들어 주면서 다결정 규수박막내의 불순물으 베이스(2)영역에 확산시켜 에미터(4)를 형성시키는 공정이며 반도체 표면은 고농도의 P2O5층(5)이 생긴다.FIG. 5 (c) shows the Pocl 3 solution of 5-20 ° C. together with the N 2 carrier gas and mixed with oxygen (O 4 ) on the polycrystalline silicon thin film 3 impurity implanted at a temperature of 1,000 ° C. It is applied to the surface of the semiconductor, so that the surface concentration of the impurity-injected polycrystalline silicon thin film is 10 21 atam / cm 3 or more, while the emitter 4 is formed by diffusing impurities in the polycrystalline silicon thin film into the base 2 region. The surface has a high concentration of P 2 O 5 layer (5).

제4공정4th process

제5(d)도는 제3공정이 Pocl3도포시 형성된 P2O5층(5)을 불화수소계(HF계) 용액으로 제거하고 금속 알루미늄 2㎛ 정도 증착시킨후 사진식각법에 의해 금속전극(6)을 형성하고 450-500도C의 열처리를함으로서 Pocl3도포에 의해 고농도의 표면농도가된 다결정 규소층(7)과 알루미늄을 합금시켜 본 발명의 반도체 소자를 얻는다.FIG. 5 (d) shows that the P 2 O 5 layer (5) formed during the Pocl 3 coating is removed with a hydrogen fluoride (HF) solution, deposited with a thickness of about 2 μm of metal aluminum, and the metal electrode is subjected to photolithography. (6) was formed and a heat treatment was performed at 450-500 ° C. to obtain a semiconductor device of the present invention by alloying aluminum with polycrystalline silicon layer 7 having a high surface concentration by Pocl 3 coating.

Claims (1)

본문에 상술하고 도면에 예시된 바와 같은 불순물이 즈입된 다결정 규소박막(3)위에 Pocl3을 도포시켜 저저항층을 형성시킴과 동시에 다결정 규소박막(3)의 불순물을 확산시켜 에미터 영역(4)을 형성한 후 다결정 규소박막(3)위의 P2O5층을 제거하고 금속전극(6)을 형성시키는 고주파용 반도체소자의 제조방법.Applying Pocl 3 to the polysilicon thin film 3 containing the impurities described above and illustrated in the figure to form a low resistance layer, and at the same time to diffuse the impurities of the polysilicon thin film 3 emitter region (4) A method for manufacturing a high frequency semiconductor device in which a P 2 O 5 layer on a polysilicon thin film (3) is removed and a metal electrode (6) is formed after the formation of the P-O.
KR1019830000047A 1983-01-07 1983-01-07 Semiconductor manufacturing method KR850001097B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019830000047A KR850001097B1 (en) 1983-01-07 1983-01-07 Semiconductor manufacturing method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019830000047A KR850001097B1 (en) 1983-01-07 1983-01-07 Semiconductor manufacturing method

Publications (2)

Publication Number Publication Date
KR840003532A KR840003532A (en) 1984-09-08
KR850001097B1 true KR850001097B1 (en) 1985-07-27

Family

ID=19227977

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019830000047A KR850001097B1 (en) 1983-01-07 1983-01-07 Semiconductor manufacturing method

Country Status (1)

Country Link
KR (1) KR850001097B1 (en)

Also Published As

Publication number Publication date
KR840003532A (en) 1984-09-08

Similar Documents

Publication Publication Date Title
US5103285A (en) Silicon carbide barrier between silicon substrate and metal layer
CA1050667A (en) Method of manufacturing semiconductor devices
Theunissen et al. Application of preferential electrochemical etching of silicon to semiconductor device technology
US4791074A (en) Method of manufacturing a semiconductor apparatus
US4290830A (en) Method of selectively diffusing aluminium into a silicon semiconductor substrate
US3753803A (en) Method of dividing semiconductor layer into a plurality of isolated regions
US4351677A (en) Method of manufacturing semiconductor device having aluminum diffused semiconductor substrate
EP0042698A2 (en) Semiconductor device
US4001873A (en) Semiconductor device
US6146947A (en) Insulated gate type field effect transistor and method of manufacturing the same
US4050967A (en) Method of selective aluminum diffusion
KR850001097B1 (en) Semiconductor manufacturing method
JPS6133253B2 (en)
EP0219243A2 (en) Process of manufacturing a bipolar transistor
US4725564A (en) Method of manufacturing a semiconductor device, in which a dopant is diffused from its oxide into a semiconductor body
JP2816684B2 (en) Manufacturing method of multiple diodes
JPS59108325A (en) Manufacture of semiconductor device
JPS61102059A (en) Semiconductor device
JPS5917529B2 (en) Manufacturing method of semiconductor device
GB2126419A (en) Materials for MOS device gate electrodes
KR940004257B1 (en) Manufacturing method of bipolar transistor
JPS6298721A (en) Zn solid-state diffusing method for iii-v compound semiconductor
RU845678C (en) Method of manufacturing hf p- &&& -p transistors
JPS5916417B2 (en) Manufacturing method of semiconductor device
JPH0137856B2 (en)

Legal Events

Date Code Title Description
A201 Request for examination
E902 Notification of reason for refusal
E902 Notification of reason for refusal
G160 Decision to publish patent application
E701 Decision to grant or registration of patent right
GRNT Written decision to grant
FPAY Annual fee payment

Payment date: 19910822

Year of fee payment: 12

LAPS Lapse due to unpaid annual fee