JPS59108325A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPS59108325A JPS59108325A JP21901582A JP21901582A JPS59108325A JP S59108325 A JPS59108325 A JP S59108325A JP 21901582 A JP21901582 A JP 21901582A JP 21901582 A JP21901582 A JP 21901582A JP S59108325 A JPS59108325 A JP S59108325A
- Authority
- JP
- Japan
- Prior art keywords
- layer
- groove
- semiconductor layer
- film
- etching
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/763—Polycrystalline semiconductor regions
Landscapes
- Engineering & Computer Science (AREA)
- Chemical & Material Sciences (AREA)
- Crystallography & Structural Chemistry (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Element Separation (AREA)
Abstract
Description
【発明の詳細な説明】
（ａ） 発明の技術分野
本発明は半導体装置の製造方法にかかり、特に素子分離
領域の改善された形成方法に関する。DETAILED DESCRIPTION OF THE INVENTION (a) Technical Field of the Invention The present invention relates to a method of manufacturing a semiconductor device, and more particularly to an improved method of forming an element isolation region.
山） 従来技術と問題点
半導体集積回路（ＩＣ）においては、半導体基板上に多
数の回路素子が設けられており、これらの回路素子をお
互いに電気的に絶縁するために素子間を分離する素子分
離領域の形成が必要である。Prior Art and Problems In a semiconductor integrated circuit (IC), a large number of circuit elements are provided on a semiconductor substrate, and in order to electrically insulate these circuit elements from each other, an element is used to separate the elements. Formation of isolation regions is necessary.
このような素子分離領域の形成方法には色々の方法があ
るが、最近広く用いられている方法に■ＯＰ （Ｉ
ｓｏｌａｔｉｏｎ ｗｉｔｈ ０ｘｉｄｅ
ａｎｄ Ｐｏ１ｙｓｉｌｉｃｏｎ）法がある。それは
エツチングして溝を形成し、その溝内に二酸化シリコン
（ＳｉＯ２） １１１１’を介して多結晶シリコン膜を
堆積し、その上面に二酸化シリコン膜を形成する方法で
、第１図にその断面構造例を示している。図において、
■はＰ型半導体基板、２はＮ＋型半導体Ｍ（これはバイ
ポーラ形半導体装置を形成する場合にコレクタ抵抗を減
少させる埋没層となるものである）、３はＮ型半導体層
、４は二酸化シリコン膜、５は多結晶シリコン膜である
。There are various methods for forming such element isolation regions, but one method that has been widely used recently is OP (I
Solation with Oxide
and Polysilicon) method. In this method, a trench is formed by etching, a polycrystalline silicon film is deposited in the trench via silicon dioxide (SiO2) 1111', and a silicon dioxide film is formed on the top surface. An example is shown. In the figure,
2 is a P-type semiconductor substrate, 2 is an N+-type semiconductor M (this is a buried layer that reduces collector resistance when forming a bipolar semiconductor device), 3 is an N-type semiconductor layer, and 4 is silicon dioxide. The film 5 is a polycrystalline silicon film.
このような■ＯＰ法において、初期にはエツチングの結
晶方位性を利用してウェットエツチングによりＶ形の溝
を形成する所謂Ｖ溝分離領域の形成法が採られていた。In the OP method, a so-called V-groove isolation region formation method was initially adopted in which a V-shaped groove is formed by wet etching using the crystal orientation of etching.
ところが、最近ドライエツチング法の発展と共に、ドラ
イエツチングでＵ形の溝を形成する所ｆｉｔｒＵ溝分離
領域の形成法が汎用化されている。それは、Ｕ形溝がＶ
形溝よりも−屓小さく形成できてＩＣの高築積化に極め
て有効であるからで、第１図はそのＵｍ溝の断面構造図
例である。However, with the recent development of the dry etching method, a method for forming a fitrU groove isolation region, in which a U-shaped groove is formed by dry etching, has become widely used. It is because the U-shaped groove is V
This is because it can be formed to be smaller than a Um groove and is extremely effective in increasing the stacking capacity of ICs. FIG. 1 is an example of the cross-sectional structure of the Um groove.
しかしながら、このようなＩＯＰ法による素子分離領域
はＵ形溝、Ｖ形溝のいづれにしても二酸化シリコン膜４
を介在させるため、電位がかかると分離領域直下の半導
体基板にチャネルが生じやすい。また、第１図に示すよ
うにＮ＋型型半体体層２形成する場合、これは高濃度層
であるから次工程でＮ型半導体層３を高温度で成長する
際に、Ｐ型半導体基板１にＮ型不純物が拡散して、半導
体基板１まで達する一定深さのＵ形溝を形成してもなお
その部分の半導体基板１はＮ型化していてチャネルがで
きており、素子間分離がなされない場合がある。一方、
そのために十分深くまでエツチング溝を形成することは
難しく、またその溝内を埋没させることも難しい。従っ
て、従来は予め溝部分の直下に半導体基板と同一導電型
不純物イオンを注入して高濃度不純物１ｉｉ６（第１図
参照）を形成し、チャネルカットをおこなっている。し
かし、このチャネルカット用高濃度不純物層６の形成は
それだけ余分の工程を必要とするするものである。また
、このような二酸化シリコンｌｌ１ｉ４を半導体結晶層
内に介在させれば、結晶内に大きなストレスが生じて結
晶欠陥を誘発しやすく、半導体装置の電気的特性に悪影
響を与える。However, the element isolation region formed by such an IOP method is formed using a silicon dioxide film 4 regardless of whether it is a U-shaped groove or a V-shaped groove.
Because of the intervening structure, a channel is likely to be formed in the semiconductor substrate directly under the isolation region when a potential is applied. In addition, when forming the N+ type half layer 2 as shown in FIG. 1, since this is a high concentration layer, when the N type semiconductor layer 3 is grown at high temperature in the next step, the P type semiconductor layer 2 is formed. Even if an N-type impurity is diffused into the semiconductor substrate 1 to form a U-shaped groove of a certain depth that reaches the semiconductor substrate 1, the semiconductor substrate 1 in that part is still N-type, forming a channel, and the isolation between elements is reduced. It may not be done. on the other hand,
Therefore, it is difficult to form an etching groove deep enough, and it is also difficult to bury the inside of the groove. Therefore, conventionally, impurity ions of the same conductivity type as the semiconductor substrate are implanted directly under the groove portion to form a high concentration impurity 1ii6 (see FIG. 1) to cut the channel. However, the formation of this high concentration impurity layer 6 for channel cutting requires an extra process. Further, if such silicon dioxide ll1i4 is interposed in a semiconductor crystal layer, a large stress is generated in the crystal, which tends to induce crystal defects, which adversely affects the electrical characteristics of the semiconductor device.
ｆｃｌ 発明の目的
本発明はこのような問題点を除去し、素子分離領域の形
成方法において二酸化シリコン膜を設けない分離領域の
形成方法をＩに案するものである。fcl OBJECT OF THE INVENTION The present invention eliminates these problems and proposes a method for forming an isolation region in which no silicon dioxide film is provided in the method for forming an element isolation region.
（ｄ）発明の構成
その目的は、−導電型半導体基板上に設けた反対導電型
半導体層に素子分離領域を形成する方法において、該半
導体層面に上記半導体基板に達する溝を形成し、該溝内
に一導電型多結晶半導体層を堆積して、更に該多結晶半
導体層の表面を酸化して絶縁膜を形成する工程が含まれ
る半導体装置の製造方法によって達成させることができ
る。(d) Structure of the Invention The object of the invention is to form a groove reaching the semiconductor substrate in a surface of the semiconductor layer in a method for forming an element isolation region in a semiconductor layer of an opposite conductivity type provided on a semiconductor substrate of a -conductivity type; This can be achieved by a method for manufacturing a semiconductor device that includes the steps of depositing a polycrystalline semiconductor layer of one conductivity type within the semiconductor layer, and further oxidizing the surface of the polycrystalline semiconductor layer to form an insulating film.
（８）発明の実施例 以下１図面を参照して実施例によって詳細に説明する。(8) Examples of the invention An embodiment will be described in detail below with reference to one drawing.
第２図ないし第６図は本発明による形成工程順断面図を
示しており、まず第２図に示すようにＰ型半導体基板１
１上に膜厚０．５μｍのＮ＋型型溝導体層１２膜厚１μ
ｍのＮ型半導体層１３をエピタキシャル成長した後、そ
の上に膜厚数１００人の二酸化シリコン膜１４と膜厚１
０００人の窒化シリコン膜１５との二重膜を選択的に形
成する。2 to 6 show sequential cross-sectional views of the formation process according to the present invention. First, as shown in FIG.
N+ type groove conductor layer 12 with a thickness of 0.5 μm on top of the layer 1 with a thickness of 1 μm
After epitaxially growing an N-type semiconductor layer 13 with a thickness of 1.0 m, a silicon dioxide film 14 with a thickness of several 100 layers and a silicon dioxide film 14 with a thickness of 1.
A double film with a silicon nitride film 15 of 1,000 yen is selectively formed.
次いで、第３図に示すように上記二重膜をマスクにして
ドライエツチングによって深さ２〜３μｍ９幅２μｍの
Ｕ形溝１６を形成する。このドライエンチングはトリフ
ロロメタン（ＣＨＦａ）と酸素（０２）との混合ガスを
用いたりアクティブイオンエツチング方法で、そのため
垂直なエツチング溝が形成される。また、溝の深さ２〜
３μｍは膜厚１μｍのＮ型半導体層１３と膜厚０．５μ
ｍのＮ＋型型溝導体層１２この半導体層１２は前記した
ように更に下層に拡散して厚さが１μｍ程度まで拡がる
ことが多い）とを突き抜けて、Ｐ型半導体基板１１に達
するに十分な深さである。Next, as shown in FIG. 3, a U-shaped groove 16 having a depth of 2 to 3 .mu.m and a width of 2 .mu.m is formed by dry etching using the double film as a mask. This dry etching uses a mixed gas of trifluoromethane (CHFa) and oxygen (02) or is an active ion etching method, thereby forming vertical etching grooves. Also, the depth of the groove is 2~
3 μm is an N-type semiconductor layer 13 with a thickness of 1 μm and a thickness of 0.5 μm.
m N+ type groove conductor layer 12 (as described above, this semiconductor layer 12 diffuses further into the lower layer and often expands to a thickness of about 1 μm) and reaches the P type semiconductor substrate 11. It's depth.
次いで、第４図に示すようにその上面に減圧気相成長法
によって硼素（Ｔ’（）を含んだ（Ｐ型）多結晶シリコ
ン屑１７を約２ｐｍの厚さに積層する。Next, as shown in FIG. 4, (P-type) polycrystalline silicon chips 17 containing boron (T'()) are deposited to a thickness of about 2 pm on the upper surface by low pressure vapor phase growth.
そうすると、Ｕ形溝１６内はこの多結晶シリコン層１７
で埋められる。次いで、第５図に示すように研磨または
エツチングによって窒化シリコン膜１５上の多結晶シリ
コンＭ１１を除去し、更にＵ形溝１６内の上部をも少し
エツチング除去して凹部を形成する。Then, inside the U-shaped groove 16 is this polycrystalline silicon layer 17.
It is filled with Next, as shown in FIG. 5, the polycrystalline silicon M11 on the silicon nitride film 15 is removed by polishing or etching, and the upper part of the U-shaped groove 16 is also slightly etched away to form a recess.
次いで、温度９００〜１０００℃のウェット酸素中、ま
たは高圧酸化性雰囲気中で熱酸化して多結晶シリコン層
１７上に数１０００人の二酸化シリコンＩ！ｇｉ！１８
を形成し、ＭＥ１多に膜厚１０００人の窒化シリコン膜
１５をエツチング除去して、第６図に示すように素子分
離領域が完成する。この際、多結晶シリコン膜１７が酸
化すれば、熱ｌ！１１１！シて二酸化シリコン膜１８に
なるから上記の凹部はなくなって表面が平坦化される。Next, several thousand silicon dioxide layers are formed on the polycrystalline silicon layer 17 by thermal oxidation in wet oxygen at a temperature of 900 to 1000° C. or in a high-pressure oxidizing atmosphere. Gi! 18
The silicon nitride film 15 having a thickness of 1,000 wafers is removed by etching on the ME1 layer, thereby completing an element isolation region as shown in FIG. At this time, if the polycrystalline silicon film 17 is oxidized, the heat l! 111! Since the silicon dioxide film 18 is formed, the above-mentioned recesses are eliminated and the surface is flattened.
このようにして形成すれば、溝内に二酸化シリコン膜が
存在しないため溝内のＰ型多結晶シリコン膜１７から半
導体基板１１に硼素（Ｐ型不純物）が拡散して、素子分
離領域下でのチャネル領域の発生が防止される。更に、
このようにすればエツチング溝の形成後、酸化して二酸
化シリコン膜４ （第１図参照）を形成する工程がなく
なるため、バーズビークの発生も小さくて高集積化に極
めて好都合となる。If formed in this manner, boron (P-type impurity) is diffused from the P-type polycrystalline silicon film 17 in the trench to the semiconductor substrate 11 because there is no silicon dioxide film in the trench, and the silicon dioxide film is not present in the trench. The generation of channel regions is prevented. Furthermore,
This eliminates the step of oxidizing and forming the silicon dioxide film 4 (see FIG. 1) after forming the etching grooves, so the occurrence of bird's beaks is also reduced, which is extremely convenient for high integration.
（ｆｌ 発明の効果
以上の説明から明らかなように、本発明によればチャネ
ルカット用高濃度不純物層のイオン注入工程と、二酸化
シリコン膜の酸化工程とを省くことができ、且つ二酸化
シリコン膜の介在によるストレスを取り除くことができ
るため、ＩＣ等の半導体装置の高性能、高品質化に°著
しく貢献するものである。(fl Effects of the Invention As is clear from the above explanation, according to the present invention, the ion implantation process of the high concentration impurity layer for channel cut and the oxidation process of the silicon dioxide film can be omitted, and the process of oxidizing the silicon dioxide film can be omitted. Since it is possible to remove the stress caused by interposition, it significantly contributes to improving the performance and quality of semiconductor devices such as ICs.
なお、本発明は上記例のＵ形溝のみならず、■形溝から
なる素子分離領域の形成にも適用できることは言うまで
もない。It goes without saying that the present invention can be applied not only to the U-shaped groove in the above example, but also to the formation of an element isolation region consisting of a ■-shaped groove.
第１図は従来の素子分離領域の構造断面図例。
第２図ないし第６図は本発明にかかる素子分離領域の形
成工程順断面図である。
図中、１．１１はＰ型半導体基板、２．１２はＮ＋型半
導体層、３．１３はＮ型半導体層、 ４． １４゜１
８は二酸化シリコン賎、５は多結晶シリコン膜。
６は高濃度不純物層、１５は窒化シリコン膜。FIG. 1 is an example of a structural cross-sectional view of a conventional element isolation region. FIGS. 2 to 6 are cross-sectional views in the order of steps for forming an element isolation region according to the present invention. In the figure, 1.11 is a P-type semiconductor substrate, 2.12 is an N+ type semiconductor layer, 3.13 is an N-type semiconductor layer, 4. 14°1
8 is a silicon dioxide layer, and 5 is a polycrystalline silicon film. 6 is a high concentration impurity layer, and 15 is a silicon nitride film.
Claims (1)
子分離領域を形成する方法において、該半導体層面に上
記半導体基板に達する溝を形成し、該溝内に一導電型多
結晶半導体層を堆積して、更に該多結晶半導体層の表面
を酸化して絶縁膜を形成する工程が含まれていることを
特徴とする半導体装置の製造方法。In a method for forming an element isolation region in a semiconductor layer of an opposite conductivity type provided on a semiconductor substrate of one conductivity type, a groove reaching the semiconductor substrate is formed in the surface of the semiconductor layer, and a polycrystalline semiconductor layer of one conductivity type is formed in the groove. A method for manufacturing a semiconductor device, comprising the steps of depositing the polycrystalline semiconductor layer and further oxidizing the surface of the polycrystalline semiconductor layer to form an insulating film.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP21901582A JPS59108325A (en) | 1982-12-13 | 1982-12-13 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP21901582A JPS59108325A (en) | 1982-12-13 | 1982-12-13 | Manufacture of semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS59108325A true JPS59108325A (en) | 1984-06-22 |
Family
ID=16728913
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP21901582A Pending JPS59108325A (en) | 1982-12-13 | 1982-12-13 | Manufacture of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS59108325A (en) |
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4767722A (en) * | 1986-03-24 | 1988-08-30 | Siliconix Incorporated | Method for making planar vertical channel DMOS structures |
| US4873203A (en) * | 1987-07-27 | 1989-10-10 | Hitachi, Ltd. | Method for formation of insulation film on silicon buried in trench |
| US5034785A (en) * | 1986-03-24 | 1991-07-23 | Siliconix Incorporated | Planar vertical channel DMOS structure |
| US5106777A (en) * | 1989-09-27 | 1992-04-21 | Texas Instruments Incorporated | Trench isolation process with reduced topography |
| US5290396A (en) * | 1991-06-06 | 1994-03-01 | Lsi Logic Corporation | Trench planarization techniques |
| US5312770A (en) * | 1991-06-06 | 1994-05-17 | Lsi Logic Corporation | Techniques for forming isolation structures |
| US5354706A (en) * | 1993-03-02 | 1994-10-11 | Lsi Logic Corporation | Formation of uniform dimension conductive lines on a semiconductor wafer |
-
1982
- 1982-12-13 JP JP21901582A patent/JPS59108325A/en active Pending
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4767722A (en) * | 1986-03-24 | 1988-08-30 | Siliconix Incorporated | Method for making planar vertical channel DMOS structures |
| US5034785A (en) * | 1986-03-24 | 1991-07-23 | Siliconix Incorporated | Planar vertical channel DMOS structure |
| US4873203A (en) * | 1987-07-27 | 1989-10-10 | Hitachi, Ltd. | Method for formation of insulation film on silicon buried in trench |
| US5106777A (en) * | 1989-09-27 | 1992-04-21 | Texas Instruments Incorporated | Trench isolation process with reduced topography |
| US5290396A (en) * | 1991-06-06 | 1994-03-01 | Lsi Logic Corporation | Trench planarization techniques |
| US5312770A (en) * | 1991-06-06 | 1994-05-17 | Lsi Logic Corporation | Techniques for forming isolation structures |
| US5354706A (en) * | 1993-03-02 | 1994-10-11 | Lsi Logic Corporation | Formation of uniform dimension conductive lines on a semiconductor wafer |
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