GB2126419A - Materials for MOS device gate electrodes - Google Patents

Materials for MOS device gate electrodes Download PDF

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Publication number
GB2126419A
GB2126419A GB08320459A GB8320459A GB2126419A GB 2126419 A GB2126419 A GB 2126419A GB 08320459 A GB08320459 A GB 08320459A GB 8320459 A GB8320459 A GB 8320459A GB 2126419 A GB2126419 A GB 2126419A
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Prior art keywords
transition metal
gate electrode
oxide film
impurity
semiconductor substrate
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GB08320459A
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GB2126419B (en
GB8320459D0 (en
Inventor
Shun-Ichi Hiraki
Yoshio Yokota
Kazuo Tsuru
Shigeo Yawata
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Toshiba Corp
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Tokyo Shibaura Electric Co Ltd
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Publication of GB8320459D0 publication Critical patent/GB8320459D0/en
Publication of GB2126419A publication Critical patent/GB2126419A/en
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Publication of GB2126419B publication Critical patent/GB2126419B/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26—Bombardment with radiation
    • H01L21/263—Bombardment with radiation with high-energy radiation
    • H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
    • H01L21/26506—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors
    • H01L21/26513—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors of electrically active species
    • H01L21/2652—Through-implantation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
    • H01L29/4966—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a composite material, e.g. organic material, TiN, MoSi2
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • High Energy & Nuclear Physics (AREA)
  • Ceramic Engineering (AREA)
  • Health & Medical Sciences (AREA)
  • Toxicology (AREA)
  • Manufacturing & Machinery (AREA)
  • Chemical & Material Sciences (AREA)
  • Composite Materials (AREA)
  • Materials Engineering (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Electrodes Of Semiconductors (AREA)

Abstract

The conductive gate electrode (16) of an MOS device comprises an interstitial transition metal nitride or carbide. The preferred metals are Ti, Hf, Zr, Ta, Nb, Sc and Mo. The gate electrode (16) is formed on a gate oxide film (10) and forms a mask for implanting ions through the gate oxide to form the source and drain regions (18,20) the structure then being annealed. The use of the specified materials for the gate electrode of a vertical type high power IGFET is also described. The materials have lower resistivity and are more resistant to etching treatments on annealing processes than polysilicon. <IMAGE>

Description

SPECIFICATION MOS type semiconductor device and process for manufacturing the same The present invention relates to a MOS type semiconductor device and a process for manufacturing the same. More particularly, the present invention relates to a MOS type semiconductor device having a gate electrode formed of an interstitial transition metal nitride or an interstitial transition metal carbide.
MOS (Metal Oxide Semiconductor) type semiconductor devices are well-known to those skilled in the art. A typical MOS type semiconductor device includes a semiconductor substrate of a first conductivity type, source and drain regions which are impurity regions of a second conductivity type and are formed in a surface region of the semiconductor substrate, a gate oxide film formed on a channel region between the source and drain regions, and a gate electrode formed on the gate oxide film. The MOS type semiconductor device of this type is prepared such that the gate oxide film is formed on the semiconductor substrate, the gate electrode is formed on the gate oxide film, and impurity ions are implanted using the gate electrode as a mask so as to form the source and drain regions. In general, annealing is performed to diffuse the impurity after the impurity ions are implanted.
Ion-implantation using the gate electrode as a mask is called a self alignment technique.
The gate electrode of the conventional MOS type semiconductor device is generally made of polycrystalline silicon (poly-Si). In the process for manufacturing the MOS type semiconductor device, the self alignment technique is used so that impurity ions are implanted into the poly-Si, thereby decreasing a sheet resistance of the gate electrode. However, the impurity, which is electrically active in poly-Si, has a limited solid solubility. For this reason, it is difficult to decrease the sheet resistance of the poly-Si gate electrode to 20 or on less. When the sheet resistance of the gate electrode is high, high-speed operation of the device cannot be performed, and high4requency characteristics thereof cannot be improved.In addition to these disadvantages, the driving voltage of the semiconductor device must be increased.
In order to eliminate these disadvantages caused by high sheet resistance of the gate electrode, it is proposed that the gate electrode be formed by a high melting metal such as molybdenum and tungsten. However, when such a metal is used to form the gate electrode, it then has a low resistance to chemicals and to high temperatures. As a result, annealing cannot be sufficiently performed after ions are implanted, thus disabling the self alignment technique. Therefore, the packing density of the device cannot be increased, and the manufacturing process becomes complex. Furthermore, electrical characteristics of the gate oxide film are degraded, and hence reliability of the semiconductor device is degraded.
in order to eliminate these drawbacks, it is also proposed that a high melting metal silicide be used to form the gate electrode.
However, the sheet resistance of such a gate electrode is also high. In addition to this drawback, reliability of the semiconductor device cannot be sufficiently improved.
It is, therefore, an object of the present invention to provide a MOS type semiconductor device, and a process for manufacturing the same, which has a gate electrode with a low sheet resistance, a good resistance to chemicals, and a good resistance to high temperatures, thereby providing high-speed operation and good high-frequency characteristics.
According to an aspect of the present invention, there is provided a MOS type semiconductor device comprising a semiconductor substrate, source and drain regions formed in the semiconductor substrate, a gate oxide film formed on a channel region of the semiconductor substrate, and a gate electrode which is formed on the gate oxide film and which is made of an interstitial transition metal nitride or an interstitial transition metal carbide.
The gate electrode of the MOS type semiconductor device of the present invention has a low sheet resistance, and good resistance to both chemicals and high temperatures. For these reasons, the MOS type semiconductor device of the present invention can be operated at high speed and provides good highfrequency characteristics. Furthermore, the driving voltage of the device can be decreased.
This invention can be more fully understood from the following detailed description when taken in conjunction with the accompanying drawings, in which: Figures 1 to 4 are sectional views for explaining the steps of manufacturing a MOS type semiconductor device according to a method of the present invention; Figures 5 to 10 are sectional views for explaining the steps of manufacturing a MOS type semiconductor device according to another method of the present invention; and Figure 11 is a graph showing the mutual conductance as a function of the frequency for the MOS type semiconductor device of the present invention as compared with the conventional MOS type semiconductor device.
A process for manufacturing a MOS type semiconductor device of the present invention will be described with reference to Figs. 1 to 4.
A semiconductor substrate 10 (see Fig. 1) with e.g. p-type conductivity is heat-treated by a well-known technique to form a thermal oxide film having a thickness of e.g. 1 ym.
This thermal oxide film serves as a field oxide film 12. The thermal oxide film is selectively etched at a prospective element formation region of the semiconductor substrate 10. The resultant structure is heat-treated to form a gate oxide film 14 having a thickness of e.g.
about 0.1 pm on an exposed portion of the semiconductor substrate 10 (Fig. 1).
A A gate electrode 16 (see Fig. 2) of an interstitial transition metal nitride or an interstitial transition metal carbide is selectively formed on the gate oxide film 14. A preferable transition metal is selected from Ti, Hf, Zr, Ta, Nb, Sc and Mo. The gate electrode 16 is formed such that the interstitial transition metal nitride or interstitial transition metal carbide is first formed to cover the entire surface of the gate oxide film 14 and is then patterned by photoetching such as a wellknown reactive ion etching technique.The interstitial transition metal nitride layer can be formed by any one of the following four techniques: (1) Sputtering A target of a transition metal nitride is placed at the top inside a hermetically sealed chamber, and a semiconductor substrate on which the interstitial transition metal nitride is intended to be deposited is placed immediately under the target. Ar gas is introduced into the hermetically sealed chamber at a pressure of 10-2 Torr. The target is heated at a a temperature of 500 C.
(2) Reactive Sputtering In the above-mentioned sputtering technique, the target is made of a transition metal, and a gaseous atmosphere comprises 90 mol% of Ar and 10 mol% of nitrogen.
(3) Plasma CVD A transition metal chloride is reacted in a plasma of N2 and H2 at a pressure of 10-2 Torr and at a temperature of 500 C to deposit a transition metal nitride on the substrate.
(4) Ion Plating A A transition metal is reacted in a plasma (90 mol% of Ar and 10 mol% of N2) at a pressure of 10-2 Torr and at a temperature of 500"C to deposit a transition metal nitride on the substrate.
The interstitial transition metal carbide can be obtained by technique (1) when a transition metal carbide is used as a target. In any other technique described above, a saturated hydrocarbon such as propane or an unsaturated hydrocarbon such as ethylene and acetylene is used instead of N2.
Using the gate electrode 16 and the field oxide film 12 as masks, ions such as phosphorus ions are implanted at an acceleration voltage of 100 keV through the gate oxide film 14, thereby forming high-impurity regions 18' and 20' (Fig. 2). The dose of the impurity depends on the desired diffusion depth, but is 1 X 1015 ions/cm2 for example.
A A CVD-SiO2 film 22 of a suitable thickness is formed by a well-known technique on the gate electrode 16, the gate oxide film 14 and the field oxide film 12 so as to provide electric insulation. The resultant structure is annealed at a temperature of 1 ,000,C for 15 minutes, so that the impurity in the highimpurity regions 18' and 20' is diffused to form source and drain regions 18 and 20, respectively (Fig. 3).
Contact holes are formed through the CVD SiO2 film 22 and the gate oxide film 14 by a well-known photo-etching technique to partially expose the source and drain regions 18 and 20, respectively. Aluminum-silicon electrodes are deposited by sputtering to form source and drain electrodes 24 and 26, respectively (Fig. 4).
When the gate electrode of the MOS type semiconductor device is formed of an interstitial transition metal nitride or interstitial transition metal carbide, the sheet resistance of the gate electrode can be decreased to 1/10 or less (e.g. to 0.5 S~/C) of that of doped poly Si. Further, the gate electrode has a good resistance to chemicals. Moreover, in the above manufacturing process, after the impurity ions are doped, annealing is performed to form the source and drain regions. Since the gate electrode is made of an interstitial transition metal nitride or interstitial transition metal carbide, the gate electrode has a good resistance to high temperatures. For example, when TiN is used, the structure may be annealed at a high temperature of 2,000"C.On the other hand, the upper limit of the annealing temperature of poly-Si is 1,200 C to 1,300 C, and the upper limit of the annealing temperature of aluminum is 500'C. Thus, according to the present invention, high-temperature annealing can be performed, so that a desirable deep impurity region can be formed. Further, annealing is often performed after an aluminum electrode is formed on the gate electrode. According to the present invention, even if this occurs, the gate electrode does not react with the aluminum electrode.
However, as in the conventional device wherein the gate electrode is made of poly-Si, Si reacts with Al, so that the sheet resistance of the gate electrode is increased. Furthermore, the interstitial transition metal nitride and the interstitial transition metal carbide have a good masking effect when the impurity is ion-implanted. Therefore, according to the method of the present invention, the impurity ions are substantially not implanted into the channel region covered with the gate electrode. Further, the interstitial transition metal nitride and the interstitial transition metal carbide provide a stable structure when impurity ions are ion-implanted therein. As a result, the gate electrode is stabilized according to the process of the present invention.
Another embodiment will be described with reference to Figs. 5 to 10, wherein the method of the present invention was applied to a high-power MOS type semiconductor device.
An epitaxial silicon layer 30 (see Fig. 5) having a resistivity of 10 to 1 5 cm was formed by a conventional method on an n+type Sb-doped silicon substrate 28 having a resistivity of 0.015 S2 ##cm, to a thickness of 40 sssm. The resultant structure was annealed at a temperature of 1,000 C to form a field oxide film 32 of about 1 ym thickness on the epitaxial silicon layer 30. The field oxide film 32 was then selectively etched by a wellknown photoetching technique to expose that part of the epitaxial layer 30 which corresponds to a prospective element formation region. Thermal oxidation was then performed to form a gate oxide film 34 about 0. 1 ym thick on the exposed portion of the epitaxial layer 30 (Fig. 5).
A TiN layer was deposited by sputtering on the gate oxide film 34 and was patterned by a photoengraving technique using a well-known reactive ion etching technique, thereby obtaining a gate electrode 36 (see Fig. 6). Using the gate electrode 36 and the field oxide film 32 as masks, boron was then ion-implanted at an acceleration voltage of 40 KeV (the acceleration voltage of boron is usually 40 to 160 KeV) and at a dose of 1 X 10-14 ions/cm-2.
Thus, high-impurity regions 38' were formed (Fig. 6).
In order to prevent oxidation of TiN, an anti-oxidation film 40 (see Fig. 7) made of poly-Si having a thickness of about 0.3 ym was formed by a well-known reduced pressure epitaxial growth technique at a temperature of 600"C to cover the gate electrode 36, the gate oxide film 34 and the field oxide film 32.
A material for the anti-oxidation film 40 may be selected, instead of poly-Si, from SiO2, phosphosilicate glass, borosilicate glass, arsenosilicate glass, phospho-arsenic silicate glass, Si3 N4 or Al203. The resultant structure was annealed in a gaseous atmosphere of N2 and O, at a ratio of 10 to 1 at a temperature of 1,OOOoC for about 10 hours. The impurity was diffused from the high-impurity regions 38' to form first impurity regions 38 (Fig. 7).
After the SiO2 film formed on the surface of the anti-oxidation film 40 was etched off by a NH4F solution, the anti-oxidation film 40 was etched off by a well-known plasma etching technique using a gaseous mixture of CF4 and 03. Using the gate electrode 36 and the field oxide film 32 as masks, 31P was ion-implanted in the first impurity regions 38 at an acceleration voltage of 120 KeV and a dose of 1 X 10'5 ions/cm2 (Fig. 8).
In order to provide electric insulation, a CVD-phosphosilicate glass film (CVDPSG film) 42 having a thickness of about 1.0 ym was formed to cover the gate electrode 36, the gate oxide film 34 and the field oxide film 32.
Subsequently, the resultant structure was annealed in a N2/02 atmosphere at a temperature of 950 C for about 15 minutes. Thus, second impurity regions 44 serving as source regions were formed in the first impurity regions 38 (Fig. 9).
Portions of the CVDPSG film 42 and portions of the gate oxide film 34 which cover the second impurity regions are selectively etched to partially expose the second impurity regions, and another portion of the CVDPSG film 42 which covers the gate electrode 36 is selectively etched to partially expose the gate electrode 36, thereby forming contact holes in accordance with a well-known selective photoengraving technique. An aluminum layer was deposited to a thickness of about 4 #m by a well-known electron-beam deposition method so as to fill the contact holes with aluminum, and was patterned by photoengraving, thereby forming aluminum electrodes 46.
Finally, a drain electrode 48 was formed on the bottom surface of the n±type silicon substrate 28 by continuously vapor-depositing V, Ni and Au thereon. As a result, a desired high-power MOS type semiconductor device was obtained.
In the MOS type semiconductor device of the present invention, the gate electrode is made of an interstitial transition metal nitride or an interstitial transition metal carbide which has a strong masking effect upon ion-implantation of the impurity. Therefore, the abovedescribed double diffusion technique is effectively adopted wherein second impurity regions are formed in the first impurity regions.
The relationship (curve I) between the frequency of the MOS type semiconductor device thus obtained and the mutual conductance IYfsl thereof is shown in Fig. 11. The relationship (curve II) between the frequency of a conventional MOS type semiconductor device and the mutual conductance thereof when the gate electrode is made of poly-Si, and the relationship (curve Ill) therebetween when the gate electrode is made of molybdenum silicide are also examined for purposes of comparison. The measuring conditions were as follows: a source-drain voltage of 10 V; a gate input voltage of 100 mV; and a drain current of 2 A. As may be apparent from Fig. 11, in the MOS type semiconductor device according to the present invention, a cut-off frequency at a point (i.e., | Yfs I which was 0.707 times Yfsi at a low frequency) where the mutual conductance JYfs is lowered by 3 dB was 4.5 MHz. However, in the conventional MOS type semiconductor devices having the poly-Si gate electrode and the molybdenum silicide gate electrode, the cut-off frequencies were 1.0 MHz and 3.0 MHz, respectively. Based on this result, the MOS type semiconductor device of the present invention has good high-frequency characteristics.

Claims (13)

1. A MOS type semiconductor device comprising: a semiconductor substrate of a first conductivity type; a first impurity region of a second conductivity type formed in said semiconductor substrate, said first impurity region extending inward from the surface of said semiconductor substrate and serving as a source region; a second impurity region of the second conductivity type formed in said semiconductor substrate, said second impurity region extending inward from the surface of said semiconductor substrate and serving as a drain region; a gate oxide film formed on a channel region of said semiconductor substrate between said first and second impurity regions; and a gate electrode formed on said gate oxide film and made of an interstitial transition metal nitride or an interstitial transition metal carbide.
2. The MOS type semiconductor device according to claim 1, wherein the impurity which is used for forming said first and second impurity regions is implanted in said gate electrode.
3. The MOS type semiconductor device according to claim 1, wherein said transition metal is selected from the group consisting of Ti, Hf, Zr, Ta, Nb, Sc and Mo.
4. A process for manufacturing the MOS type semiconductor device of claim 1, comprising the steps of: forming a gate oxide film on a semiconductor substrate of a first conductivity type; forming a gate electrode which is made of an interstitial transition,metal nitride or an interstitial transition metal carbide on said gate oxide film; and implanting an impurity ion imparting a second conductivity type in said semiconductor substrate through said gate oxide film using said gate electrode as a mask, thereby forming first and second impurity regions.
5. The process according to claim 4, wherein said transition metal is selected from the group consisting of Ti, Hf, Zr, Ta, Nb, Sc and Mo.
6. A MOS type semiconductor device comprising: a semiconductor substrate of a first conductivity type which serves as a drain region; a first impurity region of a second conductivity type formed in said semiconductor substrate, said first impurity region extending inward from the surface of said semiconductor substrate; a second impurity region of the first con ductivity type formed in said first impurity region, said second impurity region extending inward from the surface of said semiconductor substrate and serving as a source region; a gate oxide film formed on a channel region between said source and drain regions; and a gate electrode formed on said gate oxide film and made of an interstitial transition metal nitride or an interstitial transition metal carbide.
7. The MOS type semiconductor device according to claim 6, wherein said transition metal is selected from the group consisting of Ti, Hf, Zr, Ta, Nb, Sc and Mo.
8. A process for manufacturing the MOS type semiconductor device of claim 6, com prising the steps of: forming a gate oxide film on a semiconduc tor substrate of a first conductivity type; forming a gate electrode on said gate elec trode film, said gate electrode being made of an interstitial transition metal nitride or an interstitial transition metal carbide; implanting a first impurity ion imparting a second conductivity type in said semiconduc tor substrate through said gate oxide film using said gate electrode as a mask, thereby forming a first impurity region; and implanting a second impurity ion imparting the first conductivity type in said first impurity region through said gate oxide film using said gate electrode as a mask, thereby forming a second impurity region.
9. The process according to claim 8, fur ther comprising the step of performing anneal ing after the first impurity ion is implanted and before the second impurity ion is im planted, thereby diffusing the first impurity to enlarge said first impurity region.
10. The process according to claim 8, wherein said transition metal is selected from the group consisting of Ti, Hf, Zr, Ta, Nb, Sc and Mo.
11. A MOS type semiconductor device comprising: a semiconductor substrate; a source region formed in said semiconduc tor substrate; a drain region formed in said semiconductor substrate; a gate oxide film formed on a channel region of said semiconductor substrate; and a a gate electrode formed on said gate oxide film and made of an interstitial transition metal nitride or an interstitial transition metal carbide.
12. A MOS type semiconductor device, substantially as hereinbefore described with reference to the accompanying drawings.
13. A process for manufacturing a MOS type semiconductor device, substantially as hereinbefore described.
GB08320459A 1982-08-03 1983-07-29 Materials for mos device gate electrodes Expired GB2126419B (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP57135409A JPS5925273A (en) 1982-08-03 1982-08-03 Semiconductor device and manufacture thereof

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GB8320459D0 GB8320459D0 (en) 1983-09-01
GB2126419A true GB2126419A (en) 1984-03-21
GB2126419B GB2126419B (en) 1985-09-25

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Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB2243948A (en) * 1990-04-20 1991-11-13 Nobuo Mikoshiba Field effect transistor
GB2247349A (en) * 1990-08-20 1992-02-26 Samsung Electronics Co Ltd Method for fabricating MOS transistors
GB2231720B (en) * 1989-04-21 1993-08-11 Nobuo Mikoshiba Integrated circuit

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB2231720B (en) * 1989-04-21 1993-08-11 Nobuo Mikoshiba Integrated circuit
GB2243948A (en) * 1990-04-20 1991-11-13 Nobuo Mikoshiba Field effect transistor
GB2243948B (en) * 1990-04-20 1994-06-08 Nobuo Mikoshiba Integrated circuit
GB2247349A (en) * 1990-08-20 1992-02-26 Samsung Electronics Co Ltd Method for fabricating MOS transistors
DE4114166A1 (en) * 1990-08-20 1992-02-27 Samsung Electronics Co Ltd METHOD FOR PRODUCING A TRANSISTOR THAT HAS THE STRUCTURE OF A GATE INSULATION LAYER SEMICONDUCTOR

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Publication number Publication date
JPS5925273A (en) 1984-02-09
GB2126419B (en) 1985-09-25
GB8320459D0 (en) 1983-09-01
DE3328058A1 (en) 1984-02-09

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Effective date: 19981015

PCNP Patent ceased through non-payment of renewal fee

Effective date: 20010729