KR20090045754A - Method for forming pattern in semiconductor device using hardmask - Google Patents

Method for forming pattern in semiconductor device using hardmask Download PDF

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Publication number
KR20090045754A
KR20090045754A KR1020070111732A KR20070111732A KR20090045754A KR 20090045754 A KR20090045754 A KR 20090045754A KR 1020070111732 A KR1020070111732 A KR 1020070111732A KR 20070111732 A KR20070111732 A KR 20070111732A KR 20090045754 A KR20090045754 A KR 20090045754A
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KR
South Korea
Prior art keywords
film
semiconductor device
amorphous carbon
hard mask
carbon film
Prior art date
Application number
KR1020070111732A
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Korean (ko)
Inventor
김태형
Original Assignee
주식회사 하이닉스반도체
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Publication date
Application filed by 주식회사 하이닉스반도체 filed Critical 주식회사 하이닉스반도체
Priority to KR1020070111732A priority Critical patent/KR20090045754A/en
Publication of KR20090045754A publication Critical patent/KR20090045754A/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H01L21/033—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers
    • H01L21/0334—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
    • H01L21/0337—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane characterised by the process involved to create the mask, e.g. lift-off masks, sidewalls, or to modify the mask, e.g. pre-treatment, post-treatment
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31105—Etching inorganic layers
    • H01L21/31111—Etching inorganic layers by chemical means
    • H01L21/31116—Etching inorganic layers by chemical means by dry-etching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31144—Etching the insulating layers by chemical or physical means using masks

Abstract

The present invention relates to a method of forming a pattern of a semiconductor device using a hard mask, the method of forming a pattern of a semiconductor device of the present invention comprises: forming an amorphous carbon film for a hard mask and a polysilicon film for a hard mask on an etched layer; Forming a photoresist pattern on the polysilicon film; Etching the polysilicon layer using the photoresist pattern as an etching barrier; Forming a polymer on the sidewalls of the etched amorphous carbon film using at least the etched polysilicon film as an etch barrier to etch the amorphous carbon film; And etching the etched layer using at least the etched amorphous carbon film as an etch barrier, wherein the pattern forming method of the semiconductor device using the hard mask according to the present invention includes polysilicon in which a large amount of polymer is produced during dry etching. By forming the film on the amorphous carbon film hard mask, the sidewalls of the amorphous carbon film hard mask may be protected by the polymer during etching.

Hard mask, amorphous carbon film, polysilicon film, polymer

Description

Pattern formation method of semiconductor device using hard mask {METHOD FOR FORMING PATTERN IN SEMICONDUCTOR DEVICE USING HARDMASK}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device manufacturing technology, and more particularly, to a pattern formation method of a semiconductor device using an amorphous carbon film as a hard mask.

In forming a predetermined pattern of a semiconductor device such as a gate pattern and a bit line, a pattern is generally formed by interposing a hard mask below the photoresist pattern. Conventionally, an oxide film or a nitride film is used as such a hard mask, but recently, an amorphous carbon film having excellent etching selectivity and relatively low temperature deposition is widely used as a hard mask. At this time, the amorphous carbon film is hardly used alone and is used together with the SiON film thereon.

1 is a cross-sectional view for explaining a pattern formation method of a semiconductor device using a conventional amorphous carbon film hard mask. In this figure, description will be made using gate pattern formation as an example.

As shown in FIG. 1, a gate oxide film 11, a polysilicon film 12 for a gate electrode, a tungsten film 13 for a gate electrode 13 and a nitride film 14 for a gate hard mask are deposited on the semiconductor substrate 10. As shown in FIG. do.

Subsequently, the amorphous carbon film 15 and the SiON film 16 are deposited on the nitride film 14 for the gate hard mask as a hard mask for gate patterning, and then the photoresist pattern 17 is formed on the SiON film 16. do.

Subsequently, the SiON film 16 and the amorphous carbon film 15 are etched using the photoresist pattern 17 as an etching mask.

Subsequently, although not shown in the drawing, the etched SiON film 16 and the amorphous carbon film 15 are etched as a lower layer, that is, a nitride film 14 for a gate hard mask, a tungsten film 13 for a gate electrode, and a gate electrode. The polysilicon layer 12 is etched to form a gate pattern.

This prior art has the following problems.

When the SiON film 16 and the amorphous carbon film 15 are etched using the photoresist pattern 17 as an etch mask, undercuts are formed under the SiON film 16, so that sidewalls of the amorphous carbon film 15 are greatly lost. (See dotted line in FIG. 1). Accordingly, when the lower layer is etched using the lost amorphous carbon film 15 as an etch barrier, a thinning phenomenon occurs in which the lower layer, in particular, the nitride film 14 for the gate hard mask is attacked and lost.

The thinning phenomenon of the nitride film 14 for gate hard mask causes various defects such as a bridge between subsequent landing plug contacts, thereby degrading the device characteristics. In particular, with the recent high integration of semiconductor devices, pattern formation of 40 nm or less has been required.

The present invention has been proposed to solve the above problems of the prior art, by forming a polysilicon film in which a large amount of polymer during dry etching is formed on the amorphous carbon film hard mask, the sidewalls of the amorphous carbon film hard mask are etched by the polymer. An object of the present invention is to provide a method of forming a pattern of a semiconductor device using a hard mask that can be protected.

The pattern forming method of a semiconductor device using the hard mask of the present invention for achieving the above object comprises the steps of: forming an amorphous carbon film for the hard mask and a polysilicon film for the hard mask on the etching target layer; Forming a photoresist pattern on the polysilicon film; Etching the polysilicon layer using the photoresist pattern as an etching barrier; Forming a polymer on the sidewalls of the etched amorphous carbon film using at least the etched polysilicon film as an etch barrier to etch the amorphous carbon film; And etching the etched layer using at least the etched amorphous carbon film as an etch barrier.

In the method of forming a semiconductor device using the hard mask according to the present invention, a polysilicon film in which a large amount of polymer is formed during dry etching is formed on an amorphous carbon film hard mask, so that sidewalls of the polymer layer are etched by etching the amorphous carbon film hard mask. Can be protected by.

DETAILED DESCRIPTION Hereinafter, the most preferred embodiments of the present invention will be described with reference to the accompanying drawings so that those skilled in the art may easily implement the technical idea of the present invention. do.

2A to 2C are cross-sectional views illustrating a method of forming a pattern of a semiconductor device using a hard mask according to an embodiment of the present invention. In this figure, description will be made using gate pattern formation as an example.

As shown in FIG. 2A, a gate oxide film 21, a polysilicon film 22 for a gate electrode, a tungsten film 23 for a gate electrode, and a nitride film 24 for a gate hard mask are deposited on the semiconductor substrate 20. As shown in FIG. do.

Subsequently, an amorphous carbon film 25, a polysilicon film 26, and a SiON film 27 are deposited on the nitride film 24 for the gate hard mask as a hard mask for gate patterning. That is, unlike the conventional art, the polysilicon film 26 is interposed between the amorphous carbon film 25 and the SiON film 27. At this time, it is preferable that the thickness of the amorphous carbon film 25 is 500-2000 kPa, and the thickness of the polysilicon film 26 is 500-2000 kPa.

Subsequently, a photoresist pattern 29 for gate patterning is formed on the SiON film 27. In this case, an anti-reflection film 28 for anti-reflection during the exposure process may be interposed below the photoresist pattern 29.

As shown in FIG. 2B, the SiON film 27 and the polysilicon film 26 are etched using the photoresist pattern 29 as an etching mask. Here, the etching process of the polysilicon film 26 is preferably performed for 10 to 50 seconds using a mixed gas of O 2 , N 2 , NF 3 or H 2 about 400 ~ 2000sccm.

As shown in FIG. 2C, the amorphous carbon film 25 is etched using at least the etched polysilicon film 26 as an etching barrier. At this time, since a large amount of polymer (A) is generated by the polysilicon film 26, the sidewalls of the amorphous carbon film 25 to be etched are protected by the polymer (A). Therefore, it is possible to prevent sidewall loss of the amorphous carbon film 25, thereby preventing attack and thinning of the nitride film 24 for subsequent gate hard masks. The etching process of the amorphous carbon film 25 is preferably performed for 10 to 50 seconds using a mixed gas of O 2 , N 2 , SO 2 or COS about 400 ~ 2000sccm.

Subsequently, although not shown in the drawing, at least the etched amorphous carbon film 25 and the polymer A on the sidewall thereof are etched as a lower layer, that is, the nitride film 24 for the gate hard mask and the tungsten film 23 for the gate electrode. And etching the polysilicon film 22 for the gate electrode to form a gate pattern.

Although the technical spirit of the present invention has been specifically recorded in accordance with the above-described preferred embodiments, it should be noted that the above-described embodiment is for the purpose of description and not of limitation. In addition, those skilled in the art will understand that various embodiments are possible within the scope of the technical idea of the present invention.

1 is a cross-sectional view for explaining a method of forming a pattern of a semiconductor device using a conventional amorphous carbon film hard mask.

2A to 2C are cross-sectional views illustrating a method of forming a pattern of a semiconductor device using a hard mask according to an embodiment of the present invention.

* Explanation of symbols for the main parts of the drawings

20 substrate 21 gate oxide film

22 polysilicon film for gate electrode 23 tungsten film for gate electrode

24 nitride film for gate hard mask 25 amorphous carbon film

26 polysilicon film 27 SiON film

28: antireflection film 29: photoresist pattern

Claims (11)

Forming an amorphous carbon film for a hard mask and a polysilicon film for a hard mask on the etching layer; Forming a photoresist pattern on the polysilicon film; Etching the polysilicon layer using the photoresist pattern as an etching barrier; Forming a polymer on the sidewalls of the etched amorphous carbon film using at least the etched polysilicon film as an etch barrier to etch the amorphous carbon film; And Etching the etched layer using at least the etched amorphous carbon film as an etch barrier Pattern forming method of a semiconductor device comprising a. The method of claim 1, The thickness of the polysilicon film is 500 ~ 2000Å Pattern formation method of a semiconductor device. The method according to claim 1 or 2, The polysilicon film etching step, Carried out using a mixed gas of O 2 , N 2 , NF 3 or H 2 Pattern formation method of a semiconductor device. The method of claim 3, The flow rate of the mixed gas is 400 ~ 2000sccm Pattern formation method of a semiconductor device. The method of claim 3, The polysilicon film etching step, For 10 to 50 seconds Pattern formation method of a semiconductor device. The method of claim 1, The thickness of the amorphous carbon film is 500 ~ 2000Å Pattern formation method of a semiconductor device. The method according to claim 1 or 6, The amorphous carbon film etching step, Carried out using a mixed gas of O 2 , N 2 , SO 2 or COS Pattern formation method of a semiconductor device. The method of claim 7, wherein The flow rate of the mixed gas is 400 ~ 2000sccm Pattern formation method of a semiconductor device. The method of claim 7, wherein The polysilicon film etching step, For 10 to 50 seconds Pattern formation method of a semiconductor device. The method of claim 1, A SiON film is interposed between the photoresist pattern and the polysilicon film. Pattern formation method of a semiconductor device. The method of claim 1, The etched layer includes a nitride film on its top Pattern formation method of a semiconductor device.
KR1020070111732A 2007-11-02 2007-11-02 Method for forming pattern in semiconductor device using hardmask KR20090045754A (en)

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Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20120047600A (en) * 2010-11-04 2012-05-14 삼성전자주식회사 Method of forming a fine pattern and method of fabricating a semiconductor device
US9666433B2 (en) 2015-05-27 2017-05-30 Samsung Electronics Co., Ltd. Methods for manufacturing a semiconductor device
US10586709B2 (en) 2017-12-05 2020-03-10 Samsung Electronics Co., Ltd. Methods of fabricating semiconductor devices

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20120047600A (en) * 2010-11-04 2012-05-14 삼성전자주식회사 Method of forming a fine pattern and method of fabricating a semiconductor device
US8557131B2 (en) 2010-11-04 2013-10-15 Samsung Electronics Co., Ltd. Methods of forming fine patterns and methods of fabricating semiconductor devices
US9666433B2 (en) 2015-05-27 2017-05-30 Samsung Electronics Co., Ltd. Methods for manufacturing a semiconductor device
US10586709B2 (en) 2017-12-05 2020-03-10 Samsung Electronics Co., Ltd. Methods of fabricating semiconductor devices

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