KR20000044928A - Method for forming trench of semiconductor device - Google Patents

Method for forming trench of semiconductor device Download PDF

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Publication number
KR20000044928A
KR20000044928A KR1019980061431A KR19980061431A KR20000044928A KR 20000044928 A KR20000044928 A KR 20000044928A KR 1019980061431 A KR1019980061431 A KR 1019980061431A KR 19980061431 A KR19980061431 A KR 19980061431A KR 20000044928 A KR20000044928 A KR 20000044928A
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South Korea
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film
semiconductor device
forming
mask
etching
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KR1019980061431A
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Korean (ko)
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김종국
김진웅
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김영환
현대전자산업 주식회사
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Priority to KR1019980061431A priority Critical patent/KR20000044928A/en
Publication of KR20000044928A publication Critical patent/KR20000044928A/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/308—Chemical or electrical treatment, e.g. electrolytic etching using masks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31127—Etching organic layers
    • H01L21/31133—Etching organic layers by chemical means
    • H01L21/31138—Etching organic layers by chemical means by dry-etching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31144—Etching the insulating layers by chemical or physical means using masks

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • General Chemical & Material Sciences (AREA)
  • Drying Of Semiconductors (AREA)

Abstract

PURPOSE: A method for fabricating a trench of a semiconductor device is provided to reduce the fail rate of a transistor and the manufacturing time and to improve the productivity of the semiconductor device by restraining the spot defect occurred during a shallow trench isolation process is carried out. CONSTITUTION: A pad oxide layer(22) and a nitride film(23) are sequentially formed on a semiconductor substrate(21) and an organic reflection preventing film(25) is formed on an upper portion of the structure. A photo-sensitive film pattern(24) is coated on an upper portion of the organic reflection preventing film(25). Then, the organic reflection preventing film(25) is patterned. By using the photo-sensitive film pattern(24) as a mask, the nitride film(23), the pad oxide layer(22) the semiconductor substrate(21) are sequentially etched.

Description

반도체 소자의 트랜치 형성 방법Trench Formation Method for Semiconductor Devices

본 발명은 반도체 소자의 트랜치 형성 방법에 관한 것으로, 특히 쉘로우 트랜치 소자분리막(Shallow Trench Isolation; STI) 형성 공정에서 감광막 패턴 형성시 발생하는 스포트 결함(spot defect)의 발생을 억제하기 위한 반도체 소자의 트랜치 형성 방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a trench formation method of a semiconductor device, and more particularly to trenches of semiconductor devices for suppressing spot defects generated during photosensitive film pattern formation in a shallow trench isolation (STI) forming process. It relates to a forming method.

도 1a 내지 1c는 종래 반도체 소자의 트랜치 형성 방법을 설명하기 위해 순차적으로 도시한 소자의 단면도이다.1A to 1C are cross-sectional views of devices sequentially illustrated to explain a trench forming method of a conventional semiconductor device.

도 1a에 도시된 바와 같이, 실리콘 기판(11) 상부에 패드 산화막(12) 및 질화막(13)을 형성하고, 질화막(13) 상부에 감광막을 코팅한 후 마스크를 이용한 노광 및 현상 공정을 통해 소자분리용 감광막 패턴(14)을 형성한다.As shown in FIG. 1A, the pad oxide film 12 and the nitride film 13 are formed on the silicon substrate 11, the photoresist is coated on the nitride film 13, and the device is exposed and developed using a mask. The separation photosensitive film pattern 14 is formed.

도 1b는 감광막 패턴(14)을 마스크로 이용한 식각 공정으로 질화막(13)을 식각한 상태를 나타내는 단면도이다. 이 식각 공정은 감광막 패턴(14)에 대한 높은 선택비를 갖는 식각 레시피(recipe)로 실시한다. 따라서, 감광막 패터닝시에 질화막(13) 상부에 감광막 스컴(scum)이 남아 있는 경우, 질화막(13) 식각 공정에서 감광막 스컴이 식각 장벽이 되어 스포트 결함(A 부분)이 발생하며, 질화막(13)이 완전히 식각되지 않는 문제점이 있다.FIG. 1B is a cross-sectional view illustrating a state in which the nitride film 13 is etched by an etching process using the photosensitive film pattern 14 as a mask. This etching process is carried out with an etching recipe having a high selectivity to the photoresist pattern 14. Therefore, when the photoresist scum remains on the nitride film 13 at the time of photoresist patterning, the photoresist scum becomes an etch barrier in the etching process of the nitride film 13 to generate spot defects (part A), and the nitride film 13 There is a problem that is not fully etched.

도 1c는 질화막(13)에 대해 높은 선택비를 갖는 식각 레시피로 실리콘 기판(11)을 식각한 상태를 나타내는 단면도이다. 이 경우, 완전히 제거되지 않고 잔류하는 질화막 스컴이 식각 장벽이 되어, 실리콘 기판(11)이 완전히 식각되지 않아 질화막(13) 식각시 발생한 스포트 결함(A)이 더욱 심화되어 나타나는 것을 알 수 있다(B 부분).FIG. 1C is a cross-sectional view illustrating a state in which the silicon substrate 11 is etched with an etching recipe having a high selectivity with respect to the nitride film 13. In this case, it can be seen that the nitride film scum remaining without being completely removed becomes an etch barrier, and thus the silicon substrate 11 is not completely etched so that the spot defect A generated during the etching of the nitride film 13 is further deepened (B). part).

이와 같은 스포트 결함에 의해 소자분리 특성이 저하되어 소자의 신뢰성이 저하되는 문제점이 있다.Due to such spot defects, there is a problem in that device isolation characteristics are degraded and device reliability is degraded.

따라서, 본 발명은 감광막을 형성하기 전 유기(organic) 반사 방지막을 형성하고, 감광막 패턴을 형성한 다음 감광막을 식각 장벽으로 하여 유기 반사방지막을 패터닝할 때 감광막 스컴이 동시에 제거되도록 하므로써 스포트 결함의 발생을 억제할 수 있는 반도체 소자의 트랜치 형성 방법을 제공하는데 그 목적이 있다.Therefore, in the present invention, spot defects are generated by forming an organic antireflection film before forming the photoresist film, forming a photoresist pattern, and then removing the photoresist scum simultaneously when patterning the organic antireflection film by using the photoresist as an etch barrier. SUMMARY OF THE INVENTION An object of the present invention is to provide a method for forming a trench in a semiconductor device capable of suppressing this problem.

상술한 목적을 달성하기 위한 본 발명에 따른 반도체 소자의 트랜치 형성 방법은 실리콘 기판 상부에 패트 산화막 및 질화막을 순차적으로 형성하고, 전체 구조 상부에 유기 반사 방지막을 형성하는 단계와, 상기 유기 반사 방지막 상부에 감광막을 코팅한 후 마스크를 이용한 노광 및 현상 공정을 통해 소자분리용 감광막 패턴을 형성하는 단계와, 상기 감광막 패턴을 마스크로 이용하여, Cl2/및 O2를 베이스로 사용하고, 과도 식각율을 20 ∼ 100%로 한 식각 공정으로 상기 유기 반사 방지막을 패터닝하는 단계와, 상기 감광막 패턴을 마스크로 이용하여 CHF4및 Ar을 베이스로 사용한 식각 공정으로 상기 질화막을 식각한 후 패드 산화막을 식각하는 단계와, 상기 감광막 패턴을 마스크로 이용하여 상기 실리콘 기판을 식각하는 단계를 포함하여 이루어지는 것을 특징으로 한다.The trench forming method of the semiconductor device according to the present invention for achieving the above object is a step of sequentially forming a pat oxide film and a nitride film on the silicon substrate, and forming an organic antireflection film on the entire structure, and the top of the organic antireflection film Forming a photoresist pattern for device isolation through an exposure and development process using a mask after coating the photoresist on the photoresist; and using the photoresist pattern as a mask, using Cl 2 / and O 2 as a base, and transient etching rate Patterning the organic anti-reflection film by an etching process using 20 to 100%, and etching the nitride film using an etching process using CHF 4 and Ar as a base using the photoresist pattern as a mask to etch the pad oxide film. And etching the silicon substrate using the photoresist pattern as a mask. It is characterized by.

도 1a 내지 1c는 종래 반도체 소자의 트랜치 형성 방법을 설명하기 위해 순차적으로 도시한 소자의 단면도.1A to 1C are cross-sectional views of devices sequentially shown in order to explain a trench forming method of a conventional semiconductor device.

도 2a 내지 2d는 본 발명에 따른 반도체 소자의 트랜치 형성 방법을 설명하기 위해 순차적으로 도시한 소자의 단면도.2A to 2D are cross-sectional views of devices sequentially shown to explain a trench forming method of a semiconductor device according to the present invention.

<도면의 주요 부분에 대한 부호 설명><Description of the symbols for the main parts of the drawings>

11, 21 : 실리콘 기판 12, 22 : 패드 산화막11, 21: silicon substrate 12, 22: pad oxide film

13, 23 : 질화막 14, 24 : 감광막 패턴13, 23: nitride film 14, 24: photoresist pattern

25 : 유기 반사 방지막 A, B : 스포트 결함 발생 부분25: organic antireflection film A, B: spot defect generation part

이하, 첨부된 도면을 참조하여 본 발명을 상세히 설명하기로 한다.Hereinafter, with reference to the accompanying drawings will be described in detail the present invention.

도 2a 내지 2d는 본 발명에 따른 반도체 소자의 트랜치 형성 방법을 설명하기 위해 순차적으로 도시한 소자의 단면도이다.2A through 2D are cross-sectional views sequentially illustrating devices for forming trenches in the semiconductor device according to the present invention.

도 2a에 도시된 바와 같이, 실리콘 기판(21) 상부에 패트 산화막(22) 및 질화막(23)을 순차적으로 형성하고, 감광막 패턴(24)을 형성하기 전, 질화막 상부에 유기(organic) 반사 방지막(25)을 형성한다. 이후, 감광막을 코팅한 후 마스크를 이용한 노광 및 현상 공정을 통해 소자분리용 감광막 패턴(24)을 형성한다. 여기에서, 유기 반사 방지막(25)은 200 내지 1000Å의 두께로 형성한다.As shown in FIG. 2A, a pat oxide film 22 and a nitride film 23 are sequentially formed on the silicon substrate 21, and an organic antireflection film is formed on the nitride film before the photoresist pattern 24 is formed. To form 25. Subsequently, the photosensitive film is coated and then the photosensitive film pattern 24 for device isolation is formed through an exposure and development process using a mask. Here, the organic antireflection film 25 is formed to a thickness of 200 to 1000 mW.

도 2b에 도시된 바와 같이, 감광막 패턴(24)을 마스크로 이용한 식각 공정으로 유기 반사 방지막(25)을 패터닝한다. 유기 반사 방지막(25)의 식각 공정시에는 Cl2/O2를 베이스로 사용하고, 과도 식각율을 20 ∼ 100%로 하여 임계 크기를 20nm이하로 제어한다. 감광막 노광 및 현상 공정시 잔류하는 감광막 스컴(scum)은 유기 반사 방지막(25)을 패터닝하는 공정에서 동시에 제거된다.As shown in FIG. 2B, the organic anti-reflection film 25 is patterned by an etching process using the photoresist pattern 24 as a mask. In the etching process of the organic anti-reflection film 25, Cl 2 / O 2 is used as a base, and the critical size is controlled to 20 nm or less with a transient etching rate of 20 to 100%. The photoresist scum remaining during the photoresist exposure and development processes is simultaneously removed in the process of patterning the organic antireflection film 25.

도 2c에 도시된 바와 같이, 감광막 패턴(24)을 마스크로 이용한 식각 공정으로 질화막(23) 및 패드 산화막(22)을 식각한다. 유기 반사 방지막(25) 패터닝을 위한 식각 공정시 감광막 스컴이 제거되었기 때문에 질화막 형성 후 스포트 결함이 발생하지 않는다. 질화막(23)의 제거 시에는 스포트 결함을 제거하기 위해 CHF4/Ar을 베이스로 사용한다. 또한, 실리콘 기판(21)을 식각 타겟으로, 실리콘 기판(21)의 손실이 20 ∼ 200Å이 되도록 제어하여 과도식각한다.As illustrated in FIG. 2C, the nitride film 23 and the pad oxide film 22 are etched by an etching process using the photoresist pattern 24 as a mask. Since the photoresist scum is removed during the etching process for patterning the organic anti-reflection film 25, spot defects do not occur after the nitride film is formed. In removing the nitride film 23, CHF 4 / Ar is used as a base to remove spot defects. In addition, the silicon substrate 21 is used as an etching target, and the silicon substrate 21 is controlled to be over-etched so that the loss of the silicon substrate 21 is 20 to 200 microseconds.

도 2d에 도시된 바와 같이, 패터닝된 질화막(23)을 마스크로 이용한 식각 공정으로 실리콘 기판(21)을 식각하여 트랜치를 형성한다. 이때 실리콘 기판(21)의 식각 타겟은 2000 ∼ 4000Å으로 한다.As illustrated in FIG. 2D, a trench is formed by etching the silicon substrate 21 by an etching process using the patterned nitride layer 23 as a mask. At this time, the etching target of the silicon substrate 21 is set to 2000-4000 kPa.

이후, 감광막 패턴(24) 및 유기 반사 방지막(25)의 제거, 산화막에 의한 트랜치 매립, 질화막(23) 제거 공정 등을 실시하여 소자분리막을 형성하게 된다. 유기 반사 방지막(25)은 일반적인 산소 플라즈마에 의해 제거한다.Subsequently, an isolation layer is formed by removing the photoresist pattern 24 and the organic anti-reflection film 25, forming a trench by an oxide film, and removing the nitride film 23. The organic antireflection film 25 is removed by a general oxygen plasma.

상술한 바와 같이, 본 발명은 감광막을 형성하기 전 유기물로된 반사 방지막을 형성하고 감광막 패턴을 마스크로 이용한 식각 공정으로 유기 반사 방지막을 패터닝할 때 감광막 스컴(scum)이 동시에 제거되므로써, 감광막 스컴으로 인해 트랜치에 발생하는 스포트 결함(spot defect)을 제거할 수 있다. 이로 인하여, 쉘로우 트랜치 소자분리막(STI)을 사용하는 반도체 소자에서 트랜지스터의 패일 율(fail rate)을 감소시킬 수 있으므로 반도체 소자의 개발 기간을 단축시킬 수 있고 소자의 수율을 향상시킬 수 있는 효과가 있다.As described above, in the present invention, the photoresist scum is simultaneously removed when the organic antireflective film is patterned by forming an antireflective film made of organic material before forming the photoresist film and etching the pattern using the photoresist pattern as a mask. This eliminates spot defects in the trench. As a result, in the semiconductor device using the shallow trench isolation layer (STI), the fail rate of the transistor can be reduced, so that the development period of the semiconductor device can be shortened and the yield of the device can be improved. .

Claims (4)

실리콘 기판 상부에 패트 산화막 및 질화막을 순차적으로 형성하고, 전체 구조 상부에 유기 반사 방지막을 형성하는 단계와,Forming a pat oxide film and a nitride film sequentially on the silicon substrate, and forming an organic antireflection film on the entire structure; 상기 유기 반사 방지막 상부에 감광막을 코팅한 후 마스크를 이용한 노광 및 현상 공정을 통해 소자분리용 감광막 패턴을 형성하는 단계와,Forming a photoresist pattern for device isolation through an exposure and development process using a mask after coating the photoresist on the organic antireflection film; 상기 감광막 패턴을 마스크로 이용하여, Cl2/및 O2를 베이스로 사용하고, 과도 식각율을 20 ∼ 100%로 한 식각 공정으로 상기 유기 반사 방지막을 패터닝하는 단계와,Patterning the organic antireflective film using an etching process using Cl 2 / and O 2 as a base and a transient etching rate of 20 to 100% using the photoresist pattern as a mask; 상기 감광막 패턴을 마스크로 이용하여 CHF4및 Ar을 베이스로 사용한 식각 공정으로 상기 질화막을 식각한 후 패드 산화막을 식각하는 단계와,Using the photoresist pattern as a mask to etch the nitride film by an etching process using CHF 4 and Ar as a base, and then etching a pad oxide film; 상기 감광막 패턴을 마스크로 이용하여 상기 실리콘 기판을 식각하는 단계를 포함하여 이루어지는 것을 특징으로 하는 반도체 소자의 트랜치 형성 방법.And etching the silicon substrate by using the photoresist pattern as a mask. 제 1 항에 있어서,The method of claim 1, 상기 유기 반사 방지막은 200 내지 1000Å의 두께로 형성하는 것을 특징으로 하는 반도체 소자의 트랜치 형성 방법.The organic anti-reflection film is a trench forming method of a semiconductor device, characterized in that formed in a thickness of 200 to 1000Å. 제 1 항에 있어서,The method of claim 1, 상기 질화막 및 패드 산화막 식각 공정은 실리콘 기판의 손실이 20 ∼ 200Å이 되도록 제어하여 과도식각하는 것을 특징으로 하는 반도체 소자의 트랜치 형성 방법.The method of forming a trench in a semiconductor device according to claim 1, wherein the nitride film and the pad oxide film etching process are overetched by controlling the silicon substrate to have a loss of 20 to 200 GPa. 제 1 항에 있어서,The method of claim 1, 상기 실리콘 기판은 2000 ∼ 4000Å의 타겟으로 식각하는 것을 특징으로 하는 반도체 소자의 트랜치 형성 방법.The silicon substrate is etched with a target of 2000 to 4000 microns, the trench formation method of a semiconductor device.
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