KR20060131131A - Method for forming micropattern in semiconductor device - Google Patents

Method for forming micropattern in semiconductor device Download PDF

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KR20060131131A
KR20060131131A KR1020050051345A KR20050051345A KR20060131131A KR 20060131131 A KR20060131131 A KR 20060131131A KR 1020050051345 A KR1020050051345 A KR 1020050051345A KR 20050051345 A KR20050051345 A KR 20050051345A KR 20060131131 A KR20060131131 A KR 20060131131A
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amorphous carbon
layer
forming
semiconductor device
carbon film
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KR1020050051345A
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Korean (ko)
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조성윤
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주식회사 하이닉스반도체
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76897—Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31144—Etching the insulating layers by chemical or physical means using masks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823475—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type interconnection or wiring or contact manufacturing related aspects

Abstract

A method for forming a fine pattern in a semiconductor device is provided to prevent damage of an etch target layer and to restrain particles by forming an amorphous carbon layer on the etch target layer. A substrate(10) having an etch target layer(11) is prepared. An amorphous carbon layer(12) is coated on the etch target layer. A silicon oxynitride layer is deposited on the amorphous carbon layer. A groove is formed without exposing the etch target layer by etching selectively the silicon oxynitride layer and the amorphous carbon layer. The silicon oxynitride layer is eliminated. By etching the amorphous carbon layer at the lower of the groove, the etch target layer is exposed. Then, the exposed etch target layer is etched, thereby forming a fine pattern.

Description

반도체 소자의 미세패턴 형성방법{METHOD FOR FORMING MICROPATTERN IN SEMICONDUCTOR DEVICE}METHOD FOR FORMING MICROPATTERN IN SEMICONDUCTOR DEVICE}

도 1 내지 도 7은 본 발명의 바람직한 실시예에 따른 반도체 소자의 미세패턴 형성방법을 도시한 공정 단면도.1 to 7 are cross-sectional views illustrating a method of forming a fine pattern of a semiconductor device in accordance with a preferred embodiment of the present invention.

<도면의 주요 부분에 대한 부호의 설명><Explanation of symbols for the main parts of the drawings>

10 : 반도체 기판10: semiconductor substrate

11 : 피식각층11: etching target layer

12 : 아모르퍼스 카본막12: amorphous carbon film

14 : 실리콘산화질화막14 silicon oxynitride film

16 : 포토레지스트 패턴16: photoresist pattern

18, 20, 24, 26 : 식각공정18, 20, 24, 26: etching process

22 : 홈22: home

28 : 컨택홀28: contact hole

본 발명은 반도체 소자의 미세패턴 형성방법에 관한 것으로, 특히 자기정렬컨택(SAC : self aligned contact) 식각공정을 적용하고 아모르퍼스 카본(amorphous carbon)을 하드마스크로 이용하는 반도체 소자의 미세패턴 형성방법에 관한 것이다. BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of forming a fine pattern of a semiconductor device, and more particularly, to a method of forming a fine pattern of a semiconductor device using a self aligned contact (SAC) etching process and using amorphous carbon as a hard mask. It is about.

반도체 소자는 그 내부에 다수의 단위 소자들을 포함한다. 반도체 소자가 고집적화되면서 일정한 셀(cell) 면적 상에 고밀도로 반도체 소자들을 형성하여야 하며, 이로 인하여 단위 소자, 예를 들면 트랜지스터, 캐패시터의 크기는 점차 감소하고 있다. 특히, DRAM(Dynamic Random Access Memory)과 같은 반도체 메모리 소자에서 디자인 룰(design rule)이 감소하면서 셀의 내부에 형성되는 반도체 소자들의 크기가 점차 감소하고 있다. 실제로 최근 DRAM 소자의 최소 선폭은 0.1㎛ 이하로 형성된다. 따라서, 셀을 이루는 반도체 소자들의 제조공정에 많은 어려움들이 발생하고 있다. The semiconductor device includes a plurality of unit devices therein. As semiconductor devices are highly integrated, semiconductor devices must be formed at a high density on a predetermined cell area, and thus, the size of unit devices, for example, transistors and capacitors, is gradually decreasing. In particular, as a design rule is reduced in a semiconductor memory device such as a DRAM (Dynamic Random Access Memory), the size of semiconductor devices formed in a cell is gradually decreasing. In fact, the minimum line width of the recent DRAM device is formed to less than 0.1㎛. Therefore, many difficulties arise in the manufacturing process of the semiconductor elements forming the cell.

반도체 소자의 미세 패턴 형성방법은 사진식각법(photolithography)을 이용한다. 반도체 소자가 고집적화되어 감에 따라 포토 마스크 공정시 감광막의 두께를 감소시켜야만 하고, 이로 인해 식각공정시 감광막만으로는 하부층 식각이 더욱더 어려워지는 문제점이 있다. 이러한 문제점을 해결하기 위한 일환으로 아모르퍼스 카본(amorphous carbon)을 하드 마스크(hard mask)로 이용한 반도체 소자의 미세패턴 형성방법이 제안되었다. 특히, 최근에는 이러한 아모르퍼스 카본을 이용한 미세 패턴 형성시 식각율이 서로 다른 두 물질 예컨대, 산화막과 질화막 간의 식각 선택비를 이용하여 식각 프로파일을 얻는 자기정렬컨택(SAC : self aligned contact) 식각공정을 적용하고 있다.The method of forming a fine pattern of a semiconductor device uses photolithography. As the semiconductor device is highly integrated, the thickness of the photoresist layer must be reduced during the photomask process, and thus, the etching of the lower layer is more difficult with the photoresist layer only during the etching process. In order to solve this problem, a method of forming a fine pattern of a semiconductor device using amorphous carbon as a hard mask has been proposed. In particular, in recent years, a self aligned contact (SAC) etching process for obtaining an etching profile using an etching selectivity between two materials having different etching rates, for example, an oxide film and a nitride film, when forming a fine pattern using amorphous carbon is performed. It is applied.

그러나, 상기와 같이 SAC 식각공정 및 아모르퍼스 카본을 이용한 미세패턴 형성방법에 따르면, SAC 식각공정시 아모르퍼스 카본막 상의 실리콘산화질화막(SiON막)이 아모르퍼스 카본막과의 높은 식각선택비에 따라 제거되지 않고 잔류하게 된다. 이와 같이 잔류된 SiON막은 후속으로 진행될 아모르퍼스 카본막의 제거시 파티클(particle)을 유발하는 원인으로 작용한다. However, according to the SAC etching process and the fine pattern forming method using amorphous carbon as described above, the silicon oxynitride film (SiON film) on the amorphous carbon film during the SAC etching process according to the high etching selectivity with the amorphous carbon film It is not removed but remains. The remaining SiON film acts as a cause of causing particles when the amorphous carbon film is subsequently removed.

결국, 이러한 파티클을 억제하기 위해서는 SiON막을 제거하는 공정을 별도로 진행해야 하는데, SiON막을 제거하는 공정을 진행하게되면 SiON막의 제거시 패턴이 형성될 피식각층의 노출된 부분이 함께 식각되어 피식각층에 데미지(damage)를 입히거나 패턴 프로파일(profile)이 변형될 우려가 있다.As a result, in order to suppress such particles, a process of removing the SiON film must be separately performed. If the process of removing the SiON film is performed, the exposed portions of the etched layer, which will form a pattern when the SiON film is removed, are etched together and damage to the etching layer There is a risk of damaging or deforming the pattern profile.

따라서, 본 발명은 상기한 종래기술의 문제점을 해결하기 위해 안출된 것으로서, 아모르퍼스 카본을 이용한 미세패턴 형성시 피식각층에 데미지를 입히지 않으면서 파티클 발생을 억제할 수 있는 반도체 소자의 미세패턴 형성방법을 제공하는데 그 목적이 있다. Accordingly, the present invention has been made to solve the problems of the prior art, a method of forming a fine pattern of a semiconductor device which can suppress the generation of particles without damaging the etched layer when forming a fine pattern using amorphous carbon. The purpose is to provide.

상기한 목적을 달성하기 위한 일측면에 따른 본 발명은, 피식각층이 형성된 기판을 제공하는 단계와, 상기 피식각층 상부에 아모르퍼스 카본막을 도포하는 단계와, 상기 아모르퍼스 카본막 상에 실리콘산화질화막을 증착하는 단계와, 상기 피식각층이 노출되지 않도록 상기 실리콘산화질화막 및 상기 아모르퍼스 카본막의 일부영역을 식각하여 홈을 형성하는 단계와, 상기 실리콘산화질화막을 제거하는 단계와, 상기 홈 하부의 상기 아모르퍼스 카본막을 식각하여 상기 피식각층의 일부영역을 노출시키는 단계와, 노출된 영역의 상기 피식각층을 식각하는 단계를 포함하는 반도체 소자의 미세패턴 형성방법을 제공한다.According to an aspect of the present invention, there is provided a substrate on which an etched layer is formed, applying an amorphous carbon film on the etched layer, and a silicon oxynitride film on the amorphous carbon film. Forming a groove by etching a portion of the silicon oxynitride film and the amorphous carbon film so as not to expose the etched layer; and removing the silicon oxynitride film; And etching an amorphous carbon film to expose a portion of the etched layer, and etching the etched layer of the exposed region.

이하, 본 발명이 속하는 기술분야에서 통상의 지식을 가진 자가 본 발명의 기술적 사상을 용이하게 실시할 수 있을 정도로 상세히 설명하기 위하여, 본 발명의 가장 바람직한 실시예를 첨부한 도면을 참조하여 설명한다. 또한, 도면들에 있어서, 층 및 영역들의 두께는 명확성을 기하기 위하여 과장되어진 것이며, 층이 다른 층 또는 기판 "상"에 있다고 언급되어지는 경우에 그것은 다른 층 또는 기판 상에 직접 형성될 수 있거나, 또는 그들 사이에 제3의 층이 개재될 수도 있다. DETAILED DESCRIPTION Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art may easily implement the technical idea of the present invention. In addition, in the drawings, the thicknesses of layers and regions are exaggerated for clarity, and in the case where the layers are said to be "on" another layer or substrate, they may be formed directly on another layer or substrate or Or a third layer may be interposed therebetween.

실시예Example

도 1 내지 도 8은 본 발명의 바람직한 실시예에 따른 반도체 소자의 미세패턴 형성방법을 도시한 공정단면도들이다. 여기서, 도 1 내지 도 8에 도시된 참조부호들 중 동일한 참조부호는 동일한 기능을 수행하는 동일 요소이다.1 to 8 are process cross-sectional views illustrating a method of forming a fine pattern of a semiconductor device according to an exemplary embodiment of the present invention. Here, the same reference numerals among the reference numerals shown in FIGS. 1 to 8 are the same elements performing the same function.

먼저, 도 1에 도시된 바와 같이, 반도체 기판(10) 상에 미세패턴이 형성될 피식각층(11)을 증착한다. 이때, 피식각층(11)은 실리콘 질화막, 실리콘 산화막 또는 실리콘막으로 이루어진다. 이 외에 피식각층(11)은 반도체 소자의 제조공정에 사용되는 질화막, 산화막, 금속층 또는 폴리층일 수도 있다. First, as shown in FIG. 1, the etching target layer 11 on which the micropattern is to be formed is deposited on the semiconductor substrate 10. In this case, the etched layer 11 may be formed of a silicon nitride film, a silicon oxide film, or a silicon film. In addition, the etching target layer 11 may be a nitride film, an oxide film, a metal layer, or a poly layer used in the manufacturing process of the semiconductor device.

이어서, 피식각층(11) 상부에 아모르퍼스 카본막(12)을 도포한다. 이때, 아모르퍼스 카본막(12)은 기존에 도포되는 두께보다 1000 내지 1500Å만큼 더 두껍게 도포한다. 예컨대, 기존에는 1000 내지 1500Å의 두께로 도포되던 아모르퍼스 카본막(12)을 2500 내지 3000Å의 두께로 도포한다.Subsequently, an amorphous carbon film 12 is coated on the etched layer 11. At this time, the amorphous carbon film 12 is applied thicker by 1000 to 1500Å than the conventional thickness. For example, the amorphous carbon film 12, which has been conventionally applied at a thickness of 1000 to 1500 kPa, is applied at a thickness of 2500 to 3000 kPa.

이어서, 아모르퍼스 카본막(12) 상에 실리콘산화질화막(14; SiON)을 증착한다. 이때, SiON(14)은 식각공정시 아모르퍼스 카본막(12)의 손상을 방지하기 위하여 400Å의 두께로 증착한다. 여기서, 도면에 도시되지는 않았지만, 아모르퍼스 카본막(12)과 SiON(14) 간에는 하부 반사방지(BARC : Bottom Anti Reflection Coating)막이 개재될 수 있다. Subsequently, a silicon oxynitride film 14 (SiON) is deposited on the amorphous carbon film 12. At this time, the SiON 14 is deposited to a thickness of 400 kPa to prevent damage to the amorphous carbon film 12 during the etching process. Although not shown in the drawings, a bottom anti reflection coating (BARC) film may be interposed between the amorphous carbon film 12 and the SiON 14.

이어서, 실리콘산화질화막(14) 상에 포토레지스트(미도시)를 도포한 후, 포토마스크(미도시)를 이용한 노광 및 현상공정을 실시하여 포토레지스트 패턴(16)을 형성한다. 이때, 포토레지스트 패턴(16)은 2000Å의 두께로 형성한다.Subsequently, after the photoresist (not shown) is applied onto the silicon oxynitride film 14, an exposure and development process using a photomask (not shown) is performed to form the photoresist pattern 16. At this time, the photoresist pattern 16 is formed to a thickness of 2000 kPa.

이어서, 도 2에 도시된 바와 같이, 포토레지스트 패턴(16)을 식각마스크로 이용한 식각공정(18)을 실시하여 SiON(14, 도 1 참조)을 식각한다. 이때, 식각공정(18)은 건식식각공정으로 실시하는 바, CF4/O2 가스를 이용하여 실시한다.Next, as shown in FIG. 2, an etching process 18 using the photoresist pattern 16 as an etching mask is performed to etch SiON 14 (see FIG. 1). At this time, the etching step 18 is performed by a dry etching step, using a CF 4 / O 2 gas.

이어서, 도 3에 도시된 바와 같이, 스트립(strip) 공정을 실시하여 포토레지 스트 패턴(16, 도 2 참조)을 제거한다.Subsequently, as shown in FIG. 3, a strip process is performed to remove the photoresist pattern 16 (see FIG. 2).

이어서, SiON(14)을 식각마스크로 이용한 식각공정(20)을 실시하여 노출된 아모르퍼스 카본막(12)을 식각한다. 이로써, 아모르퍼스 카본막(12) 내에 홈(22)이 형성된다. 이때, 식각공정(20)은 아모르퍼스 카본막(23)이 홈(22)의 하부에 500Å의 두께로 잔류하도록 H2/N2를 이용하여 실시한다.Subsequently, an etching process 20 using SiON 14 as an etching mask is performed to etch the exposed amorphous carbon film 12. As a result, the grooves 22 are formed in the amorphous carbon film 12. At this time, the etching step 20 is performed using H 2 / N 2 so that the amorphous carbon film 23 remains at the lower portion of the groove 22 at a thickness of 500 kPa.

이어서, 도 4에 도시된 바와 같이, CF4/O2를 이용한 식각공정(24)을 실시하여 잔류하는 SiON(14)을 제거한다.Subsequently, as shown in FIG. 4, an etching process 24 using CF 4 / O 2 is performed to remove the remaining SiON 14.

이어서, 도 5에 도시된 바와 같이, 식각공정(26)을 실시하여 홈(22, 도 4 참조) 하부에 잔류하는 아모르퍼스 카본막(12)을 식각한다. 이때, 아모르퍼스 카본막(12)은 상부로 돌출된 부분에서도 홈(22) 하부에 잔류하는 두께만큼 식각된다. 이로써, 피식각층(11)의 일부영역을 노출시키는 컨택홀(28)이 형성된다. 여기서, 에치백(26) 공정은 N2/H2를 이용하여 실시한다.Subsequently, as shown in FIG. 5, an etching process 26 is performed to etch the amorphous carbon film 12 remaining under the grooves 22 (see FIG. 4). At this time, the amorphous carbon film 12 is etched by the thickness remaining in the lower portion of the groove 22 even in a portion protruding upward. As a result, a contact hole 28 exposing a portion of the etched layer 11 is formed. Here, the etch-back (26) a step is carried out using an N 2 / H 2 in.

여기서, 아모르퍼스 카본막(12)은 기존보다 1000 내지 1500Å만큼 더 두껍게 형성되었으므로, 식각 후 피식각층(11) 상부에 잔류하는 아모르퍼스 카본막(12)의 두께는 기존(1000 내지 1500Å)과 동일하다.Here, since the amorphous carbon film 12 is formed to be thicker by 1000 to 1500 kPa, the thickness of the amorphous carbon film 12 remaining on the etched layer 11 after etching is the same as that of the conventional (1000 to 1500 kPa). Do.

이어서, 도 6에 도시된 바와 같이, 식각된 아모르퍼스 카본막(12)을 하드마스크로 이용한 SAC 식각공정을 실시하여 컨택홀(28, 도 5 참조) 하부로 노출된 피식각층(11)을 식각한다. 여기서, 도 4에서 SiON(14)이 이미 제거되었으므로 SAC 식각공정시 파티클이 유발될 염려가 없다.Subsequently, as shown in FIG. 6, the SAC etching process using the etched amorphous carbon film 12 as a hard mask is performed to etch the etching target layer 11 exposed under the contact hole 28 (see FIG. 5). do. Here, since the SiON 14 is already removed in FIG. 4, there is no fear that particles are generated during the SAC etching process.

이어서, 도 7에 도시된 바와 같이, 아모르퍼스 카본막(12)을 제거한다.Subsequently, as shown in FIG. 7, the amorphous carbon film 12 is removed.

즉, 본 발명의 바람직한 실시예에 따르면, 피식각층 상의 아모르퍼스 카본막을 일정 두께 잔류하도록 식각한 상태에서 아모르퍼스 카본막 상의 SiON을 제거한 후, SAC 식각공정을 실시하여 피식각층에 패턴을 형성함으로써 미세패턴 형성시 발생되는 파티클을 억제할 수 있다. 또한, 피식각층에 데미지를 입히거나 피식각층 패턴 프로파일이 변형되는 문제점을 해결할 수 있다.That is, according to a preferred embodiment of the present invention, after removing the SiON on the amorphous carbon film in a state in which the amorphous carbon film on the etched layer remains to have a predetermined thickness, a SAC etching process is performed to form a pattern in the etched layer. Particles generated during pattern formation can be suppressed. In addition, it is possible to solve the problem of damage to the etched layer or deformation of the etched layer pattern profile.

본 발명의 기술 사상은 바람직한 실시예에서 구체적으로 기술되었으나, 상기한 실시예는 그 설명을 위한 것이며, 그 제한을 위한 것이 아님을 주의하여야 한다. 또한, 본 발명은 이 기술 분야의 통상의 전문가라면 본 발명의 기술 사상의 범위 내에서 다양한 실시예들이 가능함을 이해할 수 있을 것이다.Although the technical spirit of the present invention has been described in detail in the preferred embodiments, it should be noted that the above-described embodiments are for the purpose of description and not of limitation. In addition, it will be understood by those skilled in the art that various embodiments are possible within the scope of the technical idea of the present invention.

이상에서 설명한 바와 같이, 본 발명에 의하면, 피식각층 상의 아모르퍼스 카본막을 일정 두께 잔류하도록 식각한 상태에서 아모르퍼스 카본막 상의 SiON을 제거한 후, SAC 식각공정을 실시하여 피식각층에 패턴을 형성함으로써 피식각층의 데미지 및 패턴 프로파일의 변형이 방지될 수 있다. 또한, 미세패턴 형성시 발생되는 파티클을 억제할 수 있다.As described above, according to the present invention, after removing the SiON on the amorphous carbon film in a state where the amorphous carbon film on the etched layer remains to have a predetermined thickness, a SAC etching process is performed to form a pattern on the etched layer. Damage to each layer and deformation of the pattern profile can be prevented. In addition, it is possible to suppress particles generated when forming a fine pattern.

Claims (8)

피식각층이 형성된 기판을 제공하는 단계;Providing a substrate on which an etched layer is formed; 상기 피식각층 상부에 아모르퍼스 카본막을 도포하는 단계;Coating an amorphous carbon film on the etched layer; 상기 아모르퍼스 카본막 상에 실리콘산화질화막을 증착하는 단계;Depositing a silicon oxynitride film on the amorphous carbon film; 상기 피식각층이 노출되지 않도록 상기 실리콘산화질화막 및 상기 아모르퍼스 카본막의 일부영역을 식각하여 홈을 형성하는 단계;Etching a portion of the silicon oxynitride layer and the amorphous carbon layer to form a groove so that the etched layer is not exposed; 상기 실리콘산화질화막을 제거하는 단계;Removing the silicon oxynitride film; 상기 홈 하부의 상기 아모르퍼스 카본막을 식각하여 상기 피식각층의 일부영역을 노출시키는 단계; 및Etching the amorphous carbon film under the groove to expose a portion of the etched layer; And 노출된 영역의 상기 피식각층을 식각하는 단계Etching the etched layer of the exposed area 를 포함하는 반도체 소자의 미세패턴 형성방법.Method of forming a fine pattern of a semiconductor device comprising a. 제 1 항에 있어서, 상기 홈을 형성하는 단계는,The method of claim 1, wherein the forming of the grooves, 상기 실리콘산화질화막 상에 포토레지스트 패턴을 형성하는 단계;Forming a photoresist pattern on the silicon oxynitride layer; 상기 포토레지스트 패턴을 통해 상기 실리콘산화질화막을 식각하여 상기 아모르퍼스 카본막의 일부 영역을 노출시키는 단계; 및Etching the silicon oxynitride film through the photoresist pattern to expose a portion of the amorphous carbon film; And 상기 아모르퍼스 카본막이 일정두께로 잔류하도록 노출된 부분의 상기 아모르퍼스 카본막을 일정 깊이로 식각하여 상기 홈을 형성하는 단계Etching the amorphous carbon film of the exposed portion to a predetermined depth so that the amorphous carbon film remains at a predetermined thickness to form the grooves 를 포함하는 반도체 소자의 미세패턴 형성방법.Method of forming a fine pattern of a semiconductor device comprising a. 제 2 항에 있어서, The method of claim 2, 잔류하는 상기 아모르퍼스 카본막의 일정두께는 500Å인 반도체 소자의 미세패턴 형성방법.A method of forming a fine pattern of a semiconductor device, wherein the amorphous carbon film has a predetermined thickness of 500 mW. 제 2 항에 있어서,The method of claim 2, 상기 포토레지스트 패턴은 2000Å의 두께로 형성하는 반도체 소자의 미세패턴 형성방법.The photoresist pattern is a fine pattern forming method of a semiconductor device to form a thickness of 2000Å. 제 1 항에 있어서,The method of claim 1, 상기 아모르퍼스 카본막은 2500 내지 3000Å의 두께로 도포하는 반도체 소자의 미세패턴 형성방법.The amorphous carbon film is a method of forming a fine pattern of a semiconductor device to be applied in a thickness of 2500 to 3000Å. 제 1 항에 있어서, The method of claim 1, 상기 실리콘산화질화막은 400Å의 두께로 증착하는 반도체 소자의 미세패턴 형성방법.The silicon oxynitride film is a fine pattern forming method of a semiconductor device which is deposited to a thickness of 400Å. 제 1 항 또는 제 5 항에 있어서, The method according to claim 1 or 5, 상기 아모르퍼스 카본막은 N2/H2를 이용하여 식각하는 반도체 소자의 미세패턴 형성방법.The amorphous carbon film is a method of forming a fine pattern of a semiconductor device is etched using N 2 / H 2 . 제 1 항 또는 제 6 항에 있어서, The method according to claim 1 or 6, 상기 실리콘산화질화막은 CF4/O2를 이용하여 식각하는 반도체 소자의 미세패턴 형성방법.The silicon oxynitride layer is a method of forming a fine pattern of a semiconductor device that is etched using CF 4 / O 2 .
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Publication number Priority date Publication date Assignee Title
WO2019146936A1 (en) * 2018-01-23 2019-08-01 영창케미칼 주식회사 Novel etching method for forming micro silicon pattern in semiconductor manufacturing process

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2019146936A1 (en) * 2018-01-23 2019-08-01 영창케미칼 주식회사 Novel etching method for forming micro silicon pattern in semiconductor manufacturing process
US11315788B2 (en) 2018-01-23 2022-04-26 Young Chang Chemical Co., Ltd Etching method for forming micro silicon pattern in semiconductor manufacturing process

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