KR100895375B1 - The method for manufacturing semiconductor device - Google Patents

The method for manufacturing semiconductor device Download PDF

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Publication number
KR100895375B1
KR100895375B1 KR1020070110738A KR20070110738A KR100895375B1 KR 100895375 B1 KR100895375 B1 KR 100895375B1 KR 1020070110738 A KR1020070110738 A KR 1020070110738A KR 20070110738 A KR20070110738 A KR 20070110738A KR 100895375 B1 KR100895375 B1 KR 100895375B1
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South Korea
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contact hole
dummy
dummy contact
pattern
etching
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KR1020070110738A
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Korean (ko)
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서재욱
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주식회사 하이닉스반도체
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H01L21/76816—Aspects relating to the layout of the pattern or to the size of vias or trenches
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31144—Etching the insulating layers by chemical or physical means using masks
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices

Abstract

A method for manufacturing a semiconductor device is provided to prevent over etching due to a size of a dummy contact hole and to prevent TiN loss and a bunker in a post etch back process by uniformly forming a main contact hole and a CD(Critical Dimension) of the dummy contact hole. A sacrificial dielectric film(110) is formed in an upper part of a semiconductor substrate(100) including a bit line. A first photoresist is formed on the top of the sacrificial dielectric film. A first photoresist pattern defining a dummy contact hole(160) of a dummy cell region(1000a) is formed by performing the exposure and development process. The dummy contact hole to expose the semiconductor substrate is formed by etching the sacrificial dielectric film. The first photoresist pattern is removed. A second photosensitive film reclaiming the dummy contact hole is formed on the top of the whole surface. The reclaiming pattern reclaiming the dummy contact hole and the second photosensitive pattern are formed by performing the exposure and development process for the second photosensitive film. A main contact hole(170) is formed by partly etching the sacrificial dielectric film.

Description

반도체 소자의 형성 방법{The Method for Manufacturing Semiconductor Device}The method for manufacturing a semiconductor device

도 1a 내지 도 1c는 종래 기술에 따른 반도체 소자의 형성 방법의 문제점을 도시한 사진도.1A to 1C are photographs showing problems of the method of forming a semiconductor device according to the prior art.

도 2a 내지 도 2f는 본 발명에 따른 반도체 소자의 형성 방법을 도시한 단면도.2A to 2F are cross-sectional views illustrating a method of forming a semiconductor device in accordance with the present invention.

<도면의 주요 부분에 대한 부호 설명>          <Description of the symbols for the main parts of the drawings>

100: 반도체 기판 110: 절연막100: semiconductor substrate 110: insulating film

120: 제 1 감광막 130: 제 1 감광막 패턴120: first photosensitive film 130: first photosensitive film pattern

140: 제 2 감광막 150: 제 2 감광막 패턴140: second photosensitive film 150: second photosensitive film pattern

160: 더미 콘택홀 170: 메인 콘택홀 160: dummy contact hole 170: main contact hole

1000a: 더미 셀(Dummy Cell) 영역 1000b: 메인 셀(Main Cell) 영역 1000a: dummy cell area 1000b: main cell area

본 발명은 반도체 소자의 형성 방법에 관한 것으로, 더미 콘택홀과 메인 콘택홀 사이즈를 동일하게 패터닝하여 더미 콘택홀을 먼저 형성한다. 다음에, 더미 콘택홀과 메인 콘택홀을 동시에 마스크 공정과 에칭 공정을 실시하여 후속 딥 아웃(Dip Out) 공정 시 더미 콘택홀을 제 2 감광막으로 보호함으로써, 더미 콘택홀의 크기로 인한 오버 에칭(Over Etching)를 방지하고, 메인 콘택홀과 더미 콘택홀의 CD가 균일하여 후속 에치 백(Etch Back) 공정 시 TiN 손실(Loss) 및 벙커(Bunker) 발생을 방지하는 기술을 개시한다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of forming a semiconductor device, wherein a dummy contact hole is first formed by patterning the dummy contact hole and the main contact hole in the same size. Next, the dummy contact hole and the main contact hole are simultaneously masked and etched to protect the dummy contact hole with the second photoresist during the subsequent dip out process, thereby over-etching due to the size of the dummy contact hole. The present invention discloses a technique of preventing etching and preventing uniformity of TiN loss and bunker during subsequent etch back processes because the CDs of the main contact hole and the dummy contact hole are uniform.

최근 반도체 소자의 응용 분야가 확장됨에 따라, 집적도 및 전기적 특성이 향상된 반도체 소자를 제조하기 위한 공정 설비 또는 공정 기술의 개발이 절실히 요구되고 있다. Recently, as the application field of semiconductor devices is expanded, development of process facilities or process technologies for manufacturing semiconductor devices having improved integration and electrical characteristics is urgently required.

특히, 반도체 메모리 중에서 DRAM(Dynamic Random Access Memory)은 정보를 자유롭게 기입하고 판독할 수 있는 메모리로서, 하나의 트랜스퍼 트랜지스터와 하나의 트랜지스터 타입의 메모리 셀인 커패시터로 구성되어 있다. In particular, DRAM (Dynamic Random Access Memory) is a memory that can freely write and read information, and is composed of one transfer transistor and one transistor type memory cell.

상기 커패시터는 스토리지 노드(Storage node)와 플레이트 노드(Plate node) 사이에 유전체막(Dielectric)이 개재된 구조를 포함한다. The capacitor includes a structure in which a dielectric film is interposed between a storage node and a plate node.

한편, 반도체 메모리 소자의 집적도 증가로 소자 크기가 점차 감소함에 따라, 충분한 정전 용량을 확보할 수 있는 커패시터를 제조하는 것이 점점 어려워졌다. On the other hand, as the device size gradually decreases due to the increase in the degree of integration of semiconductor memory devices, it is increasingly difficult to manufacture capacitors capable of securing sufficient capacitance.

이에 따라, 커패시터의 정전 용량을 확보하기 위하여 트렌치 타입(Trench type)이나, 실린더 타입(Cylinder type)과 같은 3차원 커패시터 구조가 도입되었다. Accordingly, in order to secure the capacitance of the capacitor, a three-dimensional capacitor structure such as a trench type or a cylinder type has been introduced.

종래의 실린더 타입(Cylinder type)과 같은 커패시터 구조에서 포토리소그래 피 공정상에서 프로세스 마진(Process Margin)을 확보하기 위해서는 최 외곽 더미 셀(Dummy Cell) 홀의 CD(Critical Dimension)를 넓혀야 한다.In order to secure a process margin in a photolithography process in a capacitor structure such as a conventional cylinder type, the CD (Critical Dimension) of the outermost dummy cell hole should be widened.

하지만, 이러한 더미 셀(Dummy Cell) 홀의 사이즈가 메인 셀(Main Cell) 홀의 사이즈보다 크게 형성되기 때문에 더미 셀 홀에서 오버 에치(Over Etch)가 발생하고, 하부 전극 TiN에 어택(Attack)을 유발한다.However, since the size of the dummy cell hole is larger than the size of the main cell hole, overetch occurs in the dummy cell hole, causing an attack on the lower electrode TiN. .

이후, 딥 아웃(Dip Out) 공정 시 어택(Attack)을 받은 더미 셀 홀을 통해 화학물(Chemical)이 침투하면서 홀(Hole) 하부의 산화막 로스(Loss)가 발생한다.Subsequently, as the chemical penetrates through the dummy cell hole subjected to the attack during the dip out process, an oxide loss of the lower portion of the hole is generated.

이러한 산화막의 로스(Loss)로 인해 주변 회로 영역의 비트 라인 쓰러짐(Collapse)을 유발하여 디시(DC) 불량, 바이어스(Bias) 불량 및 기능(Function) 불량 등과 같은 현상이 발생한다.Due to the loss of the oxide layer, bit line collapse of the peripheral circuit area may occur, such as a bad DC, a bad bias, and a bad function.

도 1a 내지 도 1c는 종래 기술에 따른 반도체 소자의 형성 방법의 문제점을 도시한 사진이다.1A to 1C are photographs showing a problem of a method of forming a semiconductor device according to the prior art.

도 1a를 참조하면, 메인 콘택홀과 더미 콘택홀의 크기를 비교한 사진이다.Referring to FIG. 1A, it is a photograph comparing sizes of a main contact hole and a dummy contact hole.

포토 마스크 공정의 마진(Margin)을 확보하기 위해 상기 더미 콘택홀의 크기가 메인 콘택홀 보다 큰 사진을 도시한 것이다. The dummy contact hole is larger in size than the main contact hole in order to secure a margin of the photo mask process.

도 1b를 참조하면, 더미 콘택홀의 사이즈가 크기 때문에 더미 콘택홀 영역에 오버 에칭(Over Etching)이 발생한 것을 알 수 있다.Referring to FIG. 1B, it can be seen that overetching has occurred in the dummy contact hole region because the size of the dummy contact hole is large.

도 1c를 참조하면, 후속 공정으로 TiN 증착 및 에치백 공정을 실시하게 되면 더미 콘택홀은 CD(Critical Dimension)가 커서 TiN 손실(Loss)이 발생하게 된다.Referring to FIG. 1C, when the TiN deposition and etch back processes are performed in a subsequent process, the dummy contact hole has a large CD (Critical Dimension) and thus loses TiN (Loss).

이후, 딥 아웃(Dip Out) 공정을 실시하면 습식 화학물(Wet Chemical)이 침투 하여 벙커(Bunker)가 발생하는 문제가 있다.Subsequently, when the dip out process is performed, wet chemical penetrates into a bunker.

본 발명은 반도체 소자의 형성 방법에 관한 것으로, 더미 콘택홀과 메인 콘택홀 사이즈를 동일하게 패터닝하여 더미 콘택홀을 먼저 형성한다. 다음에, 더미 콘택홀과 메인 콘택홀을 동시에 마스크 공정과 에칭 공정을 실시하여 후속 딥 아웃(Dip Out) 공정 시 더미 콘택홀을 제 2 감광막으로 보호함으로써, 더미 콘택홀의 크기로 인한 오버 에칭(Over Etching)를 방지하고, 메인 콘택홀과 더미 콘택홀의 CD가 균일하여 후속 에치 백(Etch Back) 공정 시 TiN 손실(Loss) 및 벙커(Bunker) 발생을 방지할 수 있도록 하는 반도체 소자의 형성 방법을 제공하는 것을 목적으로 한다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of forming a semiconductor device, wherein a dummy contact hole is first formed by patterning the dummy contact hole and the main contact hole in the same size. Next, the dummy contact hole and the main contact hole are simultaneously masked and etched to protect the dummy contact hole with the second photoresist during the subsequent dip out process, thereby over-etching due to the size of the dummy contact hole. It provides a method of forming a semiconductor device that prevents etching and prevents TiN loss and bunker generation during the subsequent etch back process because the CDs of the main contact hole and the dummy contact hole are uniform. It aims to do it.

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본 발명은 반도체 기판 상부에 희생 절연막을 형성하는 단계, 상기 희생 절연막 상에 더미 콘택홀 마스크를 이용한 노광 및 현상 공정으로 제 1 감광막 패턴을 형성하는 단계, 상기 희생 절연막을 식각하여 더미 셀 영역에 더미 콘택홀을 형성하는 단계, 상기 더미 콘택홀을 매립하는 매립 패턴과 제 2 감광막 패턴을 형성하되, 상기 제 2 감광막 패턴은 메인 셀 영역에 메인 콘택홀을 정의하며 상기 더미 셀 영역에 상기 매립 패턴과 상기 매립 패턴 주위의 상기 희생 절연막을 노출시키는 단계, 상기 제 2 감광막 패턴을 마스크로 상기 희생 절연막을 식각하는 단계 및 상기 제 2 감광막 패턴 및 상기 매립 패턴을 제거하는 단계를 포함하는 반도체 소자의 형성 방법을 제공한다.
여기서, 상기 더미 콘택홀은 메인 콘택홀의 사이즈와 동일하게 형성하는 것과,According to an embodiment of the present invention, a sacrificial insulating film is formed on a semiconductor substrate, a first photoresist pattern is formed on the sacrificial insulating film by an exposure and development process using a dummy contact hole mask, and the sacrificial insulating film is etched to dummy the dummy cell region. Forming a contact hole, and forming a buried pattern and a second photoresist pattern filling the dummy contact hole, wherein the second photoresist pattern defines a main contact hole in a main cell region and the buried pattern in the dummy cell region. Exposing the sacrificial insulating film around the buried pattern, etching the sacrificial insulating film using the second photoresist pattern as a mask, and removing the second photoresist pattern and the buried pattern. To provide.
Here, the dummy contact hole is formed to be the same as the size of the main contact hole,

상기 더미 콘택홀을 매립하는 감광막은 식각 장벽층으로 사용되는 것을 특징으로 한다.The photoresist film filling the dummy contact hole may be used as an etching barrier layer.

이하, 본 발명이 속하는 기술분야에서 통상의 지식을 가진 자가 본 발명의 기술적 사상을 용이하게 실시할 수 있을 정도로 상세히 설명하기 위하여, 본 발명의 가장 바람직한 실시 예를 첨부한 도면을 참조하여 설명한다. DETAILED DESCRIPTION Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art may easily implement the technical idea of the present invention.

또한, 도면들에 있어서, 층 및 영역들의 두께는 명확성을 기하기 위하여 과장 된 것이며, 층이 다른 층 또는 기판 "상"에 있다고 언급된 경우에 그것은 다른 층 또는 기판상에 직접 형성될 수 있거나, 또는 그들 사이에 제 3의 층이 개재될 수도 있다. In addition, in the drawings, the thicknesses of layers and regions are exaggerated for clarity, and if it is mentioned that the layer is on another layer or substrate it may be formed directly on another layer or substrate, Alternatively, a third layer may be interposed therebetween.

또한, 명세서 전체에 걸쳐서 동일한 참조 번호가 표시된 부분은 동일한 구성요소들을 나타낸다.Also, the same reference numerals throughout the specification represent the same components.

도 2a 내지 도 2f는 본 발명에 따라 형성된 반도체 소자를 도시한 단면도이다.2A through 2F are cross-sectional views illustrating semiconductor devices formed in accordance with the present invention.

도 2a를 참조하면, 더미 셀 영역(1000a)과 메인 셀 영역(1000b)을 정의하는 반도체 기판(100) 상에 활성 영역을 정의하는 소자분리막이 형성되며, 그 상부에 게이트로 구성되는 워드 라인이 형성된다.Referring to FIG. 2A, an isolation layer defining an active region is formed on a semiconductor substrate 100 defining a dummy cell region 1000a and a main cell region 1000b, and a word line configured as a gate is formed thereon. Is formed.

여기서, 워드 라인에 의해서 3 분할된 활성 영역 중에 양 에지(Edge) 부에 스토리지 노드 콘택홀이 형성되며, 활성 영역의 중심부에는 비트라인 콘택홀이 형성된다. Here, the storage node contact hole is formed at both edges of the active region divided by the word line, and the bit line contact hole is formed at the center of the active region.

이때, 비트라인 콘택홀은 반도체 소자의 전기적 특성 및 공정 마진을 향상시키기 위하여 타원형으로 형성된다.At this time, the bit line contact hole is formed in an elliptical shape in order to improve the electrical characteristics and the process margin of the semiconductor device.

다음으로, 스토리지 노드 콘택홀 및 비트라인 콘택홀에 폴리실리콘층을 매립하여 스토리지 노드 콘택 플러그 및 비트라인 콘택 플러그를 형성한다.Next, a polysilicon layer is embedded in the storage node contact hole and the bit line contact hole to form the storage node contact plug and the bit line contact plug.

상기 비트라인 콘택 플러그 상에 비트라인을 형성한다.A bit line is formed on the bit line contact plug.

상기 비트라인 상부에 희생 절연막(110)을 형성하고, 상기 희생 절연막(110) 상부에 제 1 감광막(120)을 형성한다.A sacrificial insulating layer 110 is formed on the bit line, and a first photoresist layer 120 is formed on the sacrificial insulating layer 110.

도 2b를 참조하면, 상기 제 1 감광막(120)을 노광 마스크를 이용한 노광 및 현상 공정으로 더미 셀 영역(1000a)의 더미 콘택홀(160)을 정의하는 제 1 감광막 패턴(130)을 형성한다.Referring to FIG. 2B, a first photoresist layer pattern 130 defining a dummy contact hole 160 of the dummy cell region 1000a may be formed by exposing and developing the first photoresist layer 120 using an exposure mask.

도 2c를 참조하면, 상기 제 1 감광막 패턴(130)을 마스크로 희생 절연막(110)을 식각하여 반도체 기판(100)을 노출시키는 더미 콘택홀(160)을 형성한다.Referring to FIG. 2C, the sacrificial insulating layer 110 is etched using the first photoresist pattern 130 as a mask to form a dummy contact hole 160 exposing the semiconductor substrate 100.

다음에, 제 1 감광막 패턴(130)을 제거한다.Next, the first photosensitive film pattern 130 is removed.

이때, 더미 콘택홀(160)의 사이즈는 후속 공정으로 형성될 메인 콘택 홀의 사이즈와 동일하게 형성하는 것이 바람직하다.In this case, the size of the dummy contact hole 160 is preferably the same as the size of the main contact hole to be formed in a subsequent process.

그 다음에, 더미 콘택홀(160)을 매립하는 제 2 감광막(140)을 전체 표면 상부에 형성한다.Next, a second photosensitive film 140 filling the dummy contact hole 160 is formed over the entire surface.

도 2d를 참조하면, 제 2 감광막(140)을 노광 마스크를 이용한 노광 및 현상하여 메인 셀 영역(1000b)에 메인 콘택홀(170)을 정의하며 더미 콘택홀을 매립하는 매립 패턴(155)과 더미 셀 영역에 더미 콘택홀(도 2c의 160)보다 넓은 폭을 갖는 제 2 감광막 패턴(150)을 형성한다.Referring to FIG. 2D, the second photoresist layer 140 is exposed and developed using an exposure mask to define the main contact hole 170 in the main cell region 1000b and to fill the dummy contact hole with the buried pattern 155 and the dummy. A second photoresist pattern 150 having a width wider than that of the dummy contact hole (160 in FIG. 2C) is formed in the cell region.

도 2e 및 도 2f를 참조하면, 제 2 감광막 패턴(150)을 마스크로 희생 절연막(110)을 일부 식각하여 더미 셀 영역(1000a)의 매립 패턴(155) 주위의 희생 절연막은 일부 식각되고 메인 셀 영역(1000b)의 희생 절연막(110)은 반도체 기판을 노출시키도록 식각되어 메인 콘택홀(170)이 형성된다. 더미 콘택홀(160)의 매립 패턴(155) 주위의 희생 절연막(110)은 메인 콘택홀을 형성하기 위한 메인 셀 영역(1000b)의 희생 절연막(110)보다 식각 속도가 느리고 반도체 기판(100)이 완전히 노출될 때까지 식각되지 않는다. 이후, 제 2 감광막 패턴(150) 및 매립 패턴(155)을 제거하여 메인 콘택홀(170)보다 더 넓은 폭의 상측 CD를 갖는 더미 콘택홀을 완성한다.2E and 2F, the sacrificial insulating layer 110 is partially etched using the second photoresist pattern 150 as a mask to partially etch the sacrificial insulating layer around the buried pattern 155 of the dummy cell region 1000a and the main cell. The sacrificial insulating layer 110 in the region 1000b is etched to expose the semiconductor substrate to form a main contact hole 170. The sacrificial insulating layer 110 around the buried pattern 155 of the dummy contact hole 160 has a lower etching rate than the sacrificial insulating layer 110 of the main cell region 1000b for forming the main contact hole, and the semiconductor substrate 100 It is not etched until it is fully exposed. Thereafter, the second photoresist layer pattern 150 and the buried pattern 155 are removed to complete the dummy contact hole having a wider upper CD than the main contact hole 170.

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본 발명은 반도체 소자의 형성 방법에 관한 것으로, 더미 콘택홀의 크기로 인한 오버 에칭(Over Etching)를 방지하고, 메인 콘택홀과 더미 콘택홀의 CD가 균일하여 후속 에치 백(Etch Back) 공정 시 TiN 손실(Loss) 및 벙커(Bunker) 발생을 방지할 수 있는 효과를 제공한다.The present invention relates to a method of forming a semiconductor device, and prevents over etching due to the size of the dummy contact hole, and the uniformity of the CDs of the main contact hole and the dummy contact hole causes TiN loss during the subsequent etch back process. (Loss) and bunker (Bunker) to prevent the effect is provided.

아울러 본 발명의 바람직한 실시 예는 예시의 목적을 위한 것으로, 당업자라면 첨부된 특허청구범위의 기술적 사상과 범위를 통해 다양한 수정, 변경, 대체 및 부가가 가능할 것이며, 이러한 수정 변경 등은 이하의 특허청구범위에 속하는 것으로 보아야 할 것이다.     In addition, the preferred embodiment of the present invention for the purpose of illustration, those skilled in the art will be able to various modifications, changes, substitutions and additions through the spirit and scope of the appended claims, such modifications and changes are the following claims It should be seen as belonging to a range.

Claims (3)

반도체 기판 상부에 희생 절연막을 형성하는 단계;Forming a sacrificial insulating film on the semiconductor substrate; 상기 희생 절연막 상에 더미 콘택홀 마스크를 이용한 노광 및 현상 공정으로 제 1 감광막 패턴을 형성하는 단계;Forming a first photoresist pattern on the sacrificial insulating layer by an exposure and development process using a dummy contact hole mask; 상기 희생 절연막을 식각하여 더미 셀 영역에 더미 콘택홀을 형성하는 단계;Etching the sacrificial insulating layer to form a dummy contact hole in the dummy cell region; 상기 더미 콘택홀을 매립하는 매립 패턴과 제 2 감광막 패턴을 형성하되, 상기 제 2 감광막 패턴은 메인 셀 영역에 메인 콘택홀을 정의하며 상기 더미 셀 영역에 상기 매립 패턴과 상기 매립 패턴 주위의 상기 희생 절연막을 노출시키는 단계;Forming a buried pattern and a second photoresist pattern filling the dummy contact hole, wherein the second photoresist pattern defines a main contact hole in a main cell region and the sacrificial pattern around the buried pattern and the buried pattern in the dummy cell region Exposing the insulating film; 상기 제 2 감광막 패턴을 마스크로 상기 희생 절연막을 식각하는 단계; 및Etching the sacrificial insulating layer using the second photoresist pattern as a mask; And 상기 제 2 감광막 패턴 및 상기 매립 패턴을 제거하는 단계Removing the second photoresist pattern and the buried pattern 를 포함하는 반도체 소자의 형성 방법.Method of forming a semiconductor device comprising a. 제 1 항에 있어서,The method of claim 1, 상기 더미 콘택홀은 메인 콘택홀의 사이즈와 동일하게 형성하는 것을 특징으로 하는 반도체 소자의 형성 방법.The dummy contact hole may be formed to have the same size as a main contact hole. 제 1 항에 있어서,The method of claim 1, 상기 더미 콘택홀을 매립하는 감광막은 식각 장벽층으로 사용되는 것을 특징으로 하는 반도체 소자의 형성 방법.The photosensitive film filling the dummy contact hole is used as an etching barrier layer.
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