KR20020002630A - A method for forming a gate electrode of a semiconductor device - Google Patents
A method for forming a gate electrode of a semiconductor device Download PDFInfo
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- KR20020002630A KR20020002630A KR1020000036856A KR20000036856A KR20020002630A KR 20020002630 A KR20020002630 A KR 20020002630A KR 1020000036856 A KR1020000036856 A KR 1020000036856A KR 20000036856 A KR20000036856 A KR 20000036856A KR 20020002630 A KR20020002630 A KR 20020002630A
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- 238000000034 method Methods 0.000 title claims abstract description 53
- 239000004065 semiconductor Substances 0.000 title claims abstract description 25
- 229910052721 tungsten Inorganic materials 0.000 claims abstract description 43
- 239000010937 tungsten Substances 0.000 claims abstract description 43
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 claims abstract description 40
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 claims abstract description 27
- 230000004888 barrier function Effects 0.000 claims abstract description 24
- 238000009792 diffusion process Methods 0.000 claims abstract description 24
- 229910008807 WSiN Inorganic materials 0.000 claims abstract description 12
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 12
- 239000010703 silicon Substances 0.000 claims abstract description 12
- QGZKDVFQNNGYKY-UHFFFAOYSA-N ammonia Natural products N QGZKDVFQNNGYKY-UHFFFAOYSA-N 0.000 claims abstract description 10
- 229910052757 nitrogen Inorganic materials 0.000 claims abstract description 10
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 9
- 238000010438 heat treatment Methods 0.000 claims abstract description 8
- 239000000758 substrate Substances 0.000 claims abstract description 8
- 229910001873 dinitrogen Inorganic materials 0.000 claims abstract description 7
- 229910021529 ammonia Inorganic materials 0.000 claims abstract description 4
- 150000003376 silicon Chemical class 0.000 claims abstract description 3
- 239000007943 implant Substances 0.000 claims description 13
- 238000005530 etching Methods 0.000 claims description 6
- 238000000137 annealing Methods 0.000 claims description 2
- 238000000059 patterning Methods 0.000 claims description 2
- 230000015572 biosynthetic process Effects 0.000 claims 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 abstract description 22
- 229920005591 polysilicon Polymers 0.000 abstract description 21
- WQJQOUPTWCFRMM-UHFFFAOYSA-N tungsten disilicide Chemical compound [Si]#[W]#[Si] WQJQOUPTWCFRMM-UHFFFAOYSA-N 0.000 abstract description 6
- 229910021342 tungsten silicide Inorganic materials 0.000 abstract description 6
- 238000009413 insulation Methods 0.000 abstract 2
- 238000005229 chemical vapour deposition Methods 0.000 abstract 1
- 238000002513 implantation Methods 0.000 abstract 1
- 239000012535 impurity Substances 0.000 description 5
- 125000006850 spacer group Chemical group 0.000 description 3
- -1 tungsten nitride Chemical class 0.000 description 3
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 description 2
- 239000007789 gas Substances 0.000 description 2
- 239000011800 void material Substances 0.000 description 2
- 229910021417 amorphous silicon Inorganic materials 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 230000006698 induction Effects 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 238000001459 lithography Methods 0.000 description 1
- 238000002844 melting Methods 0.000 description 1
- 230000008018 melting Effects 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/28008—Making conductor-insulator-semiconductor electrodes
- H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
- H01L21/28026—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
- H01L21/28035—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities
- H01L21/28044—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities the conductor comprising at least another non-silicon conductive layer
- H01L21/28061—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities the conductor comprising at least another non-silicon conductive layer the conductor comprising a metal or metal silicide formed by deposition, e.g. sputter deposition, i.e. without a silicidation reaction
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
- H01L29/4916—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a silicon layer, e.g. polysilicon doped with boron, phosphorus or nitrogen
- H01L29/4925—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a silicon layer, e.g. polysilicon doped with boron, phosphorus or nitrogen with a multiple layer structure, e.g. several silicon layers with different crystal structure or grain arrangement
- H01L29/4941—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a silicon layer, e.g. polysilicon doped with boron, phosphorus or nitrogen with a multiple layer structure, e.g. several silicon layers with different crystal structure or grain arrangement with a barrier layer between the silicon and the metal or metal silicide upper layer, e.g. Silicide/TiN/Polysilicon
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- Microelectronics & Electronic Packaging (AREA)
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- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Chemical & Material Sciences (AREA)
- Chemical Kinetics & Catalysis (AREA)
- Manufacturing & Machinery (AREA)
- Crystallography & Structural Chemistry (AREA)
- Ceramic Engineering (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
- Electrodes Of Semiconductors (AREA)
Abstract
Description
본 발명은 반도체소자의 게이트전극 형성방법에 관한 것으로, 특히 폴리실리콘과 텅스텐의 적층구조로 게이트전극을 형성하는데 있어서, 확산방지막을 형성하기 위해 기존의 텅스텐 질화막 증착 대신 텅스텐 증착후 질소 임플란트를 텅스텐과 폴리실리콘의 계면에 피크 ( peak ) 가 오도록 수행한 후 후속 열처리공정에 의해 계면에 확산방지막(WSiN)을 형성하는 방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of forming a gate electrode of a semiconductor device. In particular, in forming a gate electrode in a laminated structure of polysilicon and tungsten, a tungsten nitride-deposited nitrogen implant is replaced with tungsten instead of conventional tungsten nitride to form a diffusion barrier The present invention relates to a method of forming a diffusion barrier film (WSiN) at an interface by performing a heat treatment after a peak at a polysilicon interface.
최근 반도체 소자의 집적화 및 고속화에 따라 게이트전극으로서 도핑된 다결정실리콘이나 폴리사이드 구조 대신 비저항이 낮은 텅스텐 등의 고융점 금속을 다결정실리콘 상부에 증착하여 게이트전극으로 사용하는 방법이 제안되어 있다.Recently, a method of using a gate electrode by depositing a high melting point metal such as tungsten with low specific resistance on top of polycrystalline silicon instead of a polysilicon doped as a gate electrode or a polyside structure as a semiconductor device is integrated and speeded up has been proposed.
이러한 방법은 텅스텐과 실리콘이 직접 접촉할 경우 후속 고온 공정에서 서로 반응하여 텅스텐 실리사이드가 형성되므로 본래 목적이 텅스텐의 낮은 비저항을 이용하는 것이 불가능하게 된다.This method makes it impossible to take advantage of the low resistivity of tungsten because the direct contact between tungsten and silicon reacts with each other in subsequent high temperature processes to form tungsten silicide.
이러한 현상을 방지하기 위해 텅스텐과 폴리실리콘 사이에 텅스텐 질화막이나 티타늄 질화막 등의 확산방지막을 형성시켜 주는 방법이 가장 보편적으로 이용된다.In order to prevent such a phenomenon, a method of forming a diffusion barrier such as a tungsten nitride film or a titanium nitride film between tungsten and polysilicon is most commonly used.
그러나, 상기 티타늄 질화막을 사용하는 경우는 후속 공정에서 선택 산화시킬 수 없다는 문제점이 있고, 텅스텐질화막을 사용하는 경우는 기존에 특허 출원이 되어 있어 새로운 방법이 필요하다.However, when the titanium nitride film is used, there is a problem in that it cannot be selectively oxidized in a subsequent process, and when the tungsten nitride film is used, a patent method has been applied and a new method is required.
한편, 상기 확산방지막을 형성하는 새로운 방법으로서는, 폴리실리콘 상부에 텅스텐을 증착하고 NH3 가스 분위기에 열처리하여 상기 NH3 의 N 이 텅스텐층으로 확산하여 텅스텐과 폴리실리콘 사이에 확산방지막인 WSiN을 형성한다.On the other hand, as a new method of forming the diffusion barrier, tungsten is deposited on polysilicon and heat-treated in an NH 3 gas atmosphere, whereby N of NH 3 diffuses into the tungsten layer to form WSiN, a diffusion barrier between tungsten and polysilicon.
그러나, 상기 확산방지막은 하부층의 상태에 따라 확산방지막의 특성이 열화되는 문제점이 있다.However, the diffusion barrier has a problem in that the characteristics of the diffusion barrier is deteriorated depending on the state of the lower layer.
도 1 은 종래기술에 따른 반도체소자의 게이트전극 형성방법을 도시한 단면도이다.1 is a cross-sectional view showing a gate electrode forming method of a semiconductor device according to the prior art.
먼저, 반도체기판(11) 상부에 게이트산화막(13)을 증착하고 그 상부에 게이트전극용 폴리실리콘막(15), 텅스텐막(19)을 순차적으로 적층한다.First, the gate oxide film 13 is deposited on the semiconductor substrate 11, and the polysilicon film 15 and the tungsten film 19 for the gate electrode are sequentially stacked thereon.
그리고, NH3 분위기에서 열처리하여 상기 폴리실리콘막(15)과 텅스텐막(19) 계면에 확산방지막(17)인 WSiN을 형성한다.Heat treatment in an NH 3 atmosphere forms WSiN as a diffusion barrier 17 at the interface between the polysilicon film 15 and the tungsten film 19.
이때, 상기 폴리실리콘막(15)의 상측에 보이드 ( void )(23)가 형성되고, 상기 확산방지막(17)에 국부적으로 텅스텐 실리사이드(25)이 형성된다.In this case, a void 23 is formed on the polysilicon film 15, and tungsten silicide 25 is locally formed on the diffusion barrier 17.
그 다음, 상기 적층구조 상부에 하드마스크층인 CVD 절연막(21)을 형성한다.Next, a CVD insulating film 21 as a hard mask layer is formed on the stacked structure.
그리고, 게이트전극 마스크를 이용한 식각공정으로 상기 CVD 절연막(21), 텅스텐막(19), 확산방지막(17) 및 폴리실리콘막(15)을 순차적으로 식각하여 패터닝한다. (도 1)The CVD insulating film 21, the tungsten film 19, the diffusion barrier film 17, and the polysilicon film 15 are sequentially etched and patterned by an etching process using a gate electrode mask. (Figure 1)
따라서, 본 발명의 상기한 종래기술의 문제점을 해결하기위하여, SEG 공정을 이용하여 리소그래피공정의 한계를 극복할 수 있는 미세패턴을 형성함으로써 반도체소자의 고집적화를 가능하게 하는 반도체소자의 게이트전극 형성방법을 제공하는데 그 목적이 있다.Therefore, in order to solve the above problems of the prior art of the present invention, a method of forming a gate electrode of a semiconductor device that enables high integration of the semiconductor device by forming a fine pattern that can overcome the limitations of the lithography process using the SEG process. The purpose is to provide.
도 1 은 종래기술에 따른 반도체소자의 게이트전극 형성방법을 도시한 단면도.1 is a cross-sectional view showing a gate electrode forming method of a semiconductor device according to the prior art.
도 2a 내지 도 2f 는 본 발명의 실시예에 따른 반도체소자의 게이트전극 형성방법을 도시한 단면도.2A to 2F are cross-sectional views illustrating a method of forming a gate electrode of a semiconductor device according to an embodiment of the present invention.
< 도면의 주요부분에 대한 부호의 설명 ><Description of Symbols for Major Parts of Drawings>
11,31 : 반도체기판 13,33 : 게이트전극11,31: semiconductor substrate 13,33: gate electrode
15,35 : 폴리실리콘막 17,39 : 확산방지막(WSiN)15,35 polysilicon film 17,39 diffusion barrier film (WSiN)
19,37 : 텅스텐막 21,41 : CVD 절연막19,37 tungsten film 21,41 CVD insulating film
23 : 보이드 25 : 텅스텐 실리사이드23: void 25: tungsten silicide
43 : 절연막 스페이서43: insulating film spacer
이상의 목적을 달성하기 위해 본 발명에 따른 반도체소자의 게이트전극 형성방법은,In order to achieve the above object, the gate electrode forming method of a semiconductor device according to the present invention,
반도체기판 상부에 실리콘막과 텅스텐막의 적층구조를 형성하는 공정과,Forming a stacked structure of a silicon film and a tungsten film on the semiconductor substrate;
상기 실리콘막과 텅스텐막의 계면에 N2 또는 N를 임플란트하고 암모니아가스나 질소가스 분위기에서 열처리하여 상기 계면에 확산방지막(WSiN)을 형성하는 공정과,Implanting N2 or N at the interface between the silicon film and the tungsten film and heat-treating in an ammonia or nitrogen gas atmosphere to form a diffusion barrier film (WSiN) at the interface;
상기 텅스텐막 상부에 하드마스크층인 CVD 절연막을 형성하는 공정과,Forming a CVD insulating film as a hard mask layer on the tungsten film;
게이트전극 마스크를 이용한 식각공정으로 상기 CVD 절연막, 텅스텐막, 확산방지막(WSiN) 및 실리콘막 적층구조를 식각하여 패터닝하는 공정과,Etching and patterning the CVD insulating film, tungsten film, diffusion barrier film (WSiN), and silicon film stacked structure by an etching process using a gate electrode mask;
후속공정으로 엘.디.디. 접합영역을 형성하는 공정을 포함하는 것을 특징으로한다.Subsequent process to L.D.D. And forming a junction region.
이하, 첨부된 도면을 참고로 하여 본 발명을 상세히 설명하기로 한다.Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.
도 2a 내지 도 2f 는 본 발명의 실시예에 따른 반도체소자의 게이트전극 형성방법을 도시한 단면도이다.2A to 2F are cross-sectional views illustrating a method of forming a gate electrode of a semiconductor device according to an embodiment of the present invention.
먼저, 반도체기판(31) 상부에 게이트산화막(33)을 증착하고 그 상부에 게이트전극용 폴리실리콘막(35), 텅스텐막(37)을 순차적으로 적층한다.First, the gate oxide film 33 is deposited on the semiconductor substrate 31, and the polysilicon film 35 and tungsten film 37 for the gate electrode are sequentially stacked thereon.
이때, 상기 폴리실리콘막(35)은 불순물이 도핑된 층으로서, 비정질 실리콘막으로 대신 형성할 수도 있다.In this case, the polysilicon layer 35 may be formed of an amorphous silicon layer instead of an impurity doped layer.
그리고, 상기 텅스텐막(37)은 500 - 2000 Å 두께 형성한다. (도 2a)The tungsten film 37 is formed to have a thickness of 500 to 2000 mm 3. (FIG. 2A)
그 다음, 질소가스 임플란트 ( N2 implant ) 공정을 실시하고 질소가스분위기 또는 암모니아 ( NH3 ) 가스 분위기에서 열처리하여 상기 텅스텐막(37)과 폴리실리콘막(35)의 계면에 WSiN 의 확산방지막(39)을 형성한다.Next, a nitrogen gas implant (N2 implant) process is performed and heat treated in a nitrogen gas atmosphere or ammonia (NH3) gas atmosphere so that the diffusion barrier film 39 of WSiN is formed at the interface between the tungsten film 37 and the polysilicon film 35. To form.
이때, 상기 임플란트 공정은 상기 텅스텐막(37)과 폴리실리콘막(35)의 계면에 WSiN 의 확산방지막(39)이 형성되도록 질소의 피크 ( peak ) 값이 텅스텐막(37)과 폴리실리콘막(35) 사이에 위치하도록 에너지를 조절하여 실시한다. 또한, 상기 질소가스 임플란트 ( N2 implant ) 공정은 질소 임플란트 ( N implant ) 공정으로 대신할 수도 있다.At this time, in the implant process, a peak value of nitrogen is formed so that a peak value of nitrogen is formed on the interface between the tungsten film 37 and the polysilicon film 35 so that the peak value of nitrogen is tungsten film 37 and the polysilicon film ( 35) Adjust the energy so as to be located between. In addition, the nitrogen gas implant (N2 implant) process may be replaced by a nitrogen implant (N implant) process.
그리고, 상기 임플란트 공정은 질소의 도즈(dose)량은 5E14/㎠ - 1E16/㎠ 으로 하여 실시한다.In addition, the implant process is carried out with a dose of nitrogen of 5E14 / cm 2-1E16 / cm 2.
한편, 상기 열처리공정은 700 - 800 ℃ 온도에서 10 - 30 분 정도의 시간동안 퍼니스 ( furnace )에서 어닐링하여 실시하거나, 750 - 900 ℃ 온도에서 10 - 60 초 동안 급속 열처리하여 실시하는 것이다.On the other hand, the heat treatment step is carried out by annealing in a furnace (furnace) for about 10-30 minutes at a temperature of 700-800 ℃, or by performing a rapid heat treatment for 10-60 seconds at a temperature of 750-900 ℃.
상기 확산방지막(39)은 텅스텐 실리사이드의 발생을 억제하는 역할을 한다. (도 2b)The diffusion barrier 39 serves to suppress the generation of tungsten silicide. (FIG. 2B)
그 다음, 상기 텅스텐막(37) 상부에 하드마스크층인 CVD 절연막(41)을 형성한다.Next, a CVD insulating film 41 that is a hard mask layer is formed on the tungsten film 37.
그리고, 게이트전극 마스크를 이용한 식각공정으로 상기 CVD 절연막(41), 텅스텐막(39), 확산방지막(37) 및 폴리실리콘막(35)을 순차적으로 식각하여 패터닝한다. (도 2c)The CVD insulating film 41, the tungsten film 39, the diffusion barrier film 37, and the polysilicon film 35 are sequentially etched and patterned by an etching process using a gate electrode mask. (FIG. 2C)
그 다음, 상기 하드마스크층인 CVD 절연막(41)을 마스크로하여 상기 반도체기판(31)에 저농도의 불순물을 이온주입하여 저농도의 불순물 접합영역(50)을 형성한다. (도 2d)Subsequently, a low concentration of impurity junction regions 50 are formed by ion implanting low concentrations of impurities into the semiconductor substrate 31 using the CVD insulating layer 41 as the hard mask layer as a mask. (FIG. 2D)
그리고, 상기 CVD 절연막(41), 텅스텐막(39), 확산방지막(37) 및 폴리실리콘막(35)의 적층구조에 절연막 스페이서(43)를 형성한다. (도 2e)An insulating film spacer 43 is formed in a stacked structure of the CVD insulating film 41, the tungsten film 39, the diffusion barrier film 37, and the polysilicon film 35. (FIG. 2E)
그 다음, 상기 적층구조와 절연막 스페이서(43)를 마스크로하여 상기 반도체기판(31)에 고농도의 불순물을 이온주입하여 고농도의 불순물 접합영역을 형성함으로써 LDD 접합영역(60)을 형성한다. (도 2f)Next, the LDD junction region 60 is formed by ion implanting a high concentration of impurities into the semiconductor substrate 31 using the stacked structure and the insulating film spacer 43 as a mask to form a high concentration impurity junction region. (FIG. 2F)
본 발명의 다른 실시예는 질소가스 임플란트 공정을 상기 텅스텐막(37)을 증착전인 폴리실리콘막(35) 증착 공정 직후에 실시하는 것이다.In another embodiment of the present invention, the nitrogen gas implant process is performed immediately after the polysilicon film 35 is deposited before the tungsten film 37 is deposited.
이상에서 설명한 바와같이 본 발명에 따른 반도체소자의 게이트전극 형성방법은, 폴리실리콘층과 텅스텐막의 계면에 질소 임플란트 공정을 실시하여 확산방지막(WSiN)을 형성함으로써 텅스텐 실리사이드의 유발을 방지하고 그에 따른 반도체소자의 특성 및 신뢰성을 향상시킬 수 있는 효과를 제공한다.As described above, in the method of forming a gate electrode of a semiconductor device according to the present invention, a diffusion barrier layer (WSiN) is formed by performing a nitrogen implant process at an interface between a polysilicon layer and a tungsten film to prevent induction of tungsten silicide and thereby It provides an effect that can improve the characteristics and reliability of the device.
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