KR100266019B1 - Method for fabricating semiconductor device - Google Patents

Method for fabricating semiconductor device Download PDF

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KR100266019B1
KR100266019B1 KR1019970067210A KR19970067210A KR100266019B1 KR 100266019 B1 KR100266019 B1 KR 100266019B1 KR 1019970067210 A KR1019970067210 A KR 1019970067210A KR 19970067210 A KR19970067210 A KR 19970067210A KR 100266019 B1 KR100266019 B1 KR 100266019B1
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metal layer
layer
silicon
barrier metal
gate
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KR1019970067210A
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Korean (ko)
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KR19990048488A (en
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이병학
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김영환
현대반도체주식회사
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
    • H01L29/4916—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a silicon layer, e.g. polysilicon doped with boron, phosphorus or nitrogen
    • H01L29/4925—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a silicon layer, e.g. polysilicon doped with boron, phosphorus or nitrogen with a multiple layer structure, e.g. several silicon layers with different crystal structure or grain arrangement
    • H01L29/4941—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a silicon layer, e.g. polysilicon doped with boron, phosphorus or nitrogen with a multiple layer structure, e.g. several silicon layers with different crystal structure or grain arrangement with a barrier layer between the silicon and the metal or metal silicide upper layer, e.g. Silicide/TiN/Polysilicon
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/28008—Making conductor-insulator-semiconductor electrodes
    • H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H01L21/28026—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
    • H01L21/28035—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities
    • H01L21/28044—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities the conductor comprising at least another non-silicon conductive layer
    • H01L21/28061—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities the conductor comprising at least another non-silicon conductive layer the conductor comprising a metal or metal silicide formed by deposition, e.g. sputter deposition, i.e. without a silicidation reaction

Abstract

PURPOSE: A method for fabricating a semiconductor device is to form a gate having a low resistance by rapidly annealing and recrystallizing a barrier metal layer having an amorphous state in ion implanting silicon. CONSTITUTION: A field oxide layer(33) is formed on a semiconductor substrate(31) by an LOCOS(local oxidation of silicon) method to define an active region and a field region. A gate oxide layer(35) is formed on the exposed part of the semiconductor substrate. A silicon layer(37) is deposited on the gate oxide layer. A barrier metal layer(39) are formed on the silicon layer. The barrier metal layer is recrystallized by implanting silicon ions into the semiconductor substrate and rapidly annealing it. A metal layer(41) is formed on the barrier metal layer. A cap insulating layer(43) is formed on the metal layer. A gate(45) is formed by patterning the cap insulating layer, the metal layer, the barrier metal layer, and the silicon layer through a photolithography method.

Description

반도체장치의 제조방법Manufacturing Method of Semiconductor Device

본 발명은 반도체장치의 제조방법에 관한 것으로, 특히, 게이트를 다결정실리콘과 금속이 적층된 구조로 형성하여 저항을 감소시키는 반도체장치의 제조방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device, and more particularly, to a method of manufacturing a semiconductor device in which a gate is formed in a structure in which polycrystalline silicon and a metal are laminated to reduce resistance.

반도체장치가 고집적화됨에 따라 게이트의 선폭이 감소되어 게이트의 시트 저항이 증가하여 동작 속도가 저하되는 문제점이 발생되었다.As the semiconductor device is highly integrated, the line width of the gate is reduced, and the sheet resistance of the gate is increased, resulting in a decrease in operating speed.

그러므로, 소자의 동작 속도를 증가시키기 위해 게이트의 시트 저항을 감소시키는 기술이 개발되고 있다. 게이트의 시트 저항을 감소시키는 기술 중에 게이트를 다결정실리콘과 실리사이드의 2중 구조로 형성하는 기술이 있다. 다결정실리콘과 실리사이드의 2중 구조의 게이트는 실리사이드가 다결정실리콘 보다 저항이 작으므로 게이트의 저항을 감소시킬 수 있다.Therefore, techniques for reducing the sheet resistance of the gate have been developed to increase the operating speed of the device. One technique for reducing the sheet resistance of the gate is to form the gate in a double structure of polysilicon and silicide. The gate of the double structure of polysilicon and silicide may reduce the resistance of the gate because the silicide has a lower resistance than polysilicon.

그러나, 실리사이드도 저항을 감소시키는 데 한계가 있으므로 다결정실리콘층 상에 Ti, W, Mo, Co, Ta 또는 Pt 등의 고융점 금속을 적층시킨 구조의 게이트가 제시되고 있다.However, since silicide also has a limit in reducing resistance, a gate having a structure in which a high melting point metal such as Ti, W, Mo, Co, Ta or Pt is laminated on a polysilicon layer has been proposed.

도 1a 내지 도 1c는 종래 기술에 따른 반도체장치의 제조 공정도이다.1A to 1C are manufacturing process diagrams of a semiconductor device according to the prior art.

도 1a를 참조하면, 반도체기판(11) 상의 소정 부분에 LOCOS(Local Oxidation of Silicon) 등의 방법에 의해 필드산화막(13)을 형성하여 소자의 활성영역과 필드영역을 한정한다. 그리고, 반도체기판(11)의 노출된 부분에 열산화 방법에 의해 50∼100Å 정도 두께의 게이트산화막(15)을 형성한다.Referring to FIG. 1A, a field oxide film 13 is formed on a predetermined portion of a semiconductor substrate 11 by a method such as LOCOS (Local Oxidation of Silicon) to define an active region and a field region of a device. In the exposed portion of the semiconductor substrate 11, a gate oxide film 15 having a thickness of about 50 to 100 Å is formed by a thermal oxidation method.

상기에서, 필드산화막(13)을 반도체기판(11)에 트렌치를 형성하고 산화실리콘을 채워 형성하는 STI(Shallow Trench Isolation) 방법으로도 형성할 수 있다.In the above description, the field oxide layer 13 may be formed by a trench trench isolation (STI) method in which a trench is formed in the semiconductor substrate 11 and filled with silicon oxide.

도 1b를 참조하면, 필드산화막(13) 및 게이트산화막(15) 상에 불순물이 도핑된 다결정실리콘을 화학기상증착(Chemical Vapor Deposition : 이하, CVD라 칭함) 방법으로 500∼1500Å 정도 두께로 증착하여 실리콘층(17)을 증착한다. 그리고, 실리콘층(17) 상에 TiN 또는 WN 등을 50∼100Å 정도 두께로 증착하여 장벽층(19)을 형성하고, 이 장벽층(19) 상에 Ti, W, Mo, Co, Ta 또는 Pt 등의 고융점 금속을 스퍼터링 등의 물리기상증착(Physical Vapor Deposion : 이하, PVD라 칭함) 방법으로 500∼1500Å 정도 두께로 증착하여 금속층(21)을 형성한다. 상기에서 장벽층(19)은 실리콘층(17)과 금속층(21)이 반응하여 계면에 실리사이드가 생성되는 것을 방지한다. 그리고, 금속층(21) 상에 산화실리콘 또는 질화실리콘을 CVD 방법으로 1500∼2500Å 정도 두께로 증착하여 캡절연층(23)을 형성한다.Referring to FIG. 1B, polycrystalline silicon doped with impurities on the field oxide film 13 and the gate oxide film 15 is deposited to a thickness of about 500 to 1500 Å by chemical vapor deposition (hereinafter, referred to as CVD). Silicon layer 17 is deposited. Then, TiN or WN or the like is deposited on the silicon layer 17 to a thickness of about 50 to 100 GPa to form a barrier layer 19. Ti, W, Mo, Co, Ta, or Pt is formed on the barrier layer 19. The metal layer 21 is formed by depositing a high melting point metal such as sputtering to a thickness of about 500 to 1500 mW by physical vapor deposition (hereinafter, referred to as PVD). The barrier layer 19 prevents the silicon layer 17 and the metal layer 21 from reacting to form silicide at the interface. Then, silicon oxide or silicon nitride is deposited on the metal layer 21 to a thickness of about 1500 to 2500 mV by the CVD method to form a cap insulating layer 23.

도 1c를 참조하면, 캡절연층(23), 금속층(21), 장벽층(19) 및 실리콘층(17)을 반도체기판(11)이 노출되도록 포토리쏘그래피 방법으로 순차적으로 패터닝한다. 이 때, 잔류하는 실리콘층(17), 장벽층(19) 및 금속층(21)은 게이트(25)가 된다.Referring to FIG. 1C, the cap insulation layer 23, the metal layer 21, the barrier layer 19, and the silicon layer 17 are sequentially patterned by a photolithography method so that the semiconductor substrate 11 is exposed. At this time, the remaining silicon layer 17, the barrier layer 19 and the metal layer 21 become the gate 25.

상기에서 장벽층(19)은 입자(grain)가 원주형(columnar)의 구조를 이루는 데, 이 장벽층(19) 상에 형성되는 금속층(21)은 입자의 크기가 작으므로 비저항이 증가된다. 즉, 금속층(21)은 실리콘기판 상에 형성되었을 입자가 크게 형성되어 비저항이 약 14μΩ·㎝ 정도인 데, 이에 반해, 장벽층(19) 상에 형성되었을 경우 비저항이 약 34μΩ·㎝ 정도가 되어 대략 2.5배 정도가 더 크다.In the barrier layer 19, grains have a columnar structure, and the metal layer 21 formed on the barrier layer 19 has a small particle size, thereby increasing specific resistance. That is, the metal layer 21 has a large specific particle formed on the silicon substrate and has a specific resistance of about 14 μΩ · cm. In contrast, when the metal layer 21 is formed on the barrier layer 19, the specific resistance is about 34 μΩ · cm. Approximately 2.5 times larger.

그러므로, 상술한 바와 같이 종래의 반도체장치의 제조방법은 실리콘층과 금속층이 반응되는 것을 방지하기 위한 장벽층으로 인해 게이트의 저항을 감소시키기 어려운 문제점이 있었다.Therefore, as described above, the conventional method of manufacturing a semiconductor device has a problem that it is difficult to reduce the resistance of the gate due to the barrier layer for preventing the silicon layer and the metal layer from reacting.

따라서, 본 발명의 목적은 저저항 게이트를 형성할 수 있는 반도체장치의 제조방법을 제공함에 있다.Accordingly, it is an object of the present invention to provide a method for manufacturing a semiconductor device capable of forming a low resistance gate.

상기 목적을 달성하기 위한 본 발명에 따른 반도체장치의 제조방법은 반도체기판 상에 게이트산화막을 형성하는 공정과, 상기 게이트산화막 상에 실리콘층과 장벽금속층을 순차적으로 형성하고 상기 장벽금속층에 실리콘을 이온 주입하여 비정질화시키고 금속열처리하여 재결정화하는 공정과, 상기 장벽금속층 상에 금속층 및 캡절연층을 형성하고 상기 캡절연층, 금속층, 장벽금속층 및 실리콘층을 패터닝하여 게이트를 형성하는 공정을 구비한다.A semiconductor device manufacturing method according to the present invention for achieving the above object is a step of forming a gate oxide film on a semiconductor substrate, and sequentially forming a silicon layer and a barrier metal layer on the gate oxide film and ionized silicon on the barrier metal layer Implanting, amorphizing, heat treating the metal, and recrystallizing the metal; forming a metal layer and a cap insulation layer on the barrier metal layer, and patterning the cap insulation layer, the metal layer, the barrier metal layer, and a silicon layer to form a gate. .

도 1a 내지 도 1c는 종래 기술에 따른 반도체장치의 제조 공정도1A to 1C are manufacturing process diagrams of a semiconductor device according to the prior art.

도 2a 내지 도 2d는 본 발명에 따른 반도체장치의 제조 공정도2A to 2D are manufacturing process diagrams of a semiconductor device according to the present invention.

도 3은 질소(N2) 이온 주입시 깊이에 대한 농도 분포를 도시하는 그래프FIG. 3 is a graph showing concentration distribution versus depth at the time of nitrogen (N 2 ) ion implantation

이하, 첨부한 도면을 참조하여 본 발명을 상세히 설명한다.Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.

도 2a를 참조하면, 반도체기판(31) 상의 소정 부분에 LOCOS 등의 방법에 의해 필드산화막(33)을 형성하여 소자의 활성영역과 필드영역을 한정한다. 그리고, 반도체기판(31)의 노출된 부분에 열산화 방법에 의해 50∼100Å 정도 두께의 게이트산화막(35)을 형성한다.Referring to FIG. 2A, a field oxide film 33 is formed in a predetermined portion on the semiconductor substrate 31 by a method such as LOCOS to define an active region and a field region of the device. In the exposed portion of the semiconductor substrate 31, a gate oxide film 35 having a thickness of about 50 to 100 Å is formed by a thermal oxidation method.

상기에서, 필드산화막(33)을 반도체기판(31)에 트렌치를 형성하고 산화실리콘을 채워 형성하는 STI 방법으로도 형성할 수 있다.In the above, the field oxide film 33 may be formed by the STI method of forming a trench in the semiconductor substrate 31 and filling the silicon oxide.

도 2b를 참조하면, 필드산화막(33) 및 게이트산화막(35) 상에 불순물이 도핑된 다결정실리콘을 SiH4, NH3, PH3및 B2H6를 소스 가스로 하는 CVD 방법으로 700∼ 2000Å 정도 두께로 증착하여 실리콘층(37)을 증착한다. 그리고, 실리콘층(37) 상에 TiNy, WNy, MoNy, CoNy, TaNy 또는 PtNx 등을 스퍼터링 등의 PVD 방법으로 50∼200Å 정도의 두께로 증착하여 장벽금속층(39)을 형성한다. 상기에서 장벽금속층(39)의 장벽 특성을 향상시키기 위하여 이 장벽금속층(39) 내에 질소(N)의 함유량이 40∼60% 정도가 되도록한다.Referring to FIG. 2B, polycrystalline silicon doped with impurities on the field oxide film 33 and the gate oxide film 35 is 700 to 2000 kV in a CVD method using SiH 4 , NH 3 , PH 3, and B 2 H 6 as source gases. The silicon layer 37 is deposited by depositing to a thickness. The barrier metal layer 39 is formed by depositing TiNy, WNy, MoNy, CoNy, TaNy, PtNx, or the like on the silicon layer 37 to a thickness of about 50 to 200 mV using a PVD method such as sputtering. In order to improve the barrier properties of the barrier metal layer 39, the content of nitrogen (N) in the barrier metal layer 39 is about 40 to 60%.

장벽금속층(39)에 실리콘(Si)를 5∼25KeV 정도의 에너지와 1×1015∼1×1017/㎠ 정도의 도우즈 량으로 이온 주입하고 급속 열처리하여 장벽금속층(39)을 TiSixNy, WSixNy, MoSixNy, CoSixNy, TaSixNy 또는 PtSixNy 등으로 변화시킨다. 급속열처리는 NH3또는 N2가스의 분위기에서 500∼800℃의 온도로 10∼120초 동안 진행한다. 상기에서 장벽금속층(39)은 실리콘 이온 주입시 비정질 상태로 변화되었다가 급속 열처리시 입자가 크게 결정화되므로 비저항을 감소시킨다. 또한, 장벽금속층(39)은 도핑된 실리콘에 의해 장벽 특성이 향상된다.Silicon (Si) is implanted into the barrier metal layer 39 at an energy of about 5 to 25 KeV and a dose of about 1 × 10 15 to 1 × 10 17 / cm 2 and rapidly heat-treated to make the barrier metal layer 39 TiSixNy, WSixNy. , MoSixNy, CoSixNy, TaSixNy or PtSixNy. Rapid heat treatment is performed for 10 to 120 seconds at a temperature of 500 to 800 ℃ in the atmosphere of NH 3 or N 2 gas. The barrier metal layer 39 is changed to an amorphous state during the implantation of silicon ions, and the specific resistance is reduced because the particles are greatly crystallized during the rapid heat treatment. In addition, the barrier metal layer 39 is improved in barrier properties by the doped silicon.

도 2c를 참조하면, 장벽금속층(39) 상에 Ti, W, Mo, Co, Ta 또는 Pt 등의 고융점 금속을 스퍼터링 등의 PVD 방법으로 500∼1500Å 정도의 두께로 증착하여 금속층(41)을 형성한다. 상기에서 장벽금속층(39)이 입자가 크므로 금속층(41)도 입자가 크게 형성되어 비저항이 감소된다. 또한, 금속층(41)은 장벽금속층(39)에 의해 실리콘층(37)과 반응하여 실리사이드화 되는 것이 방지된다. 금속층(41) 상에 산화실리콘 또는 질화실리콘을 CVD 방법으로 2000∼3000Å 정도의 두께로 증착하여 캡절연층(43)을 형성한다.Referring to FIG. 2C, a high melting point metal such as Ti, W, Mo, Co, Ta, or Pt is deposited on the barrier metal layer 39 to a thickness of about 500 to 1500 kPa by a PVD method such as sputtering to deposit a metal layer 41. Form. Since the barrier metal layer 39 has a large particle, the metal layer 41 also has a large particle, thereby reducing the specific resistance. In addition, the metal layer 41 is prevented from reacting with the silicon layer 37 by the barrier metal layer 39 to be silicided. Silicon oxide or silicon nitride is deposited on the metal layer 41 to a thickness of about 2000 to 3000 kPa by the CVD method to form a cap insulating layer 43.

도 2d를 참조하면, 캡절연층(43), 금속층(41), 장벽금속층(39) 및 실리콘층 (37)을 반도체기판(11)이 노출되도록 이방성 식각을 포함하는 포토리쏘그래피 방법으로 순차적으로 패터닝한다. 이 때, 잔류하는 실리콘층(37), 장벽층(39) 및 금속층(41)은 게이트(45)가 된다.Referring to FIG. 2D, the cap insulation layer 43, the metal layer 41, the barrier metal layer 39, and the silicon layer 37 are sequentially formed by a photolithography method including anisotropic etching so that the semiconductor substrate 11 is exposed. Pattern. At this time, the remaining silicon layer 37, the barrier layer 39, and the metal layer 41 become the gate 45.

따라서, 본 발명은 실리콘을 이온 주입할 때 비정질 상태로 변한 장벽금속층을 급속 열처리하여 재결정화시킬 때 입자가 크게되므로 이 후에 형성되는 금속층도 입자가 크게 되어 비저항이 감소되어 저저항 게이트를 형성할 수 있는 잇점이 있다. 또한, 장벽금속층은 도핑된 실리콘에 의해 장벽 특성이 향상되는 잇점이 있다.Therefore, in the present invention, when the silicon implant is ion implanted, the grains are large when the heat-treatment of the barrier metal layer, which has changed to an amorphous state, by rapid thermal recrystallization, so that the metal layer formed thereafter is also large in particle size, so that the resistivity is reduced to form a low resistance gate. There is an advantage. In addition, the barrier metal layer has the advantage that the barrier properties are improved by the doped silicon.

Claims (6)

반도체기판 상에 게이트산화막을 형성하는 공정과,Forming a gate oxide film on the semiconductor substrate; 상기 게이트산화막 상에 실리콘층과 장벽금속층을 순차적으로 형성하는 공정과,Sequentially forming a silicon layer and a barrier metal layer on the gate oxide film; 상기 반도체기판에 실리콘을 이온 주입하여 비정질화시키고 금속열처리시킴으로써 상기 장벽금속층을 재결정시키는 공정과,Recrystallizing the barrier metal layer by ion implantation of silicon into the semiconductor substrate to amorphize and thermally treat the metal; 상기 재결정화된 장벽금속층 상에 금속층 및 캡절연층을 순차적으로 형성하는 공정과,Sequentially forming a metal layer and a cap insulating layer on the recrystallized barrier metal layer; 상기 캡절연층, 금속층, 재결정화된 장벽금속층 및 실리콘층을 패터닝하여 게이트를 형성하는 공정을 구비하는 반도체장치의 제조방법.And forming a gate by patterning the cap insulating layer, the metal layer, the recrystallized barrier metal layer, and the silicon layer. 청구항 1에 있어서,The method according to claim 1, 상기 실리콘층을 SiH4, NH3, PH3및 B2H6를 소스 가스로하여 화학기상증착 (Chemical Vapor Deposition) 방법으로 증착하는 다결정실리콘으로 형성하는 반도체장치의 제조방법.A method of manufacturing a semiconductor device, wherein the silicon layer is formed of polycrystalline silicon which is deposited by chemical vapor deposition using SiH 4 , NH 3 , PH 3, and B 2 H 6 as source gases. 청구항 1에 있어서,The method according to claim 1, 상기 장벽금속층을 TiN, WN, MoN, CoN, TaN 또는 PtN의 금속을 물리기상증착 (Physical Vapor Deposion) 방법으로 증착하여 형성하는 반도체장치의 제조방법.The barrier metal layer is formed by depositing a metal of TiN, WN, MoN, CoN, TaN or PtN by physical vapor deposition (Physical Vapor Deposion) method. 청구항 1에 있어서,The method according to claim 1, 상기 장벽금속층을 질소의 함량이 40∼60%가 되도록 형성하는 반도체장치의 제조방법.And forming the barrier metal layer so that the nitrogen content is 40 to 60%. 청구항 1에 있어서 상기 실리콘을 5∼25KeV의 에너지와 1×1015∼1×1017/㎠의 도우즈 량으로 이온 주입하는 반도체장치의 제조방법.The method of manufacturing a semiconductor device according to claim 1, wherein the silicon is ion implanted with an energy of 5 to 25 KeV and a dose of 1 × 10 15 to 1 × 10 17 / cm 2. 청구항 1에 있어서 상기 급속열처리를 NH3또는 N2가스의 분위기에서 500 ∼800℃의 온도로 10∼120초 동안 진행하는 반도체장치의 제조방법.The method of manufacturing a semiconductor device according to claim 1, wherein the rapid heat treatment is performed for 10 to 120 seconds at a temperature of 500 to 800 ° C. in an atmosphere of NH 3 or N 2 gas.
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