KR20010089208A - 저전력 동작을 위한 스캔-bist 아키텍쳐의 적응 - Google Patents
저전력 동작을 위한 스캔-bist 아키텍쳐의 적응 Download PDFInfo
- Publication number
- KR20010089208A KR20010089208A KR1020010011927A KR20010011927A KR20010089208A KR 20010089208 A KR20010089208 A KR 20010089208A KR 1020010011927 A KR1020010011927 A KR 1020010011927A KR 20010011927 A KR20010011927 A KR 20010011927A KR 20010089208 A KR20010089208 A KR 20010089208A
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- South Korea
- Prior art keywords
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Classifications
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/317—Testing of digital circuits
- G01R31/31721—Power aspects, e.g. power supplies for test circuits, power saving during test
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/317—Testing of digital circuits
- G01R31/31723—Hardware for routing the test signal within the device under test to the circuits to be tested, e.g. multiplexer for multiple core testing, accessing internal nodes
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/317—Testing of digital circuits
- G01R31/31724—Test controller, e.g. BIST state machine
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/317—Testing of digital circuits
- G01R31/3177—Testing of logic operation, e.g. by logic analysers
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/317—Testing of digital circuits
- G01R31/3181—Functional testing
- G01R31/3185—Reconfiguring for testing, e.g. LSSD, partitioning
- G01R31/318533—Reconfiguring for testing, e.g. LSSD, partitioning using scanning techniques, e.g. LSSD, Boundary Scan, JTAG
- G01R31/318536—Scan chain arrangements, e.g. connections, test bus, analog signals
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/317—Testing of digital circuits
- G01R31/3181—Functional testing
- G01R31/3185—Reconfiguring for testing, e.g. LSSD, partitioning
- G01R31/318533—Reconfiguring for testing, e.g. LSSD, partitioning using scanning techniques, e.g. LSSD, Boundary Scan, JTAG
- G01R31/318575—Power distribution; Power saving
Landscapes
- Engineering & Computer Science (AREA)
- General Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Power Engineering (AREA)
- Computer Networks & Wireless Communication (AREA)
- Tests Of Electronic Circuits (AREA)
- Semiconductor Integrated Circuits (AREA)
- Test And Diagnosis Of Digital Computers (AREA)
Abstract
Description
Claims (3)
- 합성 스캔-BIST 아키텍쳐를 저전력 동작에 적응시키는 프로세스에 있어서,상기 스캔 BIST 아키텍쳐의 스캔 경로를, 각기 스캔 입력 및 스캔 출력을 갖는 다수의 개별 스캔 경로 섹션들로 분할하는 단계;각각의 스캔 경로 섹션의 스캔 입력들 간에 접속을 형성하는 단계;각각의 스캔 경로 섹션의 스캔 출력들 간에 접속을 형성하는 단계;개별 스캔 제어 출력들을 갖는 스캔 제어 회로를 제공하는 단계; 및상기 개별 제어 출력들 각각과 상기 스캔 경로 섹션들 중 하나 사이에 개별 접속을 형성하는 단계를 포함하는 것을 특징으로 하는 프로세스.
- 집적 회로 내의 회로의 스캔 BIST 테스트 구성에 있어서,스캔 입력, 스캔 출력 및 제어 입력을 각각 갖는 다수의 스캔 경로들,제어 입력 및 자극 데이터 출력을 갖는 생성기 회로,제어 입력 및 응답 데이터 입력을 갖는 컴팩터 회로,상기 스캔 경로의 상기 제어 입력들, 생성기 회로 및 컴팩터 회로에 제어 출력을 제공하는 제어 회로,상기 생성기 회로의 상기 자극 데이터 출력과 상기 다수의 스캔 경로들의 상기 스캔 입력들 사이에 형성된 제1 접속부, 및상기 컴팩터 회로의 상기 응답 데이터 입력과 상기 다수의 스캔 경로들의 상기 스캔 출력들 사이에 형성된 제2 접속부를 포함하는 것을 특징으로 하는 스캔 BIST 테스트 구성.
- 집적 회로 내의 회로의 스캔 BIST 테스트 구성에 있어서,제1 제어 입력을 갖는 스캔 경로,제2 제어 입력을 갖는 생성기,제3 제어 입력을 갖는 컴팩터,제1 제어 출력을 갖는 제1 제어기,제4 제어 입력 및 제2 제어 출력을 갖는 제2 제어기,상기 제1 제어 출력과 상기 제2, 제3 및 제4 제어 입력들 간의 접속부 및상기 제2 제어 출력과 상기 제1 제어 입력 간의 접속부를 포함하는 것을 특징으로 하는 스캔 BIST 테스트 구성.
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US18810900P | 2000-03-09 | 2000-03-09 | |
US60/188,109 | 2000-03-09 |
Publications (2)
Publication Number | Publication Date |
---|---|
KR20010089208A true KR20010089208A (ko) | 2001-09-29 |
KR100790238B1 KR100790238B1 (ko) | 2007-12-31 |
Family
ID=22691804
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
KR1020010011927A KR100790238B1 (ko) | 2000-03-09 | 2001-03-08 | 스캔 회로 |
Country Status (5)
Country | Link |
---|---|
US (13) | US6763488B2 (ko) |
EP (1) | EP1146343B1 (ko) |
JP (1) | JP4971547B2 (ko) |
KR (1) | KR100790238B1 (ko) |
DE (1) | DE60108993T2 (ko) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
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KR102035421B1 (ko) * | 2018-05-08 | 2019-10-22 | 한양대학교 에리카산학협력단 | Ic chip의 저전력 테스트 방법 및 장치 |
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2001
- 2001-03-07 DE DE60108993T patent/DE60108993T2/de not_active Expired - Lifetime
- 2001-03-07 EP EP01000044A patent/EP1146343B1/en not_active Expired - Lifetime
- 2001-03-08 KR KR1020010011927A patent/KR100790238B1/ko active IP Right Grant
- 2001-03-09 US US09/803,608 patent/US6763488B2/en not_active Expired - Lifetime
- 2001-03-09 JP JP2001066990A patent/JP4971547B2/ja not_active Expired - Lifetime
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2004
- 2004-07-06 US US10/886,206 patent/US7051257B2/en not_active Expired - Lifetime
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2006
- 2006-03-30 US US11/278,064 patent/US7526695B2/en not_active Expired - Lifetime
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2009
- 2009-03-18 US US12/406,348 patent/US7747919B2/en not_active Expired - Fee Related
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2010
- 2010-05-14 US US12/780,410 patent/US7925945B2/en not_active Expired - Fee Related
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2011
- 2011-03-09 US US13/043,778 patent/US8015466B2/en not_active Expired - Fee Related
- 2011-07-15 US US13/184,077 patent/US8261144B2/en not_active Expired - Lifetime
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2012
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Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
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KR102035421B1 (ko) * | 2018-05-08 | 2019-10-22 | 한양대학교 에리카산학협력단 | Ic chip의 저전력 테스트 방법 및 장치 |
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