KR20010058208A - Method of forming gate electrode which capable of preventing fail of that induced from re-oxidation process in semiconductor device - Google Patents
Method of forming gate electrode which capable of preventing fail of that induced from re-oxidation process in semiconductor device Download PDFInfo
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- KR20010058208A KR20010058208A KR1019990061719A KR19990061719A KR20010058208A KR 20010058208 A KR20010058208 A KR 20010058208A KR 1019990061719 A KR1019990061719 A KR 1019990061719A KR 19990061719 A KR19990061719 A KR 19990061719A KR 20010058208 A KR20010058208 A KR 20010058208A
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- 238000000034 method Methods 0.000 title claims abstract description 75
- 239000004065 semiconductor Substances 0.000 title claims abstract description 28
- 238000007254 oxidation reaction Methods 0.000 title abstract description 14
- 229910052751 metal Inorganic materials 0.000 claims abstract description 55
- 239000002184 metal Substances 0.000 claims abstract description 55
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 46
- 229920005591 polysilicon Polymers 0.000 claims abstract description 46
- 229910021332 silicide Inorganic materials 0.000 claims abstract description 9
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 claims abstract description 9
- 239000000758 substrate Substances 0.000 claims abstract description 8
- 238000001459 lithography Methods 0.000 claims abstract description 3
- 238000010405 reoxidation reaction Methods 0.000 claims description 15
- 230000003064 anti-oxidating effect Effects 0.000 claims description 12
- 238000005240 physical vapour deposition Methods 0.000 claims description 10
- 238000005229 chemical vapour deposition Methods 0.000 claims description 9
- 238000010438 heat treatment Methods 0.000 claims description 9
- BASFCYQUMIYNBI-UHFFFAOYSA-N platinum Chemical compound [Pt] BASFCYQUMIYNBI-UHFFFAOYSA-N 0.000 claims description 9
- 239000010936 titanium Substances 0.000 claims description 9
- 239000011651 chromium Substances 0.000 claims description 6
- 238000005530 etching Methods 0.000 claims description 6
- 239000012535 impurity Substances 0.000 claims description 6
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 claims description 5
- 229910052719 titanium Inorganic materials 0.000 claims description 5
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical group [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 claims description 5
- 229910052721 tungsten Inorganic materials 0.000 claims description 5
- 239000010937 tungsten Substances 0.000 claims description 5
- ZOKXTWBITQBERF-UHFFFAOYSA-N Molybdenum Chemical compound [Mo] ZOKXTWBITQBERF-UHFFFAOYSA-N 0.000 claims description 4
- 229910052750 molybdenum Inorganic materials 0.000 claims description 4
- 239000011733 molybdenum Substances 0.000 claims description 4
- VYZAMTAEIAYCRO-UHFFFAOYSA-N Chromium Chemical compound [Cr] VYZAMTAEIAYCRO-UHFFFAOYSA-N 0.000 claims description 3
- 229910052782 aluminium Inorganic materials 0.000 claims description 3
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims description 3
- 229910052804 chromium Inorganic materials 0.000 claims description 3
- 239000010941 cobalt Substances 0.000 claims description 3
- 229910017052 cobalt Inorganic materials 0.000 claims description 3
- GUTLYIVDDKVIGB-UHFFFAOYSA-N cobalt atom Chemical compound [Co] GUTLYIVDDKVIGB-UHFFFAOYSA-N 0.000 claims description 3
- 238000001312 dry etching Methods 0.000 claims description 3
- 229910052697 platinum Inorganic materials 0.000 claims description 3
- 229910052715 tantalum Inorganic materials 0.000 claims description 3
- GUVRBAGPIYLISA-UHFFFAOYSA-N tantalum atom Chemical compound [Ta] GUVRBAGPIYLISA-UHFFFAOYSA-N 0.000 claims description 3
- 238000001039 wet etching Methods 0.000 claims description 3
- 230000015572 biosynthetic process Effects 0.000 claims 2
- 239000003963 antioxidant agent Substances 0.000 claims 1
- 230000003078 antioxidant effect Effects 0.000 claims 1
- 150000002739 metals Chemical class 0.000 claims 1
- 230000003647 oxidation Effects 0.000 abstract description 9
- 230000007547 defect Effects 0.000 description 3
- 238000000059 patterning Methods 0.000 description 3
- 238000000206 photolithography Methods 0.000 description 3
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 description 3
- WQJQOUPTWCFRMM-UHFFFAOYSA-N tungsten disilicide Chemical compound [Si]#[W]#[Si] WQJQOUPTWCFRMM-UHFFFAOYSA-N 0.000 description 3
- 229910021342 tungsten silicide Inorganic materials 0.000 description 3
- 230000010354 integration Effects 0.000 description 2
- 238000004151 rapid thermal annealing Methods 0.000 description 2
- 229910021341 titanium silicide Inorganic materials 0.000 description 2
- 229910008484 TiSi Inorganic materials 0.000 description 1
- 238000000137 annealing Methods 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- 150000002500 ions Chemical class 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
- 230000002265 prevention Effects 0.000 description 1
- 125000006850 spacer group Chemical group 0.000 description 1
- 238000007740 vapor deposition Methods 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/28008—Making conductor-insulator-semiconductor electrodes
- H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
- H01L21/28247—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon passivation or protection of the electrode, e.g. using re-oxidation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/28008—Making conductor-insulator-semiconductor electrodes
- H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
- H01L21/28026—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
- H01L21/28035—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities
- H01L21/28044—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities the conductor comprising at least another non-silicon conductive layer
- H01L21/28052—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities the conductor comprising at least another non-silicon conductive layer the conductor comprising a silicide layer formed by the silicidation reaction of silicon with a metal layer
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/28008—Making conductor-insulator-semiconductor electrodes
- H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
- H01L21/28026—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
- H01L21/28035—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities
- H01L21/28044—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities the conductor comprising at least another non-silicon conductive layer
- H01L21/28061—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities the conductor comprising at least another non-silicon conductive layer the conductor comprising a metal or metal silicide formed by deposition, e.g. sputter deposition, i.e. without a silicidation reaction
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
- H01L29/4916—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a silicon layer, e.g. polysilicon doped with boron, phosphorus or nitrogen
- H01L29/4925—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a silicon layer, e.g. polysilicon doped with boron, phosphorus or nitrogen with a multiple layer structure, e.g. several silicon layers with different crystal structure or grain arrangement
- H01L29/4933—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a silicon layer, e.g. polysilicon doped with boron, phosphorus or nitrogen with a multiple layer structure, e.g. several silicon layers with different crystal structure or grain arrangement with a silicide layer contacting the silicon layer, e.g. Polycide gate
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- Chemical Kinetics & Catalysis (AREA)
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- Ceramic Engineering (AREA)
- Electrodes Of Semiconductors (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
Abstract
Description
본 발명은 반도체 소자의 게이트 전극 형성 방법에 관한 것으로, 보다 구체적으로는 게이트 산화막의 재산화 공정에서 게이트 전극에 불량이 발생하는 것을 방지할 수 있는 방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for forming a gate electrode of a semiconductor device, and more particularly, to a method capable of preventing a defect from occurring in a gate electrode in a reoxidation process of a gate oxide film.
반도체 소자는 단순한 트랜지스터로부터 초고집적 회로(Very Large Scale Integration: VLSI)로 점차 발달해감에 따라 제작 비용이나 성능 등 많은 부분에서 큰 발전을 이루어왔다. 이러한 발전이 가능했던 이유 중의 하나가 회로 소자의 크기를 감소시킬 수 있었던 이유에 있다.As semiconductor devices have evolved from simple transistors to very large scale integration (VLSI), significant advances have been made in many areas, including manufacturing costs and performance. One of the reasons this development has been possible is to reduce the size of circuit elements.
이러한 회로 소자의 가장 기본적인 것이 MOS 트랜지스터(Metal Oxide Semiconductor Transistor) 또는 IGFET(Insulated-Gate Field Effect Transistor) 등의 고집적 소자이다. 특히, 상기와 같은 MOS 트랜지스터의 크기를 감소시킬 수록 더욱 정밀하고, 집적도가 높은 회로를 제조하는 것이 가능해진다.The most basic of such a circuit device is a highly integrated device such as a metal oxide semiconductor transistor (MOS transistor) or an insulated-gate field effect transistor (IGFET). In particular, as the size of the MOS transistor is reduced, more precise and highly integrated circuits can be manufactured.
일반적으로 게이트 전극은 MOS 트랜지스터를 선택하기 위한 전극으로서, 주로 불순물이 도핑된 폴리 실리콘(Poly Silicon)막으로 형성하는데, 최근에는 게이트 전극의 비저항을 낮추기 위해서, 불순물이 도핑된 폴리 실리콘막과 텅스텐 실리사이드막(WSi2) 또는, 도핑된 폴리 실리콘막과 티타늄 실리사이드막(TiSi2)의 적층 구조로 형성한다.In general, a gate electrode is an electrode for selecting a MOS transistor, and is mainly formed of a polysilicon film doped with impurities. Recently, in order to reduce the specific resistance of the gate electrode, the gate electrode is doped with a doped polysilicon film and tungsten silicide. A film WSi 2 or a doped polysilicon film and a titanium silicide film TiSi 2 are formed in a stacked structure.
그러나, 상기와 같은 도핑된 폴리 실리콘막과 금속 실리사이드막의 적층 구조로 게이트 전극을 형성하는 경우에는, 낮은 집적도를 갖는 반도체 소자에는 용이하게 사용될 수 있지만, 현재의 고집적 반도체 소자의 미세 게이트 전극으로는 낮은 저항값을 얻을 수 없어서 이를 사용하는데 문제점이 있다.However, in the case of forming the gate electrode with the above-described laminated structure of the doped polysilicon film and the metal silicide film, it can be easily used in a semiconductor device having a low degree of integration, but as a fine gate electrode of the current highly integrated semiconductor device, There is a problem in using it because the resistance value cannot be obtained.
즉, 텅스텐 실리사이드막의 비저항은 약 100 uΩ-㎝의 값을 가지는데, 1 Gb DRAM(Dynamic Random Access Memory) 이상의 메모리 소자에서는 가는 선폭에서 고속으로 동작하는 소자를 얻기 위해서, 게이트 전극의 저항을 더욱 감소시켜야 한다.That is, the resistivity of the tungsten silicide film has a value of about 100 uΩ-cm, and in the memory device of 1 Gb dynamic random access memory (DRAM) or more, the resistance of the gate electrode is further reduced in order to obtain a device that operates at high speed at a thin line width. You have to.
따라서, 종래에는 약 10 uΩ-㎝의 비저항값을 갖고, 텅스텐 실리사이드막 또는 티타늄 실리사이드막보다 전도 특성이 우수한 텅스텐(W), 티타늄(Ti), 또는 몰리브덴(Mo) 등의 단일 금속을 폴리 실리콘막 상부에 적층하여 게이트 전극을 형성하는 방법이 제안되었다.Therefore, conventionally, a polysilicon film is formed of a single metal such as tungsten (W), titanium (Ti), or molybdenum (Mo), which has a resistivity of about 10 uΩ-cm and is superior in conductivity to a tungsten silicide film or a titanium silicide film. A method of forming a gate electrode by stacking on top has been proposed.
도 1a 내지 도 1e를 참조하여 종래의 게이트 전극의 형성 방법을 설명하면 다음과 같다.Referring to FIGS. 1A to 1E, a method of forming a conventional gate electrode is as follows.
먼저, 도 1a를 참조하면, 반도체 기판(1) 상에 게이트 산화막(2)을 열 성장 또는 증착 방식에 의하여 형성한 다음, 상기 게이트 산화막(2) 상에 불순물이 도핑된 폴리 실리콘막(3)을 소정 두께로 증착한다.First, referring to FIG. 1A, a gate oxide film 2 is formed on a semiconductor substrate 1 by thermal growth or deposition, and then a polysilicon film 3 doped with impurities on the gate oxide film 2 is formed. Is deposited to a predetermined thickness.
그런 다음, 도 1b에 도시된 바와 같이, 상기 도핑된 폴리 실리콘막(3) 상부에 티타늄 또는 텅스텐 등의 도전용 금속막을 증착하고, 공지의 포토 리소그라피(Photo Lithography) 방식을 통해 도전용 금속막과, 도핑된 폴리 실리콘막(3)을 식각하여 게이트 전극을 형성한다. 이 때, 설명되지 않은 부호 4는 패터닝이 이루어진 도전용 금속막을 나타낸다.Then, as illustrated in FIG. 1B, a conductive metal film such as titanium or tungsten is deposited on the doped polysilicon film 3, and the conductive metal film is formed through a known photo lithography method. The doped polysilicon layer 3 is etched to form a gate electrode. At this time, reference numeral 4, which is not described, indicates a conductive metal film on which patterning has been performed.
다음으로, 도 1c에 도시된 바와 같이, 게이트 전극을 형성하기 위한 식각 공정 과정에서 반도체 기판(1) 상부의 게이트 산화막(2) 표면에 발생된 손상 및 식각 잔재물을 제거하고, 게이트 산화막(2)의 신뢰성을 회복하기 위하여 반도체 기판(1) 결과물을 재산화 한다. 이 때, 재산화 공정은 예를 들어, 800 ℃와 같은 소정의 온도 이상에서 열산화하는 것으로, 재산화 공정에 의하여 도전용 금속막(4)의 측면 부분이 크게 산화되어 산화막(5)을 형성하게 되는데, 이는 일반적으로 금속이 산화에 매우 약하기 때문이다.Next, as illustrated in FIG. 1C, damage and etching residues generated on the surface of the gate oxide film 2 on the semiconductor substrate 1 in the etching process for forming the gate electrode are removed, and the gate oxide film 2 is removed. In order to restore the reliability of the semiconductor substrate 1, the resultant property is revised. At this time, the reoxidation process is, for example, thermal oxidation at a temperature higher than a predetermined temperature such as 800 ° C., by which the side surface portion of the conductive metal film 4 is greatly oxidized to form the oxide film 5. This is because the metal is usually very weak to oxidation.
상기와 같이, 게이트 전극의 전도성을 결정하는 도전용 금속막(4a)은 재산화 공정에서 대부분이 산화 반응을 일으키게 되어, 게이트 전극의 모양을 파괴하게 된다.As described above, most of the conductive metal film 4a that determines the conductivity of the gate electrode causes an oxidation reaction in the reoxidation process, thereby destroying the shape of the gate electrode.
재산화 공정 시에 나타나는 상기와 같은 현상은, 금속을 이용하여 게이트 전극을 형성하는 경우에 나타나는 가장 큰 문제점으로서, 게이트 전극을 구성하는 도전용 금속막(4a)의 유효 선폭이 상당히 감소하여 게이트 전극의 전도 특성을 확보하기 어렵게 만든다.This phenomenon, which occurs during the reoxidation process, is the biggest problem that occurs when forming a gate electrode using metal, and the effective line width of the conductive metal film 4a constituting the gate electrode is considerably reduced, resulting in a gate electrode. Makes it difficult to secure the conductive properties of
결국, 게이트 전극의 유효 폭이 감소할수록 게이트 전극의 저항이 증가되고, 소자의 동작 및 신뢰성이 저하되는 것이다.As a result, as the effective width of the gate electrode decreases, the resistance of the gate electrode increases, and the operation and reliability of the device deteriorate.
상기와 같은 문제점을 해결하기 위하여, 다마신(Damascene) 공정을 이용하여 게이트 전극을 형성하는 방법도 시도되고 있으나, 이러한 방법은 후에 이어지는 자기 정합 콘택 공정에서 문제점을 드러내고 있다.In order to solve the above problems, a method of forming a gate electrode using a damascene process has also been attempted, but this method has revealed a problem in a subsequent self-matching contact process.
본 발명은 상기와 같은 문제점을 해결하기 위한 것으로, 도핑된 폴리 실리콘막과 도전용 금속막의 적층 구조를 소정 형태로 패터닝하여 게이트 전극을 형성한 후에, 도전용 금속막 표면에 산화를 방지할 수 있는 금속 실리사이드막을 형성함으로써, 재산화 공정에 의한 게이트 전극의 불량을 방지하는 반도체 소자의 게이트전극 형성 방법을 제공하는데 그 목적이 있다.The present invention is to solve the above problems, after patterning the laminated structure of the doped polysilicon film and the conductive metal film in a predetermined form to form a gate electrode, which can prevent oxidation on the surface of the conductive metal film It is an object of the present invention to provide a method for forming a gate electrode of a semiconductor device in which a metal silicide film is formed to prevent defects in the gate electrode due to a reoxidation process.
도 1a 내지 도 1c는 종래의 게이트 전극 형성 방법을 설명하기 위한 각 공정별 단면도,1A to 1C are cross-sectional views of respective processes for explaining a conventional method of forming a gate electrode;
도 2a 내지 도 2e는 본 발명의 실시예에 따른, 반도체 소자의 게이트 전극을 형성하는 방법을 설명하기 위한 각 공정별 단면도.2A to 2E are cross-sectional views of respective processes for explaining a method of forming a gate electrode of a semiconductor device according to an embodiment of the present invention.
(도면의 주요 부분에 대한 부호의 명칭)(Name of the code for the main part of the drawing)
20: 반도체 기판 21: 게이트 산화막20: semiconductor substrate 21: gate oxide film
22: 도핑된 폴리 실리콘막 23: 도전용 금속막22: doped polysilicon film 23: conductive metal film
24: 산화 방지용 폴리 실리콘막 23B: 금속 실리사이드막24: polysilicon film for oxidation prevention 23B: metal silicide film
상기한 목적을 달성하기 위하여, 본 발명의 반도체 소자 게이트 전극 형성 방법은 반도체 기판 상부에 게이트 산화막과, 불순물이 도핑된 폴리 실리콘막, 도전용 금속막을 차례로 형성하는 단계와, 공지의 포토 리소그라피 공정을 통하여 도전용 금속막과, 도핑된 폴리 실리콘막을 소정 형태로 식각하는 단계와, 상기 결과물 상에 산화 방지용 폴리 실리콘막을 형성한 후에 열처리 공정을 진행하여 도전용 금속막의 표면을 금속 실리사이드막으로 상변화시키는 단계와, 산화 방지용 폴리 실리콘막을 제거한 후에 재산화 공정을 진행하는 단계를 포함하는 것을 특징으로 한다.In order to achieve the above object, the method for forming a semiconductor device gate electrode of the present invention comprises the steps of forming a gate oxide film, a polysilicon film doped with an impurity, a conductive metal film in sequence on top of the semiconductor substrate, a known photolithography process Etching the conductive metal film and the doped polysilicon film in a predetermined form, and forming an anti-oxidation polysilicon film on the resultant, followed by a heat treatment process to change the surface of the conductive metal film into a metal silicide film. And removing the anti-oxidation polysilicon film and then proceeding with the reoxidation process.
상기 도전용 금속막은 텅스텐(W), 티타늄(Ti), 몰리브덴(Mo), 탄탈륨(Ta), 알루미늄(Al), 크롬(Cr), 코발트(Co), 백금(Pt) 등 도전성이 우수한 금속을 사용하는 것을 특징으로 한다.The conductive metal film may be formed of a metal having excellent conductivity such as tungsten (W), titanium (Ti), molybdenum (Mo), tantalum (Ta), aluminum (Al), chromium (Cr), cobalt (Co), and platinum (Pt). It is characterized by using.
상기 도전용 금속막은 물리적 기상 증착법(Physical Vapor Deposition: PVD) 또는 화학적 기상 증착법(Chemical Vapor Deposition: CVD)으로 형성하는 것을 특징으로 한다.The conductive metal film may be formed by physical vapor deposition (PVD) or chemical vapor deposition (CVD).
상기 도전용 금속막은 200 내지 2,000 Å의 두께로 형성하는 것을 특징으로 한다.The conductive metal film is formed to a thickness of 200 to 2,000 kPa.
상기 산화 방지용 폴리 실리콘막은 도핑된 폴리 실리콘막, 또는 도핑되지 않은 폴리 실리콘막을 사용하는 것을 특징으로 한다.The anti-oxidation polysilicon film is characterized by using a doped polysilicon film or an undoped polysilicon film.
상기 산화 방지용 폴리 실리콘막은 화학적 기상 증착법, PE-CVD(Plasma Enhanced CVD), 또는 물리적 기상 증착법(PVD) 중의 어느 한 가지 방법을 사용하는 것을 특징으로 한다.The oxidation-resistant polysilicon film is characterized by using any one of chemical vapor deposition, PE-CVD (Plasma Enhanced CVD), or physical vapor deposition (PVD).
상기 산화 방지용 폴리 실리콘막은 50 내지 500 Å의 두께로 형성하는 것을 특징으로 한다.The anti-oxidation polysilicon film is formed to a thickness of 50 to 500 kPa.
상기 열처리 공정은 400 내지 1,000 ℃의 온도에서, 급속 열처리 공정(Rapid Thermal Annealing: RTA) 또는 튜브 열처리(Tube Annealing)로 진행하는 것을 특징으로 한다.The heat treatment process is characterized in that proceeds to Rapid Thermal Annealing (RTA) or Tube Annealing at a temperature of 400 to 1,000 ℃.
상기 산화 방지용 폴리 실리콘막은 건식 식각 또는 습식 식각 방법으로 제거하는 것을 특징으로 한다.The anti-oxidation polysilicon film may be removed by a dry etching method or a wet etching method.
이하, 첨부한 도면에 의거하여 본 발명의 바람직한 실시예를 자세히 설명하도록 한다.Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.
본 발명은 재산화 공정을 진행하기 전에 게이트 전극의 표면에 산화를 방지할 수 있는 금속 실리사이드막을 형성함으로써, 재산화 공정에서 발생하는 게이트 전극의 불량을 방지한다.The present invention forms a metal silicide film capable of preventing oxidation on the surface of the gate electrode prior to the reoxidation process, thereby preventing defects in the gate electrode generated in the reoxidation process.
도 2a 내지 도 2e는 본 발명의 실시예에 따른 게이트 전극 형성 방법을 설명하기 위한 각 공정별 단면도이다. 도면을 참조하여, 본 발명의 게이트 전극 형성 방법을 설명하면 다음과 같다.2A to 2E are cross-sectional views of respective processes for describing a method of forming a gate electrode according to an exemplary embodiment of the present invention. Referring to the drawings, the gate electrode forming method of the present invention will be described.
먼저, 도 2a에 도시된 바와 같이, 반도체 기판(20) 상에 게이트 산화막(21)을 열 성장 또는 증착 방식에 의하여 형성한 다음, 상기 게이트 산화막(21) 상에불순물이 도핑된 폴리 실리콘막(22)을 소정 두께로 증착한다.First, as shown in FIG. 2A, the gate oxide film 21 is formed on the semiconductor substrate 20 by thermal growth or vapor deposition, and then a polysilicon film doped with impurities on the gate oxide film 21 is formed. 22) is deposited to a predetermined thickness.
그런 다음, 도 2b에 도시된 바와 같이, 상기 도핑된 폴리 실리콘막(22) 상부에 도전용 금속막을 증착하고, 포토 리소그라피 공정을 통하여 도전용 금속막과, 도핑된 폴리 실리콘막(22)을 소정 형태로 패터닝 한다. 부호 23은 패터닝이 이루어진 도전용 금속막을 나타낸다.Then, as illustrated in FIG. 2B, a conductive metal film is deposited on the doped polysilicon film 22, and the conductive metal film and the doped polysilicon film 22 are predetermined through a photolithography process. Pattern in the form Reference numeral 23 denotes a conductive metal film patterned.
상기 도전용 금속막은 게이트 전극의 비저항을 낮추기 위해서, 텅스텐(W), 티타늄(Ti), 몰리브덴(Mo), 탄탈륨(Ta), 알루미늄(Al), 크롬(Cr), 코발트(Co), 백금(Pt) 등 도전성이 우수한 금속을 사용하는데, 물리적 기상 증착법(PVD) 또는 화학적 기상 증착법(CVD)을 사용하여, 200 내지 2,000 Å의 두께로 형성한다.The conductive metal film may be made of tungsten (W), titanium (Ti), molybdenum (Mo), tantalum (Ta), aluminum (Al), chromium (Cr), cobalt (Co), or platinum (T) to reduce the specific resistance of the gate electrode. A metal having excellent conductivity such as Pt) is used, and is formed to have a thickness of 200 to 2,000 kPa using physical vapor deposition (PVD) or chemical vapor deposition (CVD).
이 때, 게이트 전극을 패터닝하는 리소그라피 공정에서 게이트 산화막(21)의 표면이 손상되고, 식각 잔재물이 발생하게 되는데, 손상된 게이트 산화막(21)의 신뢰성을 회복하고, 식각 잔재물을 제거하기 위하여 재산화 공정을 진행하게 된다.At this time, in the lithography process of patterning the gate electrode, the surface of the gate oxide film 21 is damaged and etching residues are generated. In order to restore the reliability of the damaged gate oxide layer 21 and to remove the etching residues, the reoxidation process is performed. Will proceed.
이러한 재산화 공정을 진행하기 전에, 도 2c에 도시된 바와 같이, 게이트 전극이 덮이도록 산화 방지용 폴리 실리콘막(24)을 형성한다. 이는 이 후의 재산화 공정에서 도전용 금속막(23)과, 도핑된 폴리 실리콘막(22a)이 산화되는 것을 방지하기 위한 것으로, 도핑된 폴리 실리콘막 또는 도핑되지 않은 폴리 실리콘막을 사용할 수 있다.Before proceeding with this reoxidation process, as shown in Fig. 2C, an oxidation-resistant polysilicon film 24 is formed to cover the gate electrode. This is to prevent the conductive metal film 23 and the doped polysilicon film 22a from being oxidized in a subsequent reoxidation process, and a doped polysilicon film or an undoped polysilicon film may be used.
상기 산화 방지용 폴리 실리콘막(24)은 화학적 기상 증착법(CVD), PE-CVD, 또는 물리적 기상 증착법(PVD) 중의 어느 한 가지 방법을 사용하여 50 내지 500 Å의 두께로 형성하는 것이 바람직하다.The anti-oxidation polysilicon film 24 is preferably formed to a thickness of 50 to 500 kPa using any one of chemical vapor deposition (CVD), PE-CVD, or physical vapor deposition (PVD).
그리고 나서, 40 내지 1,000 ℃의 온도에서 급속 열처리 또는 튜브 열처리 공정을 진행하면, 도 2d에 도시된 바와 같이, 도전용 금속막(23)과 산화 방지용 폴리 실리콘막(24) 및 도핑된 폴리 실리콘막(22a)이 반응하여 도전용 금속막(23) 표면에 금속 실리사이드막(23B)이 형성된다.Then, if the rapid heat treatment or tube heat treatment process is performed at a temperature of 40 to 1,000 ℃, as shown in Figure 2d, the conductive metal film 23, the anti-oxidation polysilicon film 24 and the doped polysilicon film 22a reacts to form the metal silicide film 23B on the surface of the conductive metal film 23.
그 후에, 도 2e에 도시된 바와 같이, 도전용 금속막(23)과 반응하지 않고, 남아있는 산화 방지용 폴리 실리콘막(24)을 건식 식각 또는 습식 식각 방법으로 제거하고, 재산화 공정을 진행하여 손상된 게이트 산화막(21)을 회복시킨다.Thereafter, as shown in FIG. 2E, the remaining oxidation-resistant polysilicon film 24 is not reacted with the conductive metal film 23 by dry or wet etching, and the reoxidation process is performed. The damaged gate oxide film 21 is recovered.
이 때, 재산화 공정을 거치더라도, 게이트 전극을 구성하는 도전용 금속막(23A)은 표면에 형성된 금속 실리사이드막(23B)에 의하여 손상이 방지되기 때문에, 도전용 금속막(23A)의 선폭이 감소하거나, 게이트 전극의 모양이 파괴되는 것을 막을 수 있다.At this time, even if the reoxidation process is performed, since the conductive metal film 23A constituting the gate electrode is prevented from being damaged by the metal silicide film 23B formed on the surface, the line width of the conductive metal film 23A is increased. It can reduce or prevent the shape of the gate electrode from being destroyed.
그 후에, 공지된 순서에 의거하여, 게이트 전극의 측면에 스페이서를 형성하고, 불순물 이온을 주입하여 소오스/드레인 영역을 형성함으로써 게이트 전극을 완성시킨다.After that, a spacer is formed on the side of the gate electrode according to a known procedure, and impurity ions are implanted to form a source / drain region to complete the gate electrode.
상기에서는 도전용 금속막을 이용하여 게이트 전극을 형성하는 경우를 예로 들어 설명하였으나, 게이트 전극뿐만 아니라 워드 라인이나, 비트 라인 등 금속막을 이용하여 금속 라인을 형성하는 경우에도 동일하게 적용 가능하다.In the above, the case where the gate electrode is formed by using the conductive metal film is described as an example. However, the same applies to the case where the metal line is formed by using not only the gate electrode but also a metal film such as a word line or a bit line.
이상에서 자세히 설명한 바와 같이, 본 발명의 게이트 전극 형성 방법에 따르면, 게이트 전극을 형성하는 도전용 금속막이 재산화 공정에서 산화되는 것을 방지함으로써, 게이트 전극의 모양이 파괴되는 것을 막을 수 있다.As described in detail above, according to the gate electrode forming method of the present invention, by preventing the conductive metal film forming the gate electrode from being oxidized in the reoxidation process, the shape of the gate electrode can be prevented from being destroyed.
따라서, 정밀한 패턴의 게이트 전극을 형성하고, 금속을 이용한 게이트 전극의 전도 특성이 약화되는 것을 방지함으로써, 반도체 소자의 동작 특성을 향상시키고, 신뢰성을 확보할 수 있다.Therefore, by forming the gate electrode of a precise pattern and preventing the conduction characteristic of the gate electrode using a metal from being weakened, the operation characteristic of a semiconductor element can be improved and reliability can be ensured.
이하, 본 발명은 그 요지를 일탈하지 않는 범위에서 다양하게 변경하여 실시할 수 있다.Hereinafter, this invention can be implemented in various changes in the range which does not deviate from the summary.
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