KR20000023446A - Expitaxial wafer and method for manufacturing the same and method for cleaning surface of compound semiconductor substrated using in the same - Google Patents
Expitaxial wafer and method for manufacturing the same and method for cleaning surface of compound semiconductor substrated using in the same Download PDFInfo
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- KR20000023446A KR20000023446A KR1019990041237A KR19990041237A KR20000023446A KR 20000023446 A KR20000023446 A KR 20000023446A KR 1019990041237 A KR1019990041237 A KR 1019990041237A KR 19990041237 A KR19990041237 A KR 19990041237A KR 20000023446 A KR20000023446 A KR 20000023446A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/34—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies not provided for in groups H01L21/0405, H01L21/0445, H01L21/06, H01L21/16 and H01L21/18 with or without impurities, e.g. doping materials
- H01L21/46—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/428
- H01L21/461—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/428 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/465—Chemical or electrical treatment, e.g. electrolytic etching
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
Abstract
Description
본 발명은, 에피택셜웨이퍼 및 그 제조방법 및 그것에 사용되는 화합물반도체기판의 표면청정화방법에 관한 것이며, 특히, 발광디바이스등의 반도체디바이스에 사용되는 Ⅱ-Ⅵ족계 화합물반도체기판을 구비한 에피택셜웨이퍼 및 그 제조방법 및 이 기판의 표면청정화방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an epitaxial wafer, a method for producing the same, and a method for surface cleaning of a compound semiconductor substrate used therein, and in particular, an epitaxial wafer having a group II-VI compound semiconductor substrate used for semiconductor devices such as light emitting devices. And a method for producing the same and a method for surface cleaning of the substrate.
일반적으로, Ⅱ-Ⅵ족계 화합물반도체기판은, 벌크결정으로부터 슬라이스나 연마등에 의해 기판형상으로 형성된다. 이때, 기판표면에는, 「가공변형층」이라는 결정성이 나쁜층이 발생한다. 이 기판표면에 존재하는 가공변형층은, 에피택셜층을 성장하기 전에 청정화처리해서 제거하는 것이 필요하다.In general, a group II-VI compound semiconductor substrate is formed into a substrate shape by slicing, polishing, or the like from a bulk crystal. At this time, a layer with poor crystallinity called a "processing strain layer" occurs on the substrate surface. The processing strained layer present on the substrate surface needs to be cleaned and removed before the epitaxial layer is grown.
종래, Ⅱ-Ⅵ족계 화합물반도체기판중에, 예를 들면 ZnSe기판의 습식표면청정화방법으로서는, 일본국 문헌 1(1997년 춘기제 44회 응용물리학회학술강연예교집P.273, 29a-p-4) 또는 일본국 문헌 2(특개평 7-307528호 공보)에 개시되어 있는 바와 같이, 2크롬산칼륨/황산/물로 이루어진 에칭액을 사용해서, 에칭하는 방법이 있었다.Conventionally, as a wet surface cleaning method of a ZnSe substrate, for example, in a group II-VI compound semiconductor substrate, Japanese literature 1 (44th Spring Conference of the Society of Applied Physics, 1997.P.273, 29a-p-4) ) Or Japanese Patent Application Laid-Open No. 7-307528, there was a method of etching using an etching solution composed of potassium dichromate / sulfuric acid / water.
반도체디바이스중에, 예를 들면 레이저다이오드 등의 발광디바이스에 있어서는, 디바이스구조속의 결정결함이, 수명등의 디바이스특성에 악영향을 미치는 것이 알려져 있다.Among semiconductor devices, for example, in light emitting devices such as laser diodes, it is known that crystal defects in a device structure adversely affect device characteristics such as lifetime.
그러나, 상기한 바와 같은 종래의 방법에 의해 표면을 청정화한 Ⅱ-Ⅵ족계 화합물반도체기판상에 디바이스의 적층구조를 분자선에피택셜법(MBE법)등에 의해 형성했을 경우에는, 기판과그 위에 성장되는 Ⅱ-Ⅵ족계 화합물반도체에피택셜층과의 계면에서, 결정결함이 새로이 고밀도로 발생하고, 결정결함의 하나인 전위가, 기판의 표면에서 새로히 발생하고, 디바이스특성이 크게 손상된다고 하는 문제가 있었다. 예를 들면 ZnSe의 경우에서는, 기판의 표면에서 새로이 전위가 104㎝-2이상 발생한다.However, when the stacked structure of the device is formed by the molecular beam epitaxial method (MBE method) or the like on the II-VI compound semiconductor substrate which has been cleaned by the conventional method as described above, it is grown on the substrate and thereon. At the interface with the II-VI compound semiconductor epitaxial layer, there is a problem that crystal defects are newly generated at high density, dislocations, which are one of the crystal defects, are newly generated at the surface of the substrate, and the device characteristics are largely damaged. For example, in the case of ZnSe, the dislocation newly arises 10 4 cm <-2> or more from the surface of a board | substrate.
본 발명의 목적은, 상기한 문제점을 해결하고, 기판표면이 경면으로, 평활성, 청정성에 뛰어나고, 또한 에피택셜층을 성장했을때에, 반도체디바이스의 특성에 다대한 악영향을 미치게하는 결정결함의 밀도를 저감할 수 있는, Ⅱ-Ⅵ족계 화합물반도체기판의 표면청정화방법을 제공하는 데 있다.Disclosure of Invention The object of the present invention is to solve the above-mentioned problems, and the density of crystal defects to have a bad effect on the characteristics of the semiconductor device when the substrate surface is mirror surface, excellent in smoothness and cleanliness, and when the epitaxial layer is grown. The present invention provides a method for surface cleaning of a group II-VI compound semiconductor substrate, which can be reduced.
또, 본원 발명의 더한층의 목적은, 이 화합물반도체기판의 표면청정화방법을 사용한 에피택셜웨이퍼를 제조함으로써, 기판표면에서 새로히 발생하는 전위밀도가 저감되는 에피택셜웨이퍼를 제공하는 데 있다.It is a further object of the present invention to provide an epitaxial wafer in which the dislocation density newly generated on the surface of the substrate is reduced by manufacturing an epitaxial wafer using the method for surface-cleaning the compound semiconductor substrate.
도 1은, 벌크결정으로부터 잘라내어 경면연마한 직후의 ZnSe기판의 표면상태를 표시한 사진1 is a photograph showing the surface state of a ZnSe substrate immediately after being cut out from a bulk crystal and subjected to mirror polishing.
도 2는, 가공변형층을 에칭제거한 후의 ZnSe기판의 표면상태를 표시한 사진Fig. 2 is a photograph showing the surface state of the ZnSe substrate after etching away the processing strain layer.
도 3은, 에피택셜웨이퍼의 구조를 표시한 단면도3 is a cross-sectional view showing the structure of the epitaxial wafer.
도 4는, 에칭량과 ZnSe기판의 표면거칠음과의 관계를 표시한 도면4 shows the relationship between the etching amount and the surface roughness of the ZnSe substrate.
도 5는, 에칭량과 기판표면에서 새로이 발생한 ZnSe막속의 전위밀도와의 관계를 표시한 도면Fig. 5 is a graph showing the relationship between the etching amount and the dislocation density of the newly formed ZnSe film in the substrate surface.
도 6은, 2크롬산칼륨/황산/물로 이루어진 에칭액을 사용해서, ZnSe기판을 에칭하는 과정을 표시한 모델의 모식도FIG. 6 is a schematic diagram of a model showing a process of etching a ZnSe substrate using an etching solution composed of potassium dichromate / sulfuric acid / water.
도 7은, 에칭후의 기판의 표면상태를 표시한 사진7 is a photograph showing the surface state of a substrate after etching.
도 8은, 에칭후의 기판의 표면상태를 표시한 사진8 is a photograph showing the surface state of the substrate after etching.
도 9는, 에칭후의 기판의 표면상태를 표시한 사진9 is a photograph showing the surface state of a substrate after etching.
도 10은, 에칭후의 기판의 표면상태를 표시한 사진10 is a photograph showing the surface state of a substrate after etching.
도 11은, 에칭후의 기판의 표면상태를 표시한 사진11 is a photograph showing a surface state of a substrate after etching
<도면의 주요부분에 대한 부호의 설명><Description of the symbols for the main parts of the drawings>
1: ZnSe기판 2: ZnSe에피택셜층1: ZnSe substrate 2: ZnSe epitaxial layer
본원 발명에 의한 화합물반도체기판의 표면청정화방법은, Ⅱ-Ⅵ족계 화합물반도체기판의 표면의 가공변형층을 제거하는 공정과, 가공변형층이 제거된 화합물반도체기판의 표면을 에칭액을 사용해서 에칭하는 공정을 구비하고 있다.According to the present invention, a method for surface cleaning of a compound semiconductor substrate includes a step of removing a strain layer on the surface of a group II-VI compound semiconductor substrate, and etching the surface of the compound semiconductor substrate from which the strain layer has been removed using an etching solution. It is equipped with a process.
본원 발명에 있어서, 화합물반도체기판의 표면의 가공변형층을 제거하는 방법으로서는, 2크롬산칼륨/황산/물로 이루어진 에칭액, 과산화수소수/암모니아수로 이루어진 에칭액, 또는 과산화수소수/황산으로 이루어진 에칭액등을 사용해서, 습식에칭하는 방법을 들 수 있다. 또, 할로겐원소를 함유하는 반응성가스를 사용해서, 건식에칭할수도 있다. 또, 에칭에 한정되지 않고, 물리적인방법에 의해 제거하는 것도 가능하다.In the present invention, as a method of removing the processing strain layer on the surface of the compound semiconductor substrate, an etching solution composed of potassium dichromate / sulfuric acid / water, an etching solution composed of hydrogen peroxide solution / ammonia water, an etching solution composed of hydrogen peroxide solution / sulfuric acid, or the like is used. And wet etching. It is also possible to dry etch using a reactive gas containing a halogen element. Moreover, it is not limited to an etching but can also remove by a physical method.
또, 본원 발명에 있어서, 가공변형층이 제거된 화합물반도체기판의 표면을 에칭할때에는, 에칭액으로서, 황산을 60∼98중량%, 보다 바람직하게는, 80∼96중량%, 2크롬산칼륨을 0.1중량%∼포화의 비율로 함유하는 수용액을 사용하는 것이 바람직하다.In the present invention, when etching the surface of the compound semiconductor substrate from which the processing strained layer has been removed, 60 to 98% by weight of sulfuric acid, more preferably 80 to 96% by weight and potassium dichromate, are used as the etching solution. It is preferable to use the aqueous solution containing in the ratio of weight%-saturation.
황산의 함유량에 대해서는, 60중량%미만의 에칭액을 사용했을 경우에는, 경면이지만 기판표면에 거칠음이나 피트가 발명하거나, 혹은 표면거칠름이 심하여 경면을 얻을 수 없게 되어 버리기 때문이다. 한편, 황산의 함유량이 98중량%보다도 많은 에칭액을 사용했을 경우에는, 경면이지만 기판표면에 미소한 피트가 다수 발생하거나, 혹은 표면에 Ⅵ족원소가 석출하여 경면을 얻을 수 없게 되어 버리기 때문이다. 또, 2크롬산칼륨의 함유량에 대해서는, 0.1중량%미만의 에칭액을 사용했을 경우, 에칭속도가 대단히 지연되고, 실용에 제공할 수 없게 되어 버리기 때문이다.This is because when the etching solution of less than 60% by weight is used for the content of sulfuric acid, roughness or pits are invented on the surface of the substrate, or the surface roughness is so severe that the mirror surface cannot be obtained. On the other hand, when an etching solution containing more than 98% by weight of sulfuric acid is used, a large number of minute pits are generated on the surface of the substrate, but a group VI element precipitates on the surface, and thus the mirror surface cannot be obtained. Moreover, when content of potassium dichromate is less than 0.1 weight%, when etching liquid is used, an etching rate will be delayed very much and it will become impossible to provide practically.
또, 본원 발명에 있어서, 가공변형층이 제거된 화합물반도체기판의 표면을 에칭할 때에는, 화합물반도체기판의 표면을, 0.01∼3㎛의 범위의 두께로, 보다 바람직하게는 0.1∼1㎛의 범위의 두께로 에칭제거하는 것이 바람직하다.In the present invention, when etching the surface of the compound semiconductor substrate from which the processing strain layer has been removed, the surface of the compound semiconductor substrate has a thickness in the range of 0.01 to 3 µm, more preferably in the range of 0.1 to 1 µm. It is preferable to remove the etching to a thickness of.
3㎛보다 두껍게 에칭했을 경우에는, 기판표면의 거칠음이 커지게 되어, 에피택셜층을 성장했을 때에, 기판표면에서 새로이 발생하는 전위밀도도 증대해버리기 때문이다. 한편, 에칭의 두께가 0.01㎛보다도 얇은 경우에는, 에칭후의 기판의 표면상태의 재현성이 악화되어 버리기 때문이다.This is because when the etching is thicker than 3 mu m, the roughness of the substrate surface becomes large, and when the epitaxial layer is grown, the dislocation density newly generated on the substrate surface also increases. On the other hand, it is because the reproducibility of the surface state of the board | substrate after etching deteriorates when the thickness of an etching is thinner than 0.01 micrometer.
또한, 본원 발명에 있어서, 화합물반도체기판의 표면의 가공변형층을 제거하는 공정과, 가공변형층이 제거된 화합물반도체기판의 표면을 에칭하는 공정과는, 동일에칭액을 사용해서 에칭할 수도 있다. 다만, 이 경우에는, 가공변형층을 제거하기 위한 에칭을 행한 후에, 일단에칭처리를 중단해서, 기판표면을 물등을 사용해서 세정한 후에, 재차에칭을 재개하는 것이 바람직하다.In the present invention, the step of removing the strain layer on the surface of the compound semiconductor substrate and the step of etching the surface of the compound semiconductor substrate from which the strain layer is removed may be etched using the same etching solution. In this case, however, it is preferable to stop the etching process once after the etching for removing the work strain layer, and to wash the substrate surface with water or the like, and then resume etching again.
본원 발명에 있어서의 Ⅱ-Ⅵ족계 화합물반도체기판 결정에는, ZnSe가 함유된다. 또 상기의 어느 하나의 방법에 의해 표면이 청정화된 화합물반도체기판상에, 에피택셜층을 형성하는 에피택셜웨이퍼의 제조방법도 본원 발명에 포함된다. 또한, 상기 에피택셜웨이퍼는, Ⅱ-Ⅵ족계 화합물반도체기판과, 상기 화합물반도체기판상에 형성된 에피택셜층을 구비하고, 상기 화합물반도체기판의 표면에서 새로이 발생한 전위밀도가, 104㎝-2미만인 것을 특징으로 하는, 에피택셜웨이퍼도 본원 발명에 포함된다.ZnSe is contained in the II-VI type compound semiconductor substrate crystal | crystallization in this invention. The present invention also includes a method for producing an epitaxial wafer which forms an epitaxial layer on a compound semiconductor substrate whose surface is cleaned by any of the above methods. In addition, the epitaxial wafer includes a group II-VI compound semiconductor substrate and an epitaxial layer formed on the compound semiconductor substrate, and the potential density newly generated on the surface of the compound semiconductor substrate is less than 10 4 cm -2. An epitaxial wafer, characterized in that the invention is also included in the present invention.
Ⅱ-Ⅵ족계 화합물반도체기판상에, 에피택셜기술에 의해 고품질의 Ⅱ-Ⅵ족계 화합물반도체박막을 형성해서 에피택셜웨이퍼를 제조할때에, 특히, 기판의 표면청정화방법에 대해서의 최적조건을 검토하기 위해, 하기의 실험을 행하였다.When forming epitaxial wafers by forming a high quality II-VI compound semiconductor thin film on the II-VI compound semiconductor substrate by epitaxial technology, in particular, the optimum conditions for the surface-cleaning method of the substrate are examined. In order to do this, the following experiment was performed.
(실시예 1)(Example 1)
ZnSe벌크결정으로부터, 슬라이스 및 연마에 의해, 면방위가 (100)면의 ZnSe기판을 제작했다.From the ZnSe bulk crystals, a ZnSe substrate having a plane orientation (100) plane was produced by slicing and polishing.
도 1은, 이와 같이 해서 제작한 ZnSe기판의 표면상태를 표시한 사진이다. 또한, 기판표면을 관찰할때에는, 전위, 그외의 결함을 표출시키는 Br-메타놀용액에 기판을 침지한 후에, 관찰을 행하였다.Fig. 1 is a photograph showing the surface state of the ZnSe substrate thus produced. In addition, when observing the surface of the substrate, the substrate was immersed in a Br- ethanol solution that exhibits dislocations and other defects, followed by observation.
도 1을 참조해서, 벌크결정으로부터 잘라내고 경면연마한 직후의 ZnSe기판표면에는, 가늘고긴 에치피트가 복수개 관찰되었다. 이 가늘고긴 에치피트는, 기판의 전위의 존재위치에 대응하고 있다.Referring to Fig. 1, a plurality of thin etch pits were observed on the surface of the ZnSe substrate immediately after being cut out from the bulk crystal and subjected to mirror polishing. This thin etch pit corresponds to the position at which the potential of the substrate is present.
또, 이 ZnSe기판에 있어서는, 기판의 전위의 외에, 사진의 상부중앙으로부터 우하에 걸쳐서, 또 좌하로부터 우상에 걸쳐서, 띠형상으로 연속되는 결함이 관찰된다. 이 띠형상으로 연속되는 결함은, 벌크결정으로부터 잘라내어 연마까지의 가공에 의해 발생한 기판표면의 가공변형층의 존재를 시사하고 있다.In addition, in this ZnSe substrate, in addition to the potential of the substrate, defects that are continuous in a band form are observed from the upper middle to the lower right of the photograph, and from the lower left to the upper right. This continuous band-like defect suggests the presence of a processing strain layer on the surface of the substrate generated by cutting from the bulk crystal to polishing.
ZnSe기판의 표면에 존재하는 이 가공변형층을 제거하지 않고, 기판상에 ZnSe에피택셜층을 형성하면, 에피택셜층의 결정성이 악화된다. 그래서, 이 가공변형층을 제거하기 위해, 2크롬산 칼륨/황산/물로 이루어진 에칭액을 사용해서, ZnSe기판표면을, 두께 5㎛에칭제거하였다.If the ZnSe epitaxial layer is formed on the substrate without removing the processing strain layer present on the surface of the ZnSe substrate, the crystallinity of the epitaxial layer is deteriorated. Then, in order to remove this processing strain layer, the etching surface of potassium dichromate / sulfuric acid / water was used, and the surface of ZnSe substrate was etched away by 5 micrometers in thickness.
도 2는, 가공변형층을 에칭제거한 후의 ZnSe기판의 표면상태를 표시한 사진이다. 또한, 도 1과 마찬가지로, Br-메타놀용액에 침지한 후에 관찰한 것이다.Fig. 2 is a photograph showing the surface state of the ZnSe substrate after etching away the processing strain layer. In addition, as shown in Fig. 1, the immersion was carried out in Br-Methanol solution.
도 2를 참조해서, 이 기판의 표면에는, 전위에 대응하는 가늘고 긴에치피트는 관찰되나, 가공변형층에 대응하는 띠형상으로 연속되는 결함은 관찰되지 않았다. 따라서, 기판표면을 5㎛의 두께로 에칭제거함으로써, 가공변형층은 완전히 제거할 수 있었던 것을 알 수 있다.Referring to Fig. 2, on the surface of the substrate, thin and long etch pits corresponding to the dislocations were observed, but no defects that continued in a band shape corresponding to the processing strain layer were observed. Therefore, it can be seen that by removing the substrate surface with a thickness of 5 占 퐉, the processed strained layer could be completely removed.
다만, 가공변형층의 두께는, 벌크결정으로부터 기판을 잘라내기 위한 슬라이스, 연마 등의 가공처리의 종류, 조건 등에 따라 다르기 때문에, 에칭하는 두께는 반드시 5㎛로 한정되는 것이 아니고, 가공변형층을 완전히 제거하는 두께에 적당히 설정되는 것이 바람직하다.However, since the thickness of the strained deformation layer varies depending on the kind, conditions, and the like of cutting, polishing, etc. for cutting out the substrate from the bulk crystal, the thickness to be etched is not necessarily limited to 5 μm, It is preferable to set suitably to the thickness which removes completely.
다음에, 이 가공변형층이 제거된 ZnSe기판을, 1×10-10Torr의 박막성장실내에 도입하고, 350℃에서 30분간의 수소플라즈마클리닝을 한후에, MBE법에 의해 기판상에 ZnSe에피택셜층을 형성해서, 에피택셜웨이퍼를 제작하였다.Next, the ZnSe substrate from which the processed strained layer was removed was introduced into a thin film growth chamber of 1 × 10 -10 Torr, subjected to hydrogen plasma cleaning at 350 ° C. for 30 minutes, and then ZnSe epitaxial on the substrate by the MBE method. The shir layer was formed to produce an epitaxial wafer.
도 3은, 이와같이해서 얻어진 에피택셜웨이퍼의 구조를 표시한 단면도이다.3 is a cross-sectional view showing the structure of the epitaxial wafer thus obtained.
도 3을 참조해서, 이 에피택셜웨이퍼는, ZnSe기판(1)위에, ZnSe에피택셜층(2)가 형성되어 있다.Referring to Fig. 3, in the epitaxial wafer, a ZnSe epitaxial layer 2 is formed on the ZnSe substrate 1.
이 에피택셜웨이퍼에 대해서, 전위밀도를 측정했던바, 기판의 표면에서 새로이 발생한 전위밀도는, 3×104㎝-2인 것을 알 수 있었다. 또한, 본원 명세서에 있어서, 「기판의 표면에서 새로이 발생한 전위밀도」란, 에피택셜층에 있어서, 기판자체에 존재하는 전위로부터 이어받은 전위를 제외하고, 기판과의 계면에서 새로이 발생한 전위밀도를 말한다.The dislocation density was measured for this epitaxial wafer. As a result, it was found that the dislocation density newly generated on the surface of the substrate was 3 × 10 4 cm −2 . In addition, in this specification, the "dislocation density newly generate | occur | produced on the surface of a board | substrate" means the dislocation density newly generated at the interface with a board | substrate except the potential inherited from the potential which exists in the board | substrate itself in an epitaxial layer. .
다음에, 본원 발명에 따라, 가공변형층을 제거한 ZnSe기판의 표면을, 2크롬산칼륨/황산/물로 이루어진 에칭액을 사용해서, 두께 0.5㎛에칭제거했다.Next, according to the present invention, the surface of the ZnSe substrate from which the strained layer was removed was etched away in thickness of 0.5 mu m using an etching solution composed of potassium dichromate / sulfuric acid / water.
이와 같이, 본원 발명에 따라 표면을 청정화한 ZnSe기판을, 1×10-10Torr의 박막성장실내에 도입하고, 350℃에서 30분간의 수소플라즈마클리닝을 한후에, MBE법에 의해 기판위에 ZnSe에피택셜층을 형성해서, 도 3에 표시한 구조의 에피택셜웨이퍼를 제작했다.As described above, a ZnSe substrate whose surface is cleaned in accordance with the present invention is introduced into a thin film growth chamber of 1 × 10 -10 Torr, subjected to hydrogen plasma cleaning at 350 ° C. for 30 minutes, and then ZnSe epitaxial on the substrate by the MBE method. The shir layer was formed, and the epitaxial wafer of the structure shown in FIG. 3 was produced.
이와 같이 해서 얻게된 본원 발명에 따라 에피택셜웨이퍼에 대해서, 전위밀도를 측정하였던바, 기판의 표면에서 새로히 발생한 전위밀도는, 3×103㎝-2이며, 104㎝-2를 하회하고 있는 것을 알게되었다.According to the present invention thus obtained, the dislocation density was measured for the epitaxial wafer. The dislocation density newly generated on the surface of the substrate was 3 × 10 3 cm −2 , which was less than 10 4 cm −2 . I found out.
이는, 본 발명에 의한 기판의 표면청정화방법에 의해, ZnSe기판의 표면은, 경면이고, 또한 평활성, 청정성에 뛰어난 것으로 되어 있기 때문에, 에피택셜층을 성장했을때에, 기판의 표면에 새로이 발생하는 결정결함이 저감된 것으로 생각할 수 있다.This is because the surface of the ZnSe substrate is mirror surface, and excellent in smoothness and cleanliness by the method for surface cleaning of the substrate according to the present invention. Therefore, when the epitaxial layer is grown, the surface of the substrate is newly generated. It can be considered that crystal defects are reduced.
(실시예 2)(Example 2)
발명자들은, 실시예 1과 마찬가지의 조건에서, ZnSe기판의 표면을 청정화할때의 에칭조거에 대해서 여러가지의 검토를 행하였다. 그 결과, 가공변형층이 제거된 ZnSe기판의 표면을 에칭할때의 에칭량(에칭의 두께)에 따라서, 기판의 평탄성이 변동하고, 에피택셜층형성후에 새로이 발생하는 전위수에도 영향을 미치는 것을 발견하였다.The inventors carried out various studies on the etching action when the surface of the ZnSe substrate was cleaned under the same conditions as in Example 1. As a result, the flatness of the substrate fluctuates depending on the etching amount (etching thickness) when etching the surface of the ZnSe substrate from which the processing strain layer is removed, and also affects the number of dislocations newly generated after epitaxial layer formation. Found.
이하, 이에 대해서 상세히 설명한다.This will be described in detail below.
실시예 1과 마찬가지의 조건에서, 벌트결정으로부터 잘라내어 경면연마한 ZnSe기판의 표면을, 2크롬산칼륨/황산/물로 이루어진 에칭액을 사용해서 두께 5㎛에칭제거함으로써, 가공변형층을 제거했다.Under the same conditions as those in Example 1, the surface of the ZnSe substrate cut off from the bulk crystal and subjected to mirror polishing was etched away using a etching solution composed of potassium dichromate / sulfuric acid / water with a thickness of 5 µm to remove the strain layer.
다음에, ZnSe기판의 표면을 물로 일단세정한 후에, 재차 2크롬산칼륨/황산/물로 이루어진 에칭액을 사용해서, 기판의 표면을 여러가지의 두께로 에칭제거했다.Next, after the surface of the ZnSe substrate was once washed with water, the surface of the substrate was etched away in various thicknesses using an etching solution composed of potassium dichromate / sulfuric acid / water.
도 4는, 에칭후의 ZnSe기판표면을, 원자간력현미경에 의해 관찰하고, 표면거칠음을 측정한 결과를 표시한 도면이다. 표면걸칠음은, 측정영역에 있어서의 각측정점높이의 표준편차인 RMS치로서 나타내고 있다. 도 4에 있어서, 횡축은 에칭된 두께인 에칭량(㎛)을 표시하고, 종축은 ZnSe기판의 표면거칠음인 RMS치(Å)를 표시하고 있다.Fig. 4 is a view showing the results of measuring the surface roughness after observing the surface of the ZnSe substrate after etching with an atomic force microscope. Surface roughness is expressed as an RMS value which is a standard deviation of the height of each measuring point in the measurement area. In Fig. 4, the horizontal axis represents the etching amount (占 퐉) which is the etched thickness, and the vertical axis represents the RMS value of the surface roughness of the ZnSe substrate.
도 4를 참조해서, RMS치는, 에칭량에 따라서 변동하고, 에칭개시직후에서는 PMS치가 저감해서, 기판표면이 평탄화하나, 에칭량이 지나치게 많으면, RMS치가 증대해버리는 것을 알게 되었다. 즉, 경면이며 평활성에 뛰어난 기판표면을 얻기 위해서는, 에칭량의 상한은 3㎛, 보다 바람직하게는 1㎛이하가 좋은 것을 알게되었다. 한편, 에칭량의 하한에 대해서는, 0.01㎛이상정도가 필요한 것을 알게되었다. 이는, 에칭량이 지나치게 적으면, 표면상태의 재현성이 악화해버리기 때문이다.Referring to Fig. 4, it was found that the RMS value changes depending on the etching amount, and immediately after the etching start, the PMS value decreases and the substrate surface is flattened, but when the etching amount is too large, the RMS value increases. In other words, in order to obtain a substrate surface having a mirror surface and excellent in smoothness, it has been found that the upper limit of the etching amount is 3 µm, more preferably 1 µm or less. On the other hand, it turned out that about 0.01 micrometer or more is needed about the minimum of an etching amount. This is because if the etching amount is too small, the reproducibility of the surface state deteriorates.
다음에, 여러가지의 두께로 표면을 에칭한 ZnSe기판위에, 실시예 1과 마찬가지의 조건에서, ZnSe에피택셜층을 형성하고, 에피택셜웨이퍼를 제작했다.Next, a ZnSe epitaxial layer was formed on the ZnSe substrate whose surface was etched by various thickness on the conditions similar to Example 1, and the epitaxial wafer was produced.
도 5는 얻게된 에피택셜웨이퍼에 있어서, 기판표면에서 새로이 발생한 전위밀도를 표시한 도면이다. 도 5에 있어서, 횡축은 에칭된 두께인 에칭량(㎛)을 표시하고, 종축은 기판표면에서 새로이 발생한 ZnSe막속의 전위밀도(㎝-2)를 표시하고 있다.FIG. 5 is a diagram showing dislocation density newly generated on the surface of the substrate in the obtained epitaxial wafer. In Fig. 5, the horizontal axis represents the etching amount (占 퐉) which is the etched thickness, and the vertical axis represents the dislocation density (cm -2 ) of the newly generated ZnSe film in the substrate surface.
도 5를 참조해서, 도 4에 표시한 기판표면의 평탄성이 뛰어나 있는 영역에 있어서는, 기판의 표면에서 새로이 발생한 전위밀도는 낮아지는 것을 알게되었다. 즉, 에칭량이 0.01㎛이상, 3㎛이하, 보다 바람직하게는 1㎛이하일때에, 기판표면에서 새로이 발생하는 전위밀도가 104㎝-2를 하회하고, 저결함밀도로서 고품질의 ZnSe에피택셜층의 형성이 가능하게 되는 것이 알게되었다.Referring to FIG. 5, it was found that the dislocation density newly generated on the surface of the substrate is lowered in the region having excellent flatness of the substrate surface shown in FIG. 4. That is, when the etching amount is 0.01 µm or more and 3 µm or less, more preferably 1 µm or less, the dislocation density newly generated on the substrate surface is less than 10 4 cm -2 , and the ZnSe epitaxial layer of high quality with low defect density is present. It was found that the formation of.
여기서, 에칭량이 지나치게 많으면, 기판표면의 평활성이 저하하고, 결함밀도도 증대해버리는 이유로서는, 이하와 같은 것을 고려할 수 있다.Here, when the amount of etching is too large, the following can be considered as a reason that the smoothness of the substrate surface falls and the defect density also increases.
도 6은, 2크롬산칼륨/황산/물로 이루어진 에칭액을 사용해서, ZnSe기판을 에칭하는 상태의 모델의 모식도이다.6 is a schematic diagram of a model in a state in which a ZnSe substrate is etched using an etching solution composed of potassium dichromate / sulfuric acid / water.
먼저, 도 6(A)를 참조해서, ZnSe기판을 에칭액에 침지하면, 2크롬산(Cr2O7)이온의 작용에 의해, 아연은 아연이온으로 되어서 에칭액중에 용출한다. 한편, 셀렌은, 2크롬산이온과 반응해서 일단 산화셀렌(SeOx)으로된 후에, 셀렌이온으로되어서 에칭액중에 용출한다. Se의 산화반응의 속도가 느리기 때문에, 에칭이 진행하면, 도 6(B)에 표시한 바와 같이, 기판표면에는 Se가 석출하여, 표면의 평활성이 손상되어 버린다.First, referring to FIG. 6 (A), when a ZnSe substrate is immersed in an etching solution, zinc becomes an ion of zinc and elutes in the etching solution by the action of dichromic acid (Cr 2 O 7 ) ions. On the other hand, selenium reacts with dichromate ions and once becomes selenium oxide (SeOx), and then becomes selenium ions and elutes in the etching solution. Since the rate of oxidation of Se is slow, when etching proceeds, as shown in Fig. 6B, Se precipitates on the surface of the substrate and the smoothness of the surface is impaired.
이 실시예에서는, 기판의 가공변형층을 제거하기 위해, 2크롬산 칼륨/황산/물로 이루어진 에칭액을 사용한 에칭을 행하였다. 따라서, 가공변형층을 제거한 직후의 ZnSe기판표면은, 도 6(B)에 표시한 바와 같이, Se가 많이 석출되고 있는 상태인 것으로 생각할 수 있다. 이대로 에칭을 계속해도, 기판표면에서는, 2크롬산이온의 확산속도가 느리기 때문에, Se의 산화반응의 속도도 느리게되어, 기판표면에는 Se가 더욱 석출하게 된다.In this embodiment, etching was performed using an etching solution composed of potassium dichromate / sulfuric acid / water in order to remove the processing strain layer of the substrate. Therefore, it is considered that the surface of the ZnSe substrate immediately after removing the processing strained layer is in a state in which Se is precipitated, as shown in Fig. 6B. Even if etching is continued as described above, since the diffusion rate of dichromate ions is slow on the substrate surface, the oxidation reaction of Se is also slowed, and Se is further precipitated on the substrate surface.
그러나, 본원 발명에 의하면, 여기서, 일단에칭을 중단해서 기판표면을 세정하고, 재차 에칭을 개시한다. 그 때문에, 기판표면의 2크롬산이온농도는 충분히 많아지기 때문에, 표면에 석출한 Se가 급속하게 산화한다. 이 급속한 산화공정을 통해서, 기판표면의 Se는 용출하고, 기판표면의 평활성이 개선된다.However, according to the present invention, the etching is stopped once, the substrate surface is cleaned, and etching is started again. Therefore, since the dichromate ion concentration of the substrate surface is sufficiently increased, Se precipitated on the surface rapidly oxidizes. Through this rapid oxidation process, Se on the substrate surface elutes and smoothness of the substrate surface is improved.
그러나, 다시 에칭이 진행되면, 기판표면에서의 2크롬산이온의 확산속도가 재차 지연되기 때문에, Se의 산화반응속도도 지연된다. 그 결과, 기판표면에 재차 Se가 축적되어, 기판의 표면평활성이 손상되는 것으로 생각할 수 있다.However, when etching proceeds again, since the diffusion rate of dichromate ions on the substrate surface is delayed again, the oxidation reaction rate of Se is also delayed. As a result, it is considered that Se accumulates again on the substrate surface, and the surface smoothness of the substrate is impaired.
(실시예 3)(Example 3)
발명자들은, 계속해서, ZnSe기판의 표면을 청정화할때의 에칭조건중에, 2크롬산칼륨/황산/물로 이루어진 에칭액의 조성의 최적조건에 대해서 검토를 행하였다.The inventors then examined the optimum conditions of the composition of the etching solution consisting of potassium dichromate / sulfuric acid / water during the etching conditions when the surface of the ZnSe substrate was cleaned.
먼저, 2크롬산칼륨의 농도에 대해서는, 0.1중량%보다 작은 경우에는, 에칭속도가 대단히 느리기 때문에, 실용으로 제공될 수 없는 것을 알게되었다.First, it was found that when the concentration of potassium dichromate is less than 0.1% by weight, since the etching rate is very slow, it cannot be practically provided.
그래서, 2크롬산칼륨의 농도범위를 0.1중량%∼포화까지로하고, 황산농도를 H2SO4＜60중량%(조건A), 60%≤H2SO4≤98중량%(조건B), H2SO4＞98중량%(조건C)의 3종류로해서, 에칭액을 조정하고, ZnSe기판표면의 에칭을 행하였다.Therefore, the concentration range of potassium dichromate is 0.1% by weight to saturation, and sulfuric acid concentration is H 2 SO 4 <60% by weight (Condition A), 60% ≤H 2 SO 4 ≤98% by Weight (Condition B), H 2 SO 4> by three types of 98% by weight (condition C), to adjust the etching solution, and was subjected to the etching surface of the ZnSe substrate.
두께 0.5㎛의 에칭을 행한 후의 기판표면의 상태를, 노멀스키미분간섭현미경에 의해 관찰하였다.The state of the board | substrate surface after the etching of 0.5 micrometer in thickness was observed with the normal skid minute microscope.
도 7∼도 11은, 관찰한 기판표면의 상태를 표시한 사진이다. 도 7 및 도 8은 조건A의 에칭액, 도 9는 조건 B의 에칭액, 도 10 및 도 11은 조건C의 에칭액을 사용한 경우의 결과를 표시하고 있다.7-11 is a photograph which shows the state of the observed substrate surface. 7 and 8 show the results of using the etching solution under condition A, FIG. 9 the etching solution under condition B, and FIGS. 10 and 11 using the etching solution under condition C. FIG.
먼저, 조건A의 에칭액을 사용했을 경우에는, 도 7에 표시한 바와 같이, 줄무늬와 같이 보이는 표면거칠음이 발생하고, 때로는 피트가 관찰되는 경우도 있었다. 또, 도 8에 표시한 바와 같이, 표면거칠음이 심하고, 미세한 요철때문에 광이 산란해서 경면에서는 없어져 버리는 경우도 있었다.First, when using the etching liquid of condition A, as shown in FIG. 7, surface roughness which looks like a stripe generate | occur | produced, and the pit was sometimes observed. In addition, as shown in FIG. 8, surface roughness was severe, and light scattered because of fine unevenness, and it might disappear in mirror surface.
한편, 조건B의 에칭액을 사용했을 경우에는, 도 9에 표시한 바와 같이, 작은백색의 점으로서 관찰되는 미소한 피트가 발생하는 경우가 있었으나, 경면이며, 바탕에 거칠음이 없고, 평활한 표면을 얻을 수 있었다.On the other hand, when the etching solution of the condition B was used, as shown in FIG. 9, the micro pits observed as small white spots may occur, but are mirror surfaces, have no roughness on the ground, and provide a smooth surface. Could get
또한, 기판표면의 가공변형층을 제거하는 공정을 에칭액으로 상기 가공변형층을 제거하는 공정과, 가공변형층이 제거된 상기 기판의 표면을 에칭액을 사용해서 에칭하는 공정에, 조건B의 에칭액을 사용하였던바, 경면으로, 바탕의 거칠음이 없고, 평활한 표면을 얻을 수 있었다.In addition, the etching solution of the condition B is used for the process of removing the processing strain layer from the surface of a substrate with an etching solution, and the process of etching the surface of the substrate from which the processing strain layer has been removed using an etching solution. As used, it was a mirror surface, and there was no roughness of a base, and the smooth surface was obtained.
또, 조건C의 에칭액을 사용했을 경우에는, 도 10에 표시한 바와 같이, 경면은 아니고, 표면에는 격심하게 Se가 석출하고, 백색의 조개껍데기모양의 것으로서 관찰되었다. 또, 도 11에 표시한 바와 같이, 경면이기는 하지만, 백색의 점으로서 관찰되는 미소한 피트가 다수 발생하고 있었다.In the case where the etching solution under the condition C was used, as shown in FIG. 10, Se precipitated vigorously on the surface instead of the mirror surface, and was observed as a white clam. Moreover, as shown in FIG. 11, although it was a mirror surface, many micro pits observed as a white point generate | occur | produced.
또한, 도 7∼도 11에 있어서, 검은 반점으로서 관찰되는 것은, 현미경의 오점때문이고, 기판의 결함과는 하등관계가 없는 것이다.7 to 11, black spots are observed due to microscopic stains, and have no relationship with defects in the substrate.
또, 상기 실시예에 있어서는, ZnSe기판을 예를 취하고 표시하였으나, 본원 발명은 ZnSe에 한정되지 않고, Ⅱ-Ⅵ족계화합물반도체기판에 널리 적용할 수 있다.In the above embodiment, the ZnSe substrate is taken as an example, and the present invention is not limited to ZnSe, but can be widely applied to II-VI compound semiconductor substrates.
또, 상기 실시예에 있어서는, ZnSe기판위에 에피택셜층을 형성하는 방법으로서, MBE법을 사용하는 경우에 대해서 설명하였으나, 이에 한정되는 것이 아니고, MOVPE법등 다른 방법을 사용했을 경우에도, 마찬가지의 효과를 얻을 수 있는 것은 자명하다.In the above embodiment, the case where the MBE method is used as the method of forming the epitaxial layer on the ZnSe substrate has been described. It is self-evident that can be obtained.
이상 설명한 바와 같이, 본원 발명에 의하면, 기판표면이 경면으로, 평활성, 청정성에 뛰어나고, 또한 에피택셜성장에 있어서는, 기판표면에 새로이 발생하는 결정결함수를 저감하는 데 적합한, Ⅱ-Ⅵ족계화합물반도체기판의 표면청정화처리를 행할 수 있다.As described above, according to the present invention, a II-VI compound semiconductor suitable for reducing the crystal defects newly generated on the substrate surface in terms of mirror surface, excellent smoothness and cleanliness, and epitaxial growth. The surface cleaning process of a board | substrate can be performed.
또, 본원 발명에 의하면, 경면으로, 평활성, 청정성에 뛰어난 기판표면을 얻을 수 있다. 이와 같이 해서 표면을 청정화처리한 기판위에, Ⅱ-Ⅵ족계 화합물반도체에피택셜층을 형성함으로써, 기판표면에서 새로이 발생하는 전위밀도가 104㎝-2를 하회하는, 저결함밀도의 Ⅱ-Ⅵ족계 화합물반도체박막을 형성할 수 있다.Moreover, according to this invention, the board | substrate surface excellent in the smoothness and the cleanness can be obtained in a mirror surface. Thus, by forming a II-VI compound semiconductor epitaxial layer on the substrate on which the surface has been cleaned, a low defect density II-VI group having a newly generated dislocation density of less than 10 4 cm -2 on the substrate surface. Compound semiconductor thin films can be formed.
그 결과, 본 발명에 의하면, 예를 들면 레이저다이오드나 발광다이오드 등의 발광디바이스의 수명특성의 향상을 위시하여, 모든 반도체디바이스의 특성향상을 도모할 수 있다.As a result, according to the present invention, the characteristics of all semiconductor devices can be improved, for example, in order to improve the life characteristics of light emitting devices such as laser diodes and light emitting diodes.
Claims (9)
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| JP10288902A JP2000100801A (en) | 1998-09-25 | 1998-09-25 | Epitaxial wafer, its manufacture and surface cleaning method for compound semiconductor substrate used therefor |
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| JP (1) | JP2000100801A (en) |
| KR (1) | KR20000023446A (en) |
| CN (1) | CN1249533A (en) |
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| US8316866B2 (en) | 2003-06-27 | 2012-11-27 | Lam Research Corporation | Method and apparatus for cleaning a semiconductor substrate |
| US7913703B1 (en) | 2003-06-27 | 2011-03-29 | Lam Research Corporation | Method and apparatus for uniformly applying a multi-phase cleaning solution to a substrate |
| US8522801B2 (en) | 2003-06-27 | 2013-09-03 | Lam Research Corporation | Method and apparatus for cleaning a semiconductor substrate |
| US7799141B2 (en) | 2003-06-27 | 2010-09-21 | Lam Research Corporation | Method and system for using a two-phases substrate cleaning compound |
| US7737097B2 (en) | 2003-06-27 | 2010-06-15 | Lam Research Corporation | Method for removing contamination from a substrate and for making a cleaning solution |
| US7648584B2 (en) | 2003-06-27 | 2010-01-19 | Lam Research Corporation | Method and apparatus for removing contamination from substrate |
| US8323420B2 (en) | 2005-06-30 | 2012-12-04 | Lam Research Corporation | Method for removing material from semiconductor wafer and apparatus for performing the same |
| US7862662B2 (en) | 2005-12-30 | 2011-01-04 | Lam Research Corporation | Method and material for cleaning a substrate |
| US8522799B2 (en) | 2005-12-30 | 2013-09-03 | Lam Research Corporation | Apparatus and system for cleaning a substrate |
| US8043441B2 (en) | 2005-06-15 | 2011-10-25 | Lam Research Corporation | Method and apparatus for cleaning a substrate using non-Newtonian fluids |
| CN100453701C (en) * | 2005-08-22 | 2009-01-21 | 昆明物理研究所 | Wet method pattern technology of chrome-nickel alloy thin film |
| SG154438A1 (en) | 2005-12-30 | 2009-08-28 | Lam Res Corp | Cleaning compound and method and system for using the cleaning compound |
| US7897213B2 (en) | 2007-02-08 | 2011-03-01 | Lam Research Corporation | Methods for contained chemical surface treatment |
| CN101398610B (en) * | 2008-10-23 | 2011-07-27 | 清溢精密光电（深圳）有限公司 | Treatment fluid for removing black defect in plate or film and treatment method |
| CN101510046B (en) * | 2008-10-23 | 2011-08-31 | 深圳清溢光电股份有限公司 | Treating liquid for removing fungus spot on plate or film and treating method |
| CN110552009A (en) * | 2019-08-07 | 2019-12-10 | 宜兴市科兴合金材料有限公司 | Method for cleaning molybdenum wafer for super-power direct-current power transmission and transformation module |
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| JPH0817163B2 (en) * | 1990-04-12 | 1996-02-21 | 株式会社東芝 | Epitaxial wafer manufacturing method |
| JP3658454B2 (en) * | 1996-03-29 | 2005-06-08 | コマツ電子金属株式会社 | Manufacturing method of semiconductor wafer |
| JP3344287B2 (en) * | 1996-08-30 | 2002-11-11 | 住友電気工業株式会社 | Method for cleaning surface of II-VI compound semiconductor crystal |
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