KR101868566B1 - Solar cell - Google Patents

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KR101868566B1
KR101868566B1 KR1020160146666A KR20160146666A KR101868566B1 KR 101868566 B1 KR101868566 B1 KR 101868566B1 KR 1020160146666 A KR1020160146666 A KR 1020160146666A KR 20160146666 A KR20160146666 A KR 20160146666A KR 101868566 B1 KR101868566 B1 KR 101868566B1
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region
type
type region
butting
electrode
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KR1020160146666A
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Korean (ko)
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KR20180050020A (en
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이기원
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엘지전자 주식회사
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/04—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices
    • H01L31/06—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices characterised by at least one potential-jump barrier or surface barrier
    • H01L31/072—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices characterised by at least one potential-jump barrier or surface barrier the potential barriers being only of the PN heterojunction type
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/02—Details
    • H01L31/0224—Electrodes
    • H01L31/022408—Electrodes for devices characterised by at least one potential jump barrier or surface barrier
    • H01L31/022425—Electrodes for devices characterised by at least one potential jump barrier or surface barrier for solar cells
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/02—Details
    • H01L31/0236—Special surface textures
    • H01L31/02366—Special surface textures of the substrate or of a layer on the substrate, e.g. textured ITO/glass substrate or superstrate, textured polymer layer on glass substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/0248—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by their semiconductor bodies
    • H01L31/0256—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by their semiconductor bodies characterised by the material
    • H01L31/0264—Inorganic materials
    • H01L31/032—Inorganic materials including, apart from doping materials or other impurities, only compounds not provided for in groups H01L31/0272 - H01L31/0312
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/0248—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by their semiconductor bodies
    • H01L31/036—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by their semiconductor bodies characterised by their crystalline structure or particular orientation of the crystalline planes
    • H01L31/0368—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by their semiconductor bodies characterised by their crystalline structure or particular orientation of the crystalline planes including polycrystalline semiconductors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/04—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02E—REDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
    • Y02E10/00—Energy generation through renewable energy sources
    • Y02E10/50—Photovoltaic [PV] energy
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02E—REDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
    • Y02E10/00—Energy generation through renewable energy sources
    • Y02E10/50—Photovoltaic [PV] energy
    • Y02E10/546—Polycrystalline silicon PV cells
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02E—REDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
    • Y02E10/00—Energy generation through renewable energy sources
    • Y02E10/50—Photovoltaic [PV] energy
    • Y02E10/547—Monocrystalline silicon PV cells

Abstract

A solar cell according to an embodiment of the present invention includes a semiconductor substrate, a semiconductor layer formed on the semiconductor substrate opposite to a surface on which light is received, a semiconductor layer formed on the semiconductor layer and including n-type impurities and p- type region and a p-type region, an intrinsic barrier region located between the n-type region and the p-type region and dividing the n-type region and the p-type region, and an n-type impurity or a p- And a butting region connecting the n-type region and the p-type region, wherein the butting region is formed only in a part of the barrier region.

Description

Solar cell {SOLAR CELL}

The present invention relates to a solar cell with improved efficiency.

With the recent depletion of existing energy sources such as oil and coal, interest in alternative energy to replace them is increasing. Among them, solar cells are attracting attention as a next-generation battery that converts solar energy into electric energy.

In such solar cells, various layers and electrodes can be fabricated by design. The solar cell efficiency can be determined by the design of these various layers and electrodes. In order to commercialize solar cells, it is required to overcome low efficiency, and various layers and electrodes are required to be designed and manufactured so as to maximize the efficiency of the solar cell.

On the other hand, when reverse bias is applied in the rear contact type solar cell having both the emitter and the rear electric field portion on the rear surface, the emitter and the back electric field portion are not separated from each other in a part of the region of the solar cell, The hot spot problem occurs.

SUMMARY OF THE INVENTION The present invention has been made to overcome the above problems, and it is an object of the present invention to solve the hot spot problem in which a current is concentrated in one place by forming a shunt path that can bypass a current when a reverse bias is applied to the solar cell.

A solar cell according to an embodiment of the present invention includes a semiconductor substrate, a semiconductor layer formed on the semiconductor substrate opposite to a surface on which light is received, a semiconductor layer formed on the semiconductor layer and including n-type impurities and p- type region and a p-type region, an intrinsic barrier region located between the n-type region and the p-type region and dividing the n-type region and the p-type region, and an n-type impurity or a p- And a butting region connecting the n-type region and the p-type region, wherein the butting region is formed only in a part of the barrier region.

The butting region includes only an n-type impurity, and the impurity concentration of the butting region is substantially equal to the impurity concentration of the n-type region.

The butting region includes only a p-type impurity, and the impurity concentration of the butting region is substantially equal to the impurity concentration of the p-type region.

The butting region includes both an n-type impurity and a p-type impurity, and the impurity concentration of the butting region is higher than the impurity concentration of the n-type region and the impurity concentration of the p-type region.

The n-type impurity concentration of the butting region is higher than the concentration of the p-type impurity in the vicinity of the n-type region, and the concentration of the p-type impurity adjacent to the p- high.

The area of the butting region with respect to the area of the semiconductor substrate is 10% or less.

The butting region is uniformly distributed over the semiconductor substrate.

A solar cell according to another embodiment of the present invention includes a semiconductor substrate, a semiconductor layer formed on the semiconductor substrate opposite to a surface on which light is received, a semiconductor layer formed on the semiconductor layer and including n-type impurities and p- An n-type region and a p-type region, an intrinsic barrier region located between the n-type region and the p-type region and dividing the n-type region and the p-type region, An electrode and a p-type electrode, and a butting electrode connecting the n-type region and the p-type region.

The butting electrode is formed of the same material in the same layer as the n-type electrode and the p-type electrode.

A portion of the butting electrode contacts the n-type region and the other portion contacts the p-type region.

The n-type region, the barrier region, and the p-type region are alternately arranged along the first direction, and are formed to be long in the second direction intersecting the first direction.

The n-type electrode and the p-type electrode are divided in a region where the butting electrode is located.

The solar cell is formed over the semiconductor layer and includes a first contact hole exposing the n-type region and a p-type region, a second contact hole exposing a part of the n-type region, the barrier region, And a passivation film.

The area of the butting electrode is 10% or less of the area of the semiconductor substrate.

The butting electrode is uniformly distributed over the semiconductor substrate.

A solar cell according to this embodiment forms a shunt path to a pn junction, induces a current to flow through the shunt path when a reverse bias is applied to the solar cell, and when the reverse bias is applied, Reduce hot spot problems that are happening.

1 shows a rear view of a solar cell according to a first embodiment of the present invention.
FIG. 2 shows a cross-sectional view taken along the line AA 'in FIG.
FIG. 3 shows a rear view of a solar cell according to a second embodiment of the present invention.
4 shows a cross-sectional view taken along the line B-B 'in Fig.
5 to 8 are enlarged views of the portion "I" in Fig. 4, illustrating the distribution of impurities in the butting region.

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings. However, it is needless to say that the present invention is not limited to these embodiments and can be modified into various forms.

In the drawings, the same reference numerals are used for the same or similar parts throughout the specification. In the drawings, the thickness, the width, and the like are enlarged or reduced in order to make the description more clear, and the thickness, width, etc. of the present invention are not limited to those shown in the drawings.

Wherever certain parts of the specification are referred to as "comprising ", the description does not exclude other parts and may include other parts, unless specifically stated otherwise. Also, when a portion of a layer, film, region, plate, or the like is referred to as being "on" another portion, it also includes the case where another portion is located in the middle as well as the other portion. When a portion of a layer, film, region, plate, or the like is referred to as being "directly on" another portion, it means that no other portion is located in the middle.

Hereinafter, a solar cell according to an embodiment of the present invention will be described in detail with reference to the drawings.

FIG. 1 partially shows a rear view of a solar cell according to a first embodiment of the present invention, and FIG. 2 shows a sectional view taken along line A-A 'of FIG.

1 and 2, the solar cell 100 according to the present embodiment has a rear contact type structure in which the n-type electrode 44 and the p-type electrode 42 are both located on the rear surface. Here, the rear surface means the opposite surface of the surface on which the solar cell receives light to generate electricity.

The photovoltaic cell of the first embodiment includes a semiconductor substrate 10, a semiconductor layer 30 formed on the opposite side of the light receiving surface of the semiconductor substrate 30, an n-type region 34 formed in the semiconductor layer, and a p- 32, a barrier region 32 located between the n-type region and the p-type region and separating the n-type region and the p-type region, an n-type electrode 44 A p-type electrode 42, and a butting electrode 46 connecting the n-type region and the p-type region.

The first passivation film 20 may be disposed between the semiconductor substrate 10 and the semiconductor layer 30 and may include a second passivation film 40 formed on the semiconductor layer 30. [

The solar cell 100 may further include a front passivation film 24 and an antireflection film 26 located on the front surface of the semiconductor substrate 10. This will be explained in more detail.

The semiconductor substrate 10 can be preferably used with a crystalline semiconductor (for example, a single crystal or a polycrystalline semiconductor, such as monocrystalline or polycrystalline silicon, particularly monocrystalline silicon) containing n-type impurities in a preferred form have.

When the semiconductor substrate 10 has an n-type, the p-type region 32 forming the pn junction can be formed to be wider and the photoelectric conversion area can be increased. In this case, the p-type region 32 having a large area can effectively collect holes having a relatively low moving speed, thereby contributing to the improvement of photoelectric conversion efficiency. However, the present invention is not limited thereto, and it is also possible that the semiconductor substrate 10 includes a p-type impurity or a polycrystalline silicon semiconductor or amorphous silicon.

An antireflection structure capable of minimizing reflection can be formed on the front surface of the semiconductor substrate 10. [ For example, a texturing structure having a concavo-convex shape in the form of a pyramid or the like may be provided as an antireflection structure. The texturing structure formed on the semiconductor substrate 10 may have a certain shape (e.g., a pyramid shape) having an outer surface formed along a specific crystal plane (e.g., (111) plane) of the semiconductor. When the surface roughness of the semiconductor substrate 10 is increased by the irregularities formed on the front surface of the semiconductor substrate 10 by such texturing, the reflectance of light incident through the front surface of the semiconductor substrate 10 can be reduced to minimize the optical loss.

The rear surface of the semiconductor substrate 10 is made of a relatively smooth and flat surface having a surface roughness lower than that of the front surface by mirror polishing or the like. When the n-type region 34 and the p-type region 32 are formed on the semiconductor layer 10 at the back side of the semiconductor substrate 10 as in the present embodiment, It is preferable that it is a flat surface.

As a result, unevenness due to texturing is not formed on the rear surface of the semiconductor substrate 10, so that passivation characteristics can be improved and the characteristics of the solar cell 100 can be improved. However, the irregularities due to texturing may be formed on the rear surface of the semiconductor substrate 10 as the case may be. Various other variations are possible.

A first rear passivation film 20 is formed on the rear surface of the semiconductor substrate 10. For example, the first passivation film 20 may be formed entirely in contact with the rear surface of the semiconductor substrate 10. Then, the first rear passivation film 20 can be easily formed without patterning.

This first rear passivation film 20 may be an oxide film, and in particular, it may be a silicon oxide film containing silicon oxide. The silicon oxide film has excellent passivation characteristics and is effective for carrier transfer.

A crystalline semiconductor layer 30 is located on the first passivation film 20. For example, the semiconductor layer 30 may be formed in contact with the first rear passivation film 20 to simplify the structure and allow the carrier to be easily transferred.

In this embodiment, the semiconductor layer 30 includes a p-type region 32 having a p-type impurity and serving as an emitter, and an n-type region 34 having n-type impurities and serving as a BSF. The n-type region 34 and the p-type region 32 may be formed by thermally diffusing an impurity into the semiconductor layer 30 or by forming a doping layer containing an impurity on the semiconductor layer 30, So that impurities can be diffused into the semiconductor layer 30 by laser.

Thus, the n-type region 34 and the p-type region 32 can be composed of the same layer, that is, a part of the semiconductor layer 30. [ A barrier region 36 is further formed between the n-type region 34 and the p-type region 32 to prevent them from being butted. Unlike the n-type region 34 and the p-type region 32, the barrier region 34 is an intrinsic semiconductor layer which contains no impurity.

This barrier region 36 is located between the n-type region 34 and the p-type region 32 and prevents them from buiding so that the recombination sites 34, the recombination site can be reduced and the efficiency can be improved.

The p-type region 32 is formed by forming a pn junction (or a pn tunnel junction) with a first passivation film 20 having a thin thickness (about 1 nm or less) through which the carrier can pass, And an emitter region is formed. The n-type region 34 forms a back surface field to constitute a rear electric field region for preventing carriers from being lost due to recombination at the rear surface of the semiconductor substrate 10.

The p-type region 32 includes a conductive impurity opposite to the semiconductor substrate 10. The n-type region 34 includes the same conductivity type impurity as the semiconductor substrate 10, and the doping concentration is higher than that of the semiconductor substrate 10.

In this embodiment, the p-type region 32 and the n-type region 34 are formed on the semiconductor substrate 10 and in a layer different from the semiconductor substrate 10. Accordingly, the p-type region 32 and the n-type region 34 can be formed of a semiconductor layer (for example, an amorphous silicon layer or a polycrystalline silicon layer) having a different crystal structure on the semiconductor substrate 10, The high efficiency can be obtained.

If the p-type region 32 and the n-type region 34 are made of a polycrystalline silicon layer, high carrier mobility can be obtained. the impurities contained in the p-type region 32 and the n-type region 34 may be included together in the semiconductor layer 30 in the step of forming the semiconductor layer 30, May be included in the semiconductor layer 30 by various doping methods such as a diffusion method and an ion implantation method.

At this time, as the impurity for forming the conductive type region, various materials capable of exhibiting n type or p type can be used. When the impurity is p-type, materials such as boron (B), aluminum (Al), gallium (Ga), and indium (In) are used. In the case of n-type, materials such as phosphorus (P), arsenic (As), bismuth (Bi) and antimony (Sb) are used.

A barrier region 36 is located between the p-type region 32 and the n-type region 34 to separate the p-type region 32 and the n-type region 34 from each other. When the p-type region 32 and the n-type region 34 are in contact with each other, a shunt is generated and the performance of the solar cell 100 may be deteriorated. Accordingly, in this embodiment, unnecessary shunt can be prevented by positioning the barrier region 36 between the p-type region 32 and the n-type region 34. [

Preferably, the barrier region 36 is an intrinsic semiconductor layer free of impurities. The p-type region 32 and the n-type region 34 and the barrier region 36 are made of the same semiconductor (for example, amorphous silicon, microcrystalline silicon, polycrystalline silicon) continuously formed while being in side contact with each other, Region 36 is an i-type (intrinsic) semiconductor that does not substantially contain a dopant.

For example, after a semiconductor layer including a semiconductor material is formed, a p-type region 32 is formed by doping a part of the semiconductor layer with a p-type impurity, and a predetermined distance from the p- -Type impurity is doped to form the n-type region 34, a barrier region 36 is also formed between the p-type region 32 and the n-type region 34 to prevent them from buiding.

However, the present invention is not limited thereto. For example, the barrier region 36 may be formed of a trench, which is an empty space, or may be formed of an insulating material (e.g., oxide or nitride) 32 and the n-type region 34 can be used.

A second passivation film 40 may be formed on the semiconductor layer 30. This second rear passivation film 40 is formed so as to completely cover the semiconductor layer 30 and has the effect of passivating the surface of the semiconductor layer made of silicon.

 This second rear passivation film 40 has a first contact hole 46 for electrical connection between the p-type and n-type regions 32 and 34 and the electrodes 42 and 44. The first contact holes 46 open portions of the p-type and n-type regions 32 and 34 so that the electrodes 42 and 44 filling the contact holes 46 are electrically connected to the p- and n-type regions 32 and 34 Respectively. Therefore, the p-type electrode 42 is connected only to the p-type region 32 to collect holes, and the n-type electrode 44 is connected only to the n-type region 34 to collect electrons.

 In addition, the second rear passivation film 40 further includes a second contact hole 48a. The second contact hole 48a simultaneously opens the p-type region 32, the n-type region 34 and the barrier region 36 so that the butting electrode 46 contacts the p-type region 32 and the n- 34 so that the p-type region 32 and the n-type region 34 can be butted.

On the other hand, the p-type region 32 and the n-type region 34 are alternately arranged in a direction intersecting the longitudinal direction while being elongated so as to form a stripe shape. The barrier region 36 is located between the p-type region 32 and the n-type region 34 to prevent the p-type region 32 and the n-type region 34 from butting, Thereby enhancing the power generation efficiency.

At this time, the area of the p-type region 32 may be larger than the area of the n-type region 34. In one example, the areas of the p-type region 32 and the n-type region 34 can be adjusted by varying their widths. That is, the width W1 of the p-type region 32 may be larger than the width W2 of the n-type region 34. [ The carriers produced in the p-type region 32 are holes and the carriers produced in the n-type region 32 are electrons. The life time of holes is shorter than that of electrons, and the migration speed is also slow. By making the width W1 of the p-type region 32 larger than the width W2 of the n-type region 34 as described above, it is possible to reduce the loss of carriers produced in the p-type region 32, .

The p-type electrode 42 is formed in a stripe shape corresponding to the p-type region 32 and the n-type electrode 44 is formed in a stripe shape corresponding to the n-type region 34. It is preferable that the p-type electrode 42 and the n-type electrode 44 are separated from each other so as not to be electrically connected to the butting electrode 48 where the butting electrode 48 is formed. In a preferred form, The electrode 42 and the n-type electrode 44 are disconnected where the butting electrode 48 is formed.

In one embodiment, the p-type electrode 42 and the n-type electrode 44 are elongated in one direction (x-axis direction in the drawing), and only the butting electrode 46 and the n- It is disconnected not to be contacted. As a result, the p-type electrode 42 and the n-type electrode 44 are physically separated from the butting electrode 28.

On the other hand, the butting electrode 48 is in contact with the p-type region 32 and the n-type region 34 through the second contact hole 48a. Thus, the p-type region 32 and the n-type region 34 are shunted by the butting electrode 48.

The second contact hole 48a is formed in the p-type region 32 and the n-type region 34 and the barrier region 36 existing therebetween at the position where the p-type electrode 42 and the n-type electrode 44 are cut off, Lt; / RTI > Since the butting electrode 48 is formed filling the second contact hole 48a, the butting electrode 48 makes a junction between a part of the p-type region 32 and a part of the n-type region 34. [

Thus, when a reverse bias is applied to the solar cell, the reverse bias causes a current to flow into the shunt, whereby electrons are collected by the butting electrode 48. Since the butting electrode 48 functions as a recombination site, electrons collected at the butting electrode 48 are lost there, and the intensity of the current flowing through the solar cell can be reduced by reverse bias.

If a reverse bias is applied in the conventional rear-contact solar cell having both the emitter and the rear electric field portion on the rear surface, the current should not flow because the solar cell is a diode. However, in some areas of the solar cell, The hot spot problem occurs because current and current flow to the backplane and backplane due to various factors (for example, technical problems and purpose of bypassing).

On the other hand, in this embodiment, since the shunt path is formed by the butting electrode 48, when the reverse bias is applied, the current which is concentrated in one direction is dispersed to the reverse bias, Hot spot problems can be reduced.

The butting electrode 48 may be made of the same material as the n-type electrode 44 or the p-type electrode 42 on the same layer. The n-type electrode 44 or the p-type electrode 42 is formed in the second rear passivation film 40 by forming the contact holes 48 and 48a by the patterning process, The n-type electrode 44, the p-type electrode 46, and the butting electrode 48 may be formed by various known methods such as sputtering, plating, vapor deposition, screen printing or the like.

In a preferred form, the size or shape of the butting electrode 48 may be varied according to the shape to be implemented, without any particular limitation, and the position where the butting electrode 48 is formed in a preferred form, It is preferable that the semiconductor substrate 20 is uniformly formed on the entire surface of the semiconductor substrate 20.

The area of the butting electrode 48 is preferably 10% or less of the area of the semiconductor substrate 20. If the area exceeds 10%, the area where the carrier is not collected due to the shunt path made by the butting electrode 48 becomes too large, and the power generation efficiency can be remarkably reduced.

In this embodiment, since the p-type region 32 and the n-type region 34 are partially bonded in this manner, the region where a dead layer (region not used for electric power generation) is generated is reduced to a minimum, When the reverse bias is applied without reducing the current, the reverse bias current is dispersed to solve the hot spot problem caused by the current concentration.

The front passivation film 24 and / or the antireflection film 26 may be positioned on the front surface of the semiconductor substrate 10. However, the present invention is not limited thereto. The semiconductor substrate 10 and the front passivation film 24 may further include a front electric field area including an impurity having the same conductivity type as the semiconductor substrate 10.

The front passivation film 24 and the antireflection film 26 may be formed entirely on the entire surface of the semiconductor substrate 10. [

The front passivation film 24 or the rear passivation films 20 and 40 may be formed in contact with the semiconductor substrate 10 or the semiconductor layer 30 and may be formed on the entire surface or in the bulk of the semiconductor substrate 10 or the semiconductor layer 30 Passivates defects. Thus, the recombination site of the minority carriers is removed to increase the open-circuit voltage of the solar cell 100. The antireflection film 26 may reduce the reflectivity of light incident on the front surface of the semiconductor substrate 10, thereby increasing the amount of light reaching the pn junction. Thereby increasing the short circuit current Isc of the solar cell 100. [

The front passivation film 24 and the antireflection film 26 may be formed of various materials. For example, the front passivation film 24 and the antireflection film 26 may be formed of a silicon nitride film, a silicon nitride film containing hydrogen, a silicon oxide film, a silicon oxynitride film, an aluminum oxide film, a silicon carbide film, MgF 2 , ZnS, TiO 2, and CeO 2 Or a multilayer structure in which two or more membranes are combined.

Hereinafter, a second embodiment of the present invention will be described. In comparison with the first embodiment described above, the same reference numerals are used for the same components, and a detailed description thereof will be omitted. FIG. 3 shows a rear view of a solar cell according to a second embodiment of the present invention. FIG. 4 shows a sectional view taken along the line B-B 'in FIG. 1, In which the impurity distribution in the butting region is exemplified.

 Comparing this second embodiment with the first embodiment, there is a difference only in the manner in which the p-type region 32 and the n-type region 34 are butted. If the first embodiment forms a shunt path in the p-type region 32 and the n-type region 34 via the butting electrode 48, the shunt path is formed through the barrier region including the impurity in the second embodiment.

In this embodiment, the semiconductor layer 30 includes a p-type region 32 having a p-type impurity and serving as an emitter, an n-type region 34 having an n-type impurity and serving as a BSF, A p-type electrode 42 is formed in a stripe shape corresponding to the p-type region 32 and an n-type electrode 44 is formed in correspondence with the n-type region 34 So that they are formed in a stripe shape.

However, the difference between the n-type region 34 and the p-type region 32 is formed by the butting region 361 formed in the barrier region 36.

In this embodiment, the butting region 361 is formed with the barrier region 36, and may include an n-type impurity or a p-type impurity or an n-type impurity and a p-type impurity.

The n-type region 34 and the p-type region 32, which are formed by doping a part of the semiconductor layer 30 with impurities, can be formed by various doping methods such as a thermal diffusion method and an ion implantation method.

For example, if the n-type region 34 and the p-type region 32 are formed by thermal diffusion, a part of the barrier region 36 is exposed and a barrier in which the n-type region is completely covered is formed on the semiconductor layer 40 When the p-type impurity is thermally diffused to the semiconductor layer 40, the p-type impurity is doped not only in the p-type region 32 but also in the barrier region 36 to form the butting region 361.

The burring region 361 and the p-type region 32 are protected by a barrier and the n-type impurity is thermally diffused into the semiconductor layer 40 while the semiconductor layer in which the n-type region is to be formed is opened, Regions 32 are formed.

Thereby, the n-type region 34 and the p-type region 32 and the barrier region 36 in which the impurity is not doped are formed, and the n-type region 34 and the p- The burring region 361 is made of the semiconductor layer 30.

When the barrier region 36 of one line is viewed, the butting region 361 is formed only for a part of the barrier region 36. [ If the butting region 361 is formed in one line as a whole, recombination sites due to butting are increased, and the power generation efficiency of the solar cell is reduced. In consideration of this point, it is preferable that the butting region 361 is uniformly distributed over the entire solar cell, and it is ideal that the butting region 361 is 10% or less of the area of the semiconductor substrate.

On the other hand, the impurity concentration included in the butting region 361 is substantially equal to the impurity concentration included in the p-type region 32 made in the same process.

FIG. 5 illustrates a case where a butting region is formed by doping a part of the butting region 361 with a p-type impurity. FIG. 6 illustrates a case where a butting region is formed by doping an n-type impurity.

7 illustrates a case where a butting region is formed by doping an n-type impurity and a p-type impurity into a part of the barrier region, respectively.

The butting region 361 illustrated in FIG. 7 is formed by exposing a part of the barrier region 36 in the process of forming the n-type region 34 and the p-type region 32, respectively, and doping the n-type impurity and the p- .

Since the majority of the n-type impurity is adjacent to the n-type region 34 in the butting region 361, the concentration of the n-type impurity is higher than that of the p-type impurity, Type impurity is higher than the concentration of the n-type impurity because a majority of the p-type impurities are distributed.

8 illustrates a case where the burring region 361 is formed by doping the barrier region with an n-type impurity and a p-type impurity, respectively.

8, the n-type impurity and the p-type impurity are doped twice by exposing the barrier region 36 which is a butting region in the process of forming the n-type region 34 and the p-type region 32, respectively . According to this, the butting region 361 is doped higher than the impurity concentration of the n-type region 34 and the p-type region 32.

In the above description, it is explained that the butting region 361 is formed by a heat diffusion method by heat treatment in the state of using a gas containing an impurity, but the present invention is not limited thereto. The butting region 361 may be formed by various methods such as a laser doping method or an ion implantation method in which a doping layer is formed and then a laser is irradiated and diffused.

Claims (18)

A semiconductor substrate;
A semiconductor layer formed on a surface of the semiconductor substrate opposite to a surface on which light is received;
An n-type region and a p-type region which are formed in the semiconductor layer and each include an n-type impurity and a p-type impurity;
An intrinsic barrier region located between the n-type region and the p-type region and dividing the n-type region and the p-type region; And
A butting region formed in the barrier region and including at least one of the n-type impurity and the p-type impurity to connect the n-type region and the p-type region;
/ RTI >
Wherein the butting region is formed only in a part of the barrier region,
Wherein the butting region includes only an n-type impurity, only a p-type impurity, or both an n-type impurity and a p-type impurity. delete The method according to claim 1,
Wherein the impurity concentration of the butting region is equal to the impurity concentration of the n-type region. delete The method according to claim 1,
And the impurity concentration of the butting region is equal to the impurity concentration of the p-type region. delete The method according to claim 1,
Wherein the impurity concentration of the butting region is higher than the impurity concentration of the n-type region and the impurity concentration of the p-type region. The method according to claim 1,
The n-type impurity concentration of the butting region is higher than the concentration of the p-type impurity in the vicinity of the n-type region, and the concentration of the p-type impurity adjacent to the p- High solar cells. The method according to claim 1,
Wherein an area of the butting region with respect to an area of the semiconductor substrate is 10% or less. 10. The method of claim 9,
Wherein the butting region is uniformly distributed over the semiconductor substrate. A semiconductor substrate;
A semiconductor layer formed on a surface of the semiconductor substrate opposite to a surface on which light is received;
An n-type region and a p-type region which are formed in the semiconductor layer and each include an n-type impurity and a p-type impurity;
An intrinsic barrier region located between the n-type region and the p-type region and dividing the n-type region and the p-type region;
An n-type electrode and a p-type electrode connected to the n-type region and the p-type region, respectively; And
A butting electrode connecting the n-type region and the p-type region;
/ RTI >
And a second contact hole formed on the semiconductor layer, the second contact hole exposing a portion of the n-type region, a portion of the barrier region, and the p-type region simultaneously, the first contact hole exposing the n-type region and the p- A solar cell further comprising a membrane. 12. The method of claim 11,
Wherein the butting electrode is formed of the same material as the n-type electrode and the p-type electrode. 12. The method of claim 11,
Wherein a portion of the butting electrode is in contact with the n-type region and the other portion is in contact with the p-type region. 12. The method of claim 11,
Wherein the n-type region, the barrier region, and the p-type region are alternately arranged along a first direction, and are arranged in parallel in a second direction intersecting the first direction. 15. The method of claim 14,
Wherein the n-type electrode and the p-type electrode are divided in a region where the butting electrode is located, respectively. delete 12. The method of claim 11,
Wherein an area of the butting electrode is 10% or less of an area of the semiconductor substrate. 14. The method of claim 13,
Wherein the butting electrode is uniformly distributed over the semiconductor substrate.
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