KR101455478B1 - 반도체 디바이스의 접촉 구조 - Google Patents

반도체 디바이스의 접촉 구조 Download PDF

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KR101455478B1
KR101455478B1 KR1020120155062A KR20120155062A KR101455478B1 KR 101455478 B1 KR101455478 B1 KR 101455478B1 KR 1020120155062 A KR1020120155062 A KR 1020120155062A KR 20120155062 A KR20120155062 A KR 20120155062A KR 101455478 B1 KR101455478 B1 KR 101455478B1
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layer
metal layer
dielectric layer
semiconductor device
substrate
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KR20140041306A (ko
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승리 왕
딩캉 시
친샹 린
세이핑 선
크레먼트 싱젠 완
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타이완 세미콘덕터 매뉴팩쳐링 컴퍼니 리미티드
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Abstract

본 발명은 반도체 디바이스의 접촉 구조에 관한 것이다. 반도체 디바이스를 위한 접촉 구조에 대한 예시적인 구조는 주면 및 상기 주면 아래의 트렌치를 포함하는 기판; 상기 트렌치를 충진하는 변형 물질로서, 상기 변형 물질의 격자 상수는 상기 기판의 격자 상수와 상이한 것인, 상기 변형 물질; 상기 변형 물질 위의 개구부를 갖는 층간 유전체(ILD)층으로서, 상기 개구부는 절연체 측벽 및 변형 물질 저부를 포함하는 것인, 층간 유전체층; 상기 개구부의 측벽 및 저부를 코팅하고, 1 nm 내지 10 nm의 범위 내의 두께를 갖는 유전체층; 및 상기 유전체층의 코팅된 개구부를 충진하는 금속층를 포함한다.

Description

반도체 디바이스의 접촉 구조{CONTACT STRUCTURE OF SEMICONDUCTOR DEVICE}
관련 출원
본 출원은 이하의 동시계류중인(co-pending) 일반적으로 할당된 그 명칭이 Contact Structure of Semiconductor Device,”(Atty Docket No. TSM12-0787)인 특허 출원에 관한 것이고, 상기 출원은 참조에 의해 여기에 통합된다
기술분야
본 발명은 집적 회로 제조에 관한 것이고, 보다 구체적으로 접촉 구조를 갖는 반도체 디바이스에 관한 것이다.
반도체 산업이 더 높은 디바이스 밀도, 더 높은 성능, 및 더 낮은 비용을 위해서 나노미터 기술 공정 노드로 진행함에 따라 핀 전계 효과 트랜지스터(fin field effect transistor; FinFET) 등의 반도체 디바이스의 3차원 설계의 개발에서 제조 및 설계 모두로부터의 도전 과제가 발생되었다. 전형적인 FinFET은 예를 들어 기판의 실리콘층의 일부를 에칭함으로써 형성된 기판으로부터 연장하는 얇은 수직 "핀(fin)"(또는 핀 구조)와 함께 제조된다. FinFET의 채널은 이러한 수직 핀 내에 형성된다. 게이트는 핀의 3개의 측면(예를 들면, 래핑) 위에 제공된다. 채널의 양측 상에 게이트를 갖는 것은 양측으로부터 채널의 게이트 제어를 허용한다. FinFET의 추가의 이점은 짧은 채널 효과 및 더 높은 전류 흐름의 감소를 포함한다.
그러나, 상보성 금속 산화물 반도체(complementary metal-oxide-semiconductor; CMOS) 제조에서는 그러한 피쳐 및 공정을 구현하기 위한 도전 과제가 있다. 예를 들면, 변형 물질(strained material) 상의 실리사이드 형성은 FinFET의 영역의 소스/드레인의 높은 접촉 저항을 발생시킴으로써 디바이스의 성능을 저하시킨다.
실시예에 따르면, 반도체 디바이스 접촉 구조는 주면(major surface) 및 상기 주면 아래의 트렌치를 포함하는 기판; 상기 트렌치를 충진하는 변형 물질(strained material)로서, 상기 변형 물질의 격자 상수는 상기 기판의 격자 상수와 상이한 것인, 상기 변형 물질; 상기 변형 물질 위의 개구부를 갖는 층간 유전체(inter-layer dielectric; ILD)층으로서, 상기 개구부는 절연체 측벽 및 변형 물질 저부(bottom)를 포함하는 것인, 층간 유전체층; 상기 개구부의 측벽 및 저부를 코팅하고, 1 nm 내지 10 nm의 범위 내의 두께를 갖는 유전체층; 및 상기 유전체층의 코팅된 개구부를 충진하는 금속층을 포함한다.
또 다른 실시예에 따르면, 금속 산화물 반도체 전계 효과 트랜지스터(metal oxide semiconductor field effect transistor; MOSFET)는 주면을 포함하는 기판; 상기 기판의 상기 주면 상의 게이트 스택; 상기 게이트 스택에 인접한 상기 주면 아래의 트렌치; 상기 게이트 스택에 대향하는 트렌치의 측면에 배치되고, 상기 기판 내에 있는 얇은 트렌치 절연 영역(shallow trench isolation; STI); 및 접촉 구조를 포함하고, 상기 접촉 구조는 상기 트렌치를 충진하는 변형 물질로서, 상기 변형 물질의 격자 상수는 상기 기판의 격자 상수와 상이한 것인, 상기 변형 물질; 상기 변형 물질 위의 개구부를 갖는 층간 유전체(inter-layer dielectric; ILD)층으로서, 상기 개구부는 절연체 측벽 및 변형 물질 저부를 포함하는 것인, 층간 유전체층; 상기 개구부의 측벽 및 저부를 코팅하고, 1 nm 내지 10 nm의 범위 내의 두께를 갖는 유전체층; 및 상기 유전체층의 코팅된 개구부를 충진하는 금속층을 포함한다.
또 다른 실시예에 따르면, 반도체 디바이스를 제조하는 방법은 주면 및 상기 주면 아래의 트렌치를 포함한 기판을 제공하는 단계; 상기 트렌치 내에 변형 물질(strained material)을 에피-성장시키는 단계로서, 상기 변형 물질의 격자 상수는 상기 기판의 격자 상수와 상이한 것인, 상기 에피-성장시키는 단계; 상기 변형 물질 위에 층간 유전체(inter-layer dielectric; ILD)층을 형성하는 단계; 상기 변형 물질의 일부를 노출하도록 상기 ILD층 내에 개구부를 형성하는 단계; 상기 개구부의 내부를 코팅하고 상기 ILD층 위로 연장하는 제 1 금속층을 형성하는 단계; 상기 변형 물질 위에 유전체층을 형성하도록 상기 제 1 금속층을 처리하는(treating) 단계; 및 상기 유전체층의 코팅된 개구부 내에 제 2 금속층을 형성하는 단계를 포함한다.
본 개시는 첨부 도면과 함께 판독될 때 다음의 상세한 설명으로부터 가장 잘 이해된다. 산업상 표준 시행에 따라 여러 도면은 일정한 비율로 그려지지 않았으며, 단지 예시의 목적으로만 사용됨이 강조된다. 실제, 다양한 특징의 치수는 논의의 명료함을 위해 임의로 증감될 수 있다.
도 1은 본 개시의 다양한 양상에 따른 반도체 디바이스의 접촉 구조 제조 방법을 예시하는 흐름도이다;
도 2 내지 도 12는 본 개시의 각종 양상에 따라 제작의 각종 단계에서 접촉 구조를 구성하는 반도체 장치의 개략적이 단면도이다.
이하의 개시는 본 개시의 상이한 피쳐들을 구현하기 위한 다수의 상이한 실시예 또는 예를 제공한다고 이해된다. 본 개시를 단순화하기 위해서 컴포넌트 및 배치의 구체적인 예들이 이하에 설명된다. 물론, 이들은 단지 예시를 위한 것이며 한정을 의도하는 것은 아니다. 예를 들면, 다음의 설명에서 제 2 피쳐 상부 또는 위에 제 1 피쳐를 형성하는 것은 제 1 피쳐와 제 2 피쳐가 직접 접촉하여 형성된 실시예를 포함할 수 있고, 또한 제 1 피쳐와 제 2 피쳐가 직접 접촉하지 않도록 제 1 피쳐와 제 2 피쳐 사이에 추가의 피쳐가 형성될 수 있는 실시예도 포함할 수 있다. 추가로, 본 개시는 다양한 예들에서 참조 번호 및/또는 문자를 반복할 수 있다. 이러한 반복은 단순 명료함을 위한 것으로서 그 자체가 논의된 다양한 실시예 및/또는 구성 사이의 관계를 영향을 주지 않는다.
도 1를 참조하면, 본 개시의 다양한 양상에 따른 반도체 디바이스의 접촉 구조를 제조하는 방법(100)의 흐름도를 예시한다. 방법(100)은 주면(major surface), 및 주면 아래의 트렌치를 포함하는 기판이 제공되는 단계(102)로 시작한다. 방법(100)은 변형 물질이 트렌치에서 에피(epi)-성장되는 단계(104)로 계속되고, 변형 물질의 격자 상수는 기판의 격자 상수와 상이하다. 방법(100)은 층간 유전체(inter-layer dielectric; ILD)층이 변형 물질 위에 형성되는 단계(106)로 계속한다. 방법(100)은 변형 물질의 일부를 노출하도록 ILD층 내에 개구부가 형성되는 단계(108)로 계속한다. 방법(100)은 제 1 금속층이 개구부의 내부를 코팅하고 ILD층 위로 연장되는 단계 110로 계속한다. 방법(100)은 제 1 금속층이 개구부의 내부를 코팅하고 ILD층 위로 연장되도록 형성되는 단계(110)로 계속한다. 방법(100)은 제 1 금속층이 변형 물질 위에 유전체층을 형성하도록 처리되는 단계(112)로 계속한다. 방법(100)은 제 2 금속층이 유전체층의 코팅된 개구부 내에 형성되는 단계(114)로 계속한다. 이하의 논의는 도 1의 방법(100)에 따라 제조될 수 있는 반도체 디바이스의 실시예를 예시한다.
도 2 내지 도 12는 본 개시의 다양한 양상에 따른 제작의 각종 단계에서 접촉 구조(230)를 포함한 반도체 장치(200)의 개략적인 단면도이다. 본 개시에서 채용된 바와 같은, 반도체 디바이스(200)란 용어는 핀 전계 효과 트랜지스터(FinFET)를 말한다. FinFET은 어떤 핀 기반의 다중 게이트 트랜지스터를 말한다. 일부 대안의 실시형태에서 반도체 디바이스(200)란 용어는 평면 금속 산화물 반도체 전계 효과 트랜지스터(metal-oxide-semiconductor field effect transistor; MOSFET)를 말한다. 다른 트랜지스터 구조 및 유사 구조는 본 개시의 고려 범위 내에 있다. 반도체 디바이스(200)는 마이크로프로세서, 메모리 셀, 및/또는 다른 집적 회로(integrated circuit; IC) 내에 포함될 수 있다.
일부 실시예에 있어서, 도 1에서 언급된 동작의 수행은 완전한 반도체 디바이스(200)를 생산하지 않는다는 것이 주목된다. 완전한 반도체 디바이스(200)는 예를 들어 상보성 금속-산화물-반도체(CMOS) 기술 프로세싱을 이용하여 제조될 수 있다. 따라서, 도 1의 방법(100)의 이전, 동안, 및/또는 이후에 추가의 공정이 제공될 수 있고, 일부 다른 공정은 여기서 간략히만 설명될 수 있다는 것이 이해된다. 또한, 도 2 내지 도 12는 본 개시의 개념을 더 잘 이해하기 위해서 간략화되었다. 예를 들어, 도면은 반도체 디바이스(200)를 예시하지만, IC는 저항기, 캐패시터, 인덕터, 퓨즈 등을 포함한 다수의 다른 디바이스를 포함할 수 있다는 것이 이해된다.
도 2와 도 1에서 단계(102)를 참조하면, 주면(20s)을 포함하는 기판(20)이 제공된다. 적어도 하나의 실시예에 있어서, 기판(20)은 결정질 실리콘 기판(예를 들어 웨이퍼)을 포함한다. 기판(20)은 설계 요건에 따라 다양하게 도핑된 영역(예를 들어, p형 기판 또는 n형 기판)을 포함할 수 있다. 일부 실시예에 있어서, 도핑된 영역은 p형 또는 n형 도판트로 도핑될 수 있다. 예를 들어, 도핑된 영역은 붕소 또는 BF2와 같은 p형 도판트; 인 또는 비소와 같은 n형 도판트; 및/또는 그 조합으로 도핑될 수 있다. 도핑된 영역은 n형 FinFET 또는 평면 MOSFET을 위해 형성되거나, 대안적으로 p형 FinFET 또는 평면 MOSFET을 위해 구성될 수 있다.
대안적으로, 기판(20)은 다이아몬드 또는 게르마늄과 같은 어떤 다른 적합한 원소의 반도체; 갈륨 비소화물, 실리콘 카바이드, 인듐 비소화물, 또는 인듐 인화물과 같은 적합한 합성 반도체; 또는 실리콘 게르마늄 카바이드, 갈륨 비소 인화물, 또는 갈륨 인듐 인화물과 같은 적합한 합금 반도체로 이루어질 수 있다. 또한, 기판(20)은 에피택셜층(에피층)을 포함할 수 있고, 성능 향상을 위해 변형될 수 있으며, 및/또는 실리콘-온-인슐레이터(silicon-on-insulator; SOI) 구조를 포함할 수 있다.
설명된 실시예에 있어서, 기판(20)은 핀 구조(202)에 더 포함한다. 기판(20)에 형성된 핀 구조(202)는 하나 이상의 핀을 포함한다. 본 실시예에서는 간단함을 위해 핀 구조(202)는 단일 핀을 포함한다. 핀은 어떤 적합한 물질을 포함하고, 예를 들어 핀은 실리콘, 게르마늄 또는 합성 반도체를 포함할 수 있다. 핀 구조(202)는 핀에 배치된 캡핑층(도시되지 않음)을 더 형성할 수 있고, 실리콘 캡핑층일 수 있다.
핀 구조(202)는 다양한 증착, 포토리소그라피 및/또는 에칭 공정을 포함한 어떤 적합한 공정을 이용하여 형성된다. 예시적인 포토리소그라피 공정은 기판(20) 위에 놓인(예를 들면, 실리콘층 상의) 포토레지스트층(레지스트)을 형성하는 것, 패턴에 레지스트를 노출하는 것, 노광후 베이크(post-exposure bake) 공정을 수행하는 것, 및 레지스트를 포함한 마스킹 엘리먼트를 형성하기 위해 레지스트를 개발하는 것을 포함할 수 있다. 그 다음에, 실리콘층은 반응성 이온 에칭(reactive ion etch; RIE) 공정 및/또는 다른 적합한 공정을 사용하여 에칭될 수 있다. 예를 들어 핀 구조(202)의 실리콘 핀은 실리콘 기판(20)의 부분의 패터닝 및 에칭을 이용하여 형성될 수 있다. 또 다른 실시예에 있어서, 핀 구조(202)의 실리콘 핀은 절연층(예를 들어, SOI 기판의 실리콘-절연체-실리콘 스택의 상위 실리콘층) 위에 증착된 실리콘층의 패터닝 및 에칭을 이용하여 형성될 수 있다. 또 다른 실시예에 있어서, 핀 구조는 기판 위에 유전체층을 형성하고, 유전체층에서 트렌치를 개방하고, 핀을 형성하기 위해 트렌치 내에 기판으로부터 핀을 에피택셜 성장함으로써 형성된다.
개시된 실시예에 있어서, 분리 영역은 핀 구조(202)의 다양한 핀을 규정하고 전기적으로 분리하기 위해 기판(20) 내에 형성된다. 일례에서 분리 영역은 얇은 트렌치 분리(shallow trench isolation; STI) 영역(204)(204a와 204b 포함)을 포함한다. 분리 영역은 실리콘 산화물, 실리콘 질화물, 실리콘 산화질화물, 불화물-도핑 실리케이트 글래스(fluoride-doped silicate glass; FSG), 로우-k 유전체 물질, 및/또는 그 조합을 포함할 수 있다. 절연 영역은 개시된 실시예에 있어서, STI 영역(204)는 어떤 적합한 공정에 의해 형성될 수도 있다. 일례로서, STI 영역(204)의 형성은 (예를 들어 화학 기상 증착 공정을 사용하여) 핀 사이의 트렌치를 유전체 물질로 충진하는 것을 포함할 수 있다. 일부 실시예에 있어서, 충진된 트렌치는 실리콘 질화물 또는 실리콘 산화물로 충진된 열 산화물 라이너층와 같은 다층 구조를 가질 수 있다.
여전히 도 2를 참조하면, 게이트 스택(210)은 STI 영역(204) 사이에서 기판(20)의 주면(20s)[즉, 핀 구조(202)의 상면] 상에 형성된다. 게이트 스택(210)이 핀의 상면에만 연장하는 평면에서 도면에 도시되었지만, 당업자는 디바이스의 다른 평면에서(도시되지 않음) 게이트 스택(210)은 핀 구조(202)의 측벽을 따라 연장한다고 인지할 것이다. 일부 실시예에 있어서 게이트 스택(210)은 게이트 유전체층(212), 및 게이트 유전체층(212) 위의 게이트 전극층(214)을 포함한다. 일부 실시예에 있어서, 한 쌍의 측면 스페이서(216)가 게이트 스택(210)의 양측에 형성된다. 개시된 실시예에 있어서, 게이트 스택(210)은 여기에 설명된 공정을 포함하여 어떤 적합한 공정를 사용하여 형성될 수 있다.
일례에 있어서, 게이트 유전체층(212) 및 게이트 전극층(214)은 기판(20) 위에 순차적으로 증착된다. 일부 실시예에 있어서, 게이트 유전체층(212)은 실리콘 산화물, 실리콘 질화물, 실리콘 산화질화물, 또는 높은 유전 상수(하이-k) 유전체를 포함할 수 있다. 하이-k 유전체는 금속 산화물을 포함한다. 하이-k 유전체에 사용된 금속 산화물의 예로는 Li, Be, Mg, Ca, Sr, Sc, Y, Zr, Hf, Al, La, Ce, Pr, Nd, Sm, Eu, Gd, Tb, Dy, Ho, Er, Tm, Yb, Lu 및 그 혼합물의 산화물을 포함한다. 본 실시예에 있어서, 게이트 유전체층(212)은 약 10 옹스트롬 내지 약 30 옹스트롬의 범위 내의 두께를 갖는 하이-k 유전체층이다. 게이트 유전체층(212)은 원자층 증착(atomic layer deposition; ALD), 화학 기상 증착(chemical vapor deposition; CVD), 물리 기상 증착(physical vapor deposition; PVD), 열 산화, UV-오존 산화 또는 그들 조합과 같은 적합한 공정을 사용하여 형성될 수 있다. 게이트 유전체층(212)은 게이트 유전체층(212) 및 핀 구조(202) 사이의 손상을 감소하기 위해 계면층(도시되지 않음)을 더 포함할 수 있다. 계면층은 실리콘 산화물을 포함할 수 있다.
일부 실시예에 있어서, 게이트 전극층(214)은 단층 또는 다층 구조를 포함할 수 있다. 적어도 하나의 실시예에 있어서, 게이트 전극층(214)은 폴리실리콘을 포함한다. 또한, 게이트 전극층(214)은 균일한 또는 비균일한 도핑으로 폴리실리콘을 도핑할 수 있다. 대안의 실시예에 있어서, 게이트 전극층(214)은 W, Cu, Ti, Ag, Al, TiAl, TiAlN, TaC, TaCN, TaSiN, Mn, 및 Zr의 그룹으로부터 선택된 금속을 포함한다. 대안의 실시예에 있어서, 게이트 전극층(214)은 TiN, WN, TaN, 및 Ru의 그룹으로부터 선택된 금속을 포함한다. 본 실시예에 있어서, 게이트 전극층(214)은 약 60 나노미터 내지 약 30 나노미터의 범위 내의 두께를 포함한다. 게이트 전극층(214)은 ALD, CVD, PVD, 도금 또는 그들의 조합과 같은 적합한 공정을 사용하여 형성될 수 있다.
그 다음에, 포토레지스트층(도시되지 않음)이 스핀-온 코팅과 같은 적합한 공정에 의해 게이트 전극층(214) 위에 형성되고, 적당한 리소그래피 패터닝 방법에 의해 패터닝되어 패턴팅된 포토레지스트 피쳐를 형성한다. 적어도 하나의 실시예에 있어서, 패터닝된 포토레지스트 피쳐의 폭은 약 5 nm 내지 약 45 nm의 범위 내에 있다. 패터닝된 포토레지스트 피쳐는 게이트 스택(210)을 형성하기 위해 아래 놓인 층[즉, 게이트 전극층(214) 및 게이트 유전체층(212)]에 건식 에칭 공정을 사용하여 전사될 수 있다. 포토레지스트층은 이후에 박리될 수 있다.
여전히 도 2를 참조하면, 반도체 디바이스(200)는 게이트 스택(210) 및 기판(20)위에 형성되고 게이트 스택(210)의 측벽을 커버하는 유전체층을 더 포함한다. 유전체층은 실리콘 산화물, 실리콘 질화물 또는 실리콘 산화질화물을 포함할 수 있다. 유전체층은 단층 또는 다층 구조를 포함할 수 있다. 유전체층은 CVD, PVD, ALD 또는 다른 적합한 기술에 의해 형성될 수 있다. 유전체층은 약 5 nm 내지 약 15 nm의 범위 내의 두께를 포함한다. 그 다음에, 이방성 에칭이 게이트 스택(210)의 2개의 측면에 한쌍의 측벽 스페이서(216)를 형성하기 위해 유전체층에 수행된다.
도 3 및 도 1의 단계(102)를 참조하면, 핀 구조(202)의 부분들[그 위에 게이트 스택(210) 및 한 쌍의 측벽 스페이서(216)가 형성되는 부분 이외]은 게이트 스택(210)에 인접한 기판(20)의 주면(20s) 아래의 소스 및 드레인(S/D) 트렌치(206)(206a 및 206b를 포함함)를 형성하기 위해 리세스된다. 개시된 실시예에 있어서, S/D 트렌치(206) 각각은 게이트 스택(210)과 STI 영역(204) 중 하나의 사이에 있다. 이와 같이, S/D 트렌치(206a)는 게이트 스택 (206)에 인접하여 있는 반면, STI 영역(204a)은 게이트 스택(210)에 대향하는 S/D 트렌치(206a)의 측면에 배치된다. 이와 같이, S/D 트렌치(206b)는 게이트 스택(210)에 인접하여 있는 반면, STI 영역(204b)은 게이트 스택(210)에 대향하는 S/D 트렌치(206b)의 측면에 배치된다.
개시된 실시예에 있어서, 하드 마스크로서 게이트 스택(210)과 한 쌍의 측벽 스페이서(216)를 사용하여 S/D 트렌치(206)을 형성하도록 비보호되거나 노출된 기판(20)의 주면(20s)을 리세스하기 위해 바이어스된 에칭 공정이 수행된다. 하나의 실시예에 있어서, 에칭 공정은 약 1 mTorr 내지 약 1000 mTorr의 압력, 약 50 W 내지 약 1000 W의 전력, 약 20 V 내지 약 500 V의 바이어스 전압 하에 약 40 ℃ 내지 약 60 ℃의 온도에서 에칭 가스로 HBr 및/또는 Cl2를 사용하여 수행될 수 있다. 또한, 제공된 실시예에 있어서, 에칭 공정에서 사용된 바이어스 전압은 S/D 트렌치(206)를 위한 원하는 프로파일을 달성하기 위해 에칭 방향을 더 잘 제어할 수 있도록 조정될 수 있다.
도 4 및 도 1의 단계 104에 예시된 바와 같이, 기판(20)의 주면(20s) 아래의 S/D 트렌치(206)의 형성 이후에, 도 4의 구조는 S/D 트렌치(206)에서 변형 물질(208)을 에피 성장시킴으로써 생성되고, 여기서 변형 물질(208)의 격자 상수는 기판(20)의 격자 상수와 상이하다. 그러므로, 반도체 디바이스(200)의 채널 영역은 변형되거나 응력이 가해져 디바이스의 캐리어 이동성을 향상시킨다.
일부 실시예에 있어서, 변형 물질(208)은 Si, Ge, SiGe, SiC, SiP, 또는 III-V 반도체 물질을 포함한다. 개시된 실시예에 있어서, 사전 세정(pre-cleaning) 공정이 HF 또는 다른 적합한 솔루션으로 S/D 트렌치(206)을 세정하기 위해 수행될 수 있다. 그 다음에, 실리콘 게르마늄(SiGe)과 같은 변형 물질(208)은 S/D 트렌치(206)를 충진하기 위한 저압 CVD(LPCVD) 공정에 의해 선택적으로 성장된다. 하나의 실시예에 있어서, 변형 물질(208)의 상면은 주면(20s)(도시되지 않음)보다 낮다. 또 다른 실시예에 있어서, S/D 트렌치(206)를 충진한 변형 물질(208)은 주면(20s) 위에서 상향하여 연장된다. 개시된 실시예에 있어서, LPCVD 공정은 약 400 ℃ 내지 약 800 ℃의 온도에서 약 1 Torr 내지 약 15 Torr의 압력 하에 반응 가스로서 SiH2Cl2, HCl, GeH4, B2H6, 및 H2를 사용하여 수행한다.
이 시점까지의 공정 단계는 S/D 트렌치(206) 내에 변형 물질(208)을 갖는 기판(20)을 제공하고 있다. 일부 어플리케이션에 있어서, 변형 물질 (208)위의 실리사이드 영역은 니켈, 티타늄, 코발트 및 그 조합과 같은 금속 물질의 얇은 층을 증착하는 블랑켓으로 형성될 수 있다. 그 다음에, 기판(20)은 가열되어 실리콘이 접촉되는 금속에 반응하도록 한다. 반응 후에 금속 실리사이드의 층은 실리콘 함유 물질과 금속 사이에 형성된다. 비반응 금속은 금속 물질을 공격하지만 실리사이드는 공격하지 않는 에쳔트를 통하여 선택적으로 제거된다. 그러나, 금속 실리사이드와 변형 물질(208) 사이의 페르미 레벨 핀닝(Fermi level pinning)은 고정된 쇼트키 장벽 높이(Schottky barrier height; SBH)을 야기한다. 이 고정된 SBH는 반도체 디바이스의 S/D 영역의 높은 접촉 저항을 발생시켜 장치의 성능을 저하시킨다.
따라서, 도 5 내지 도 12를 참조하여 아래에 설명된 프로세싱은 실리사이드 영역을 대체하기위해 전도성 유전체층을 포함하는 접촉 구조를 형성할 수 있다. 전도성 유전체 층은 높은 저항 금속 실리사이드를 대체하기 위해 낮은 저항 중간층으로서 사용할 수 있다. 그와 같이, 접촉 구조는 반도체 장치의 S/D 영역의 낮은 접촉 저항을 제공할 수 있고, 따라서 디바이스의 성능을 향상시킨다.
반도체 디바이스 (200)의 접촉 구조[도 12에 나타낸 접촉 구조(230) 등]을 제조하는 도 5 및 도 6 과 도 1의 단계(106)에 예시된 바와 같이, 변형 물질(208),게이트 스택(210), 한 쌍의 스페이서 측면(216) 및 분리 영역(204) 위에 층간 유전체(ILD)층(218)을 형성함으로써 생성된다.
ILD층(218)은 유전체 물질을 포함한다. 유전체 물질은 실리콘 산화물, 실리콘 질화물, 실리콘 산화질화물, 포스포실리케이트 글래스(PSG), 보로포스포실리케이트 글라스 (BPSG), 스핀 온 글래스(SOG), 플루오리네이트 시리카 글래스(FSG), 탄소 도핑된 실리콘 산화물(예를 들어 SiCOH) 및/또는 그 조합을 포함할 수 있다. 일부 실시예에서, ILD층(218)은 CVD, 고밀도 플라즈마(HDP) CVD, 서브 대기CVD (SACVD), 스핀-온, 스퍼터링, 또는 다른 적합한 방법에 의해 변형 물질(208)을 위에 형성될 수 있다. 본 실시예에 있어서, ILD층(218)은 약 4000 Å 내지 약 8000 Å 내의 두께를 갖는다. ILD층(218)은 하나 이상의 유전체 물질 및/또는 하나 이상의 유전체층을 포함할 수 있다는 것이 이해된다.
ILD층(218)은 게이트 전극층(214)의 상면이 노출하거나 도달할 때까지 CMP 공정을 사용하여 평탄화된다(도 6에 나타냄). CMP 공정은 게이트 전극층(214)와 ILD층(218)에 대해 주로 평면 표면을 제공하도록 높은 선택성을 갖는다.
도 6의 반도체 디바이스(200)에 적용된 후속의 CMOS 프로세싱 단계는 ILD층(218)를 통해 접촉 개구부를 형성하여 반도체 디바이스(200)의 S/D 영역에 전기적 접촉을 제공하는 것을 포함한다. 도 7을 참조하면, 도 7의 구조는 변형 물질(208)의 일부를 노출하기 위해 ILD층(218)에서 개구부(220)를 형성함으로써 생성된다[도 1에서 단계(108)]. 일례로서, 개구부(220)의 형성은 ILD층(218) 위에 스핀 온 코팅과 같은 적합한 공정에 의해 포토레지스트의 층(도시되지 않음)을 형성하고, 적합한 리소그래피 방법에 의해 패터닝된 포토레지스터가 피쳐를 형성하도록 포토레지스터층을 패터닝하고, 변형 물질(208)의 일부를 노출하기 위해 제거하도록 노출된 ILD층(218)을 에칭(예를 들어, 건식 에칭, 습식 에칭 및/또는 플라즈마 에칭 공정을 사용함으로써)하는 것을 포함한다. 이와 같이, 개구부(220)는 변형 물질(208) 위에 있고, 여기서 개구부(220)는 변형 물질 저부(220b)와 유전체 측벽(220a)를 포함한다. 패터닝된 포토레지스트층은 이후 박리할 수 있다.
도 8 및 도 1의 단계(108)를 참조하면, ILD층(218) 내에 개구부(220)를 형성한 후에, 도 8의 구조는 개구부(220) 내부를 코팅하고 게이트 스택(210)과 ILD층(218) 위로 연장하는 제 1 금속 층(222)을 형성함으로써 생성된다. 일부 실시예에 있어서, 제 1 금속층 (222)는 Ti, Al, Zr, Hf, Ta, In, Ni, Be, Mg, Ca, Y, Ba, Sr, Sc, 또는 Ga를 포함할 수 있고 CVD, ALD 또는 스퍼터링과 같은 방법을 사용하여 있다. 일부 실시예에서는 제 1 금속층(222)은 약 1 nm 내지 약 4 nm 범위 내의 제 1 두께(T1)이 있다.
도 9 및 도 10과 도 1의 단계(112)를 참조하면, 제 1 금속층(222)의 형성에 후속하여 도 10의 구조가 변형 물질(208) 위에 유전체층(226)을 형성하기 위해 제 1 금속층(222)을 처리함으로써 생성된다. 개시된 실시예에 있어서, 제 1 금속 층(222)을 처리하는 단계는 먼저 약 1*10-10 Torr에서 약 760 Torr의 산소 압력 하에 에어 또는 밀봉 챔버와 같은 산소 함유 환경에 제 1 금속층(222)의 표면을 노출함으로써 수행되고, 결과적으로 블랭킷 흡착된 산소 함유 필름(blanket adsorbed oxygen-containing film)(224)을 제 1 금속층(222)의 표면 위에 형성한다(도 9에 나타냄). 일부 실시예에 있어서, 산소 함유 환경은 H2O, O2, 또는 O3을 포함한다.
산소 함유 환경에서 제 1 금속층(222)의 표면을 노출한 후에, 제 1 금속층(222)을 처리하는 단계는 약 200 ℃ 내지 800 ℃의 온도에서 제 1 금속층(222)의 표면을 비활성 가스에 노출하는 것을 더 포함한다. 일부 실시예에 있어서, 비활성 가스는 N2, He, 또는 Ar을 포함한다. 개시된 실시예에서 블랭킷 흡착된 산소 함유 필름(224)은 변형 물질(228) 위에 유전체층(226)을 형성하기 위해 접촉되는 제 1 금속층(222)과 반응한다. 일부 실시예에 있어서, 개구부(220)의 내부를 코팅하는 유전체층(226)은 코팅된 개구부(220a)를 형성한다.
일부 실시예에 있어서, 유전체층(226)은 약 1 nm 내지 약 10 nm의 범위 내에 있는 제 2 두께(t2)를 갖고, 이것은 유전체층(226)을 전도성으로 만든다. 이와 같이, 유전체층(226)은 이후 전도성 유전체층(226)이라 한다. 적어도 하나의 실시예에서, 전도성 유전체층(226)은 TiO, TiO2 또는 Ti2O3을 포함한다. 대안의 실시예에서 전도성 유전체층(226)은 Al2O3을 포함한다. 대안의 실시예에서 전도성 유전체층은 Zr, Hf, Ta, In, Ni, Be, Mg, Ca, Y, Ba, Sr, Sc, Ga, 및 그 혼합물로 구성된 그룹의 산화물로부터 선택된다. 개시된 실시예에서 전도성 유전체층(226)은 고정된 SBH를 감소시키고 고저항 금속 실리사이드를 대체하기 위해 저저항 중간층으로서 사용할 수 있고 디바이스의 성능을 향상시킨다.
도 11 및 도 12와 도 1의 단계(114)를 참조하면, 전도성 유전체층(226)의 형성은 전도성 유전체층(226)의 코팅된 개구부(220a) 내에 제 2 금속층(228)을 형성함으로써 생성된다. 개시된 실시예에 있어서, 제 2 금속층(228)은 전도성 유전체층(226)의 코팅된 개구부(220a)를 충진하기 위해 유전체층(226) 위에 증착된다. 일부 실시예에 있어서, 제 2 금속층(228)은 Ta, Ti, Hf, Zr, Ni, W, Co, Cu, 또는 Al을 포함한다. 일부 실시예에 있어서, 제 2 금속층(228)은 CVD, PVD, 도금, ALD 또는 다른 적합한 기술에 의해 형성될 수 있다. 일부 실시예에 있어서, 제 2 금속층(228)은 라미네이트를 포함할 수 있다. 라미네이트는 베리어 금속층, 라이너 금속층 또는 습윤 금속층을 더 포함할 수 있다. 또한, 제 2 금속층(228)의 두께는 코팅된 개구부(220a)의 깊이에 의존할 것이다. 그러므로, 제 2 금속층(228)은 코팅된 개구부(220a)가 거의 충진되거나 오버 충진될 때까지 증착된다.
그 다음에, 다른 CMP는 코팅된 개구부(220a)를 충진한 후에(도 12에 나타냄), 제 2 금속층(228)를 평면화하기 위해 수행된다. CMP가 코팅된 개구부(220a)의 외측의 제 2 금속층의 일부를 제거한 이후 CMP 공정은 ILD층(218)에 도달했을 때 정지할 수 있고, 그에 따라 실질적으로 평면의 표면을 제공한다.
일부 실시예에 있어서, 도 2 내지 도 12에 개시된 예에 관하여 반도체 디바이스(200)를 위한 접촉 구조(230)는 주면(20s) 및 주면(20s) 아래의 트렌치(206)를 포함한 기판(도 3 참조); 트렌치(206)를 충진하는 변형 물질(208) - 변형 물질(208)의 격자 상수는 기판(20)의 격자 상수와 상이함 -(도 4 참조); 변형 물질(208) 위의 개구부(220) - 개구부(220)는 유전체 측면(220a)과 변형 물질 저부(220b)를 포함 - 을 갖는 층간 유전체층(ILD)(218)(도 7 참조); 개구부(220)의 측벽(220a) 및 저부(220b)를 코팅하는 유전체층(226) - 유전체층(226)은 1 nm 내지 10 nm의 범위 내의 두께(t2)를 갖음 - (도 10 참조); 및 유전체층(226)의 코팅된 개구부(220a)를 충진하는 금속층(228)(도 12 참조)을 포함한다.
개시된 실시예에 있어서, 게이트 스택(210)은 게이트-퍼스트(gate-first) 공정을 사용하여 제조된다. 대안의 실시예에 있어서, 게이트 스택(210)은 더미 게이트 스택을 먼저 형성함으로써 수행되는 게이트-라스트(gate-last) 공정을 사용하여 제조될 수 있다. 일부 실시예에 있어서, 게이트-라스트 공정은 더미 게이트 스택을 둘러싸는 ILD층을 형성하는 단계, ILD층 내에 트렌치를 형성하기 위해 더미 게이트 전극층 제거하는 단계, 그 다음에 전도성 게이트 전극층으로 트렌치를 충진하는 단계를 포함한다. 일부 실시예에 있어서, 게이트-라스트 공정은 더미 게이트 스택을 둘러싸는 ILD층을 형성하는 단계, ILD층 내에 트렌치를 형성하기 위해 더미 게이트 전극층 및 더미 게이트 전극층을 제거하는 단계, 그 다음에 게이트 유전체층과 전도성 게이트 전극층으로 트렌치를 충진하는 단계를 포함한다.
도 2 내지 도 12에 도시된 예에 대하여 더 설명된 바와 같은 도 1에 나타낸 단계가 수행된 후에, 상호연결 프로세싱을 포함한 후속하는 프로세스가 반도체 디바이스(200) 제조를 완료하기 위해 수행된다. 전도성 유전체층(226)을 포함하는 접촉 구조(230)는 상호연결을 위한 저저항 경로를 제공함으로써 디바이스 성능을 개선한다는 것이 관찰되었다.
본 발명은 예시를 통해 바람직한 실시예의 측면에서 설명되었지만, 본 발명은 개시된 실시예에 한정되지 않음을 이해하여야 한다. 반대로, (당업자에게 명백해지는 바와 같이,) 다양한 수정 및 유사한 배치를 포함하도록 의도된다. 그러므로, 첨부된 청구항의 범위는 그러한 수정 및 유사한 배치를 모두 내포하기 위해서 가장 광범위한 해석을 따라야 한다.

Claims (10)

  1. 반도체 디바이스를 제조하는 방법에 있어서,
    주면(major surface) 및 상기 주면 아래의 트렌치를 포함하는 기판을 제공하는 단계;
    상기 트렌치 내에 변형 물질(strained material) - 상기 변형 물질의 격자 상수는 상기 기판의 격자 상수와 상이함 - 을 에피-성장시키는 단계;
    상기 변형 물질 위에 층간 유전체(inter-layer dielectric; ILD) 층을 형성하는 단계;
    상기 변형 물질의 부분을 노출하도록 상기 ILD 층 내에 개구부를 형성하는 단계;
    상기 개구부의 내부를 코팅하고 상기 ILD 층 위로 연장하는 제1 금속층을 형성하는 단계;
    상기 변형 물질 위에 전도성 유전체층을 형성하도록 상기 제1 금속층을 처리(treating)하는 단계; 및
    상기 전도성 유전체층의 코팅된 개구부 내에 제2 금속층을 형성하는 단계를 포함하고,
    상기 제1 금속층을 처리하는 단계는,
    상기 제1 금속층의 표면 상에 블랭킷 흡착된 산소 함유 필름(blanket adsorbed oxygen-containing film)을 형성하기 위해 상기 제1 금속층의 표면을 산소 함유 환경(oxygen-containing environment)에 노출시키는 단계와, 상기 제1 금속층과 상기 블랭킷 흡착된 산소 함유 필름을 반응시킴으로써 상기 전도성 유전체층을 형성하기 위해 상기 제1 금속층의 표면을 산소 함유 환경에 노출시킨 후에 상기 제1 금속층의 표면을 비활성 가스에 노출시키는 단계를 포함하는 것인, 반도체 디바이스를 제조하는 방법.
  2. 제 1 항에 있어서,
    상기 변형 물질은 Si, Ge, SiGe, SiC, SiP 또는 III-V 반도체 물질을 포함하는 것인, 반도체 디바이스를 제조하는 방법.
  3. 제 1 항에 있어서,
    상기 트렌치 내에 변형 물질을 에피-성장시키는 단계는, 상기 변형 물질이 상기 주면 위로 연장하는 것인, 반도체 디바이스를 제조하는 방법.
  4. 제 1 항에 있어서,
    상기 전도성 유전체층은 TiO, TiO2, 또는 Ti2O3을 포함하는 것인, 반도체 디바이스를 제조하는 방법.
  5. 제 1 항에 있어서,
    상기 전도성 유전체층은 Al2O3을 포함하는 것인, 반도체 디바이스를 제조하는 방법.
  6. 제 1 항에 있어서,
    상기 전도성 유전체층은 Zr, Hf, Ta, In, Ni, Be, Mg, Ca, Y, Ba, Sr, Sc, Ga, 및 그 혼합물들로 구성된 그룹의 산화물로부터 선택되는 것인, 반도체 디바이스를 제조하는 방법.
  7. 제 1 항에 있어서,
    상기 제2 금속층은 Ta, Ti, Hf, Zr, Ni, W, Co, Cu, 또는 Al을 포함하는 것인, 반도체 디바이스를 제조하는 방법.
  8. 제 1 항에 있어서, 상기 산소 함유 환경은 H2O 또는 O2를 포함하는 것인, 반도체 디바이스를 제조하는 방법.
  9. 제 1 항에 있어서,
    상기 비활성 가스는 N2, He 또는 Ar을 포함하는 것인, 반도체 디바이스를 제조하는 방법.
  10. 제 1 항에 있어서,
    상기 제1 금속층의 표면을 비활성 가스에 노출시키는 단계는 200 ℃ 내지 800 ℃ 의 온도에서 수행되는 것인, 반도체 디바이스를 제조하는 방법.
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