KR101325634B1 - Method for inspecting pcb of semiconductor packages - Google Patents

Method for inspecting pcb of semiconductor packages Download PDF

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Publication number
KR101325634B1
KR101325634B1 KR1020120048631A KR20120048631A KR101325634B1 KR 101325634 B1 KR101325634 B1 KR 101325634B1 KR 1020120048631 A KR1020120048631 A KR 1020120048631A KR 20120048631 A KR20120048631 A KR 20120048631A KR 101325634 B1 KR101325634 B1 KR 101325634B1
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KR
South Korea
Prior art keywords
mounting area
vision
pattern
circuit board
mounting
Prior art date
Application number
KR1020120048631A
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Korean (ko)
Inventor
정현권
지승용
이정균
Original Assignee
한미반도체 주식회사
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Publication date
Application filed by 한미반도체 주식회사 filed Critical 한미반도체 주식회사
Priority to KR1020120048631A priority Critical patent/KR101325634B1/en
Priority to CN201610172885.2A priority patent/CN105845594B/en
Priority to CN201310164735.3A priority patent/CN103426787B/en
Priority to TW102116432A priority patent/TWI516759B/en
Application granted granted Critical
Publication of KR101325634B1 publication Critical patent/KR101325634B1/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/67005—Apparatus not specifically provided for elsewhere
    • H01L21/67242—Apparatus for monitoring, sorting or marking
    • H01L21/67294—Apparatus for monitoring, sorting or marking using identification means, e.g. labels on substrates or labels on containers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
    • H01L22/10—Measuring as part of the manufacturing process
    • H01L22/12—Measuring as part of the manufacturing process for structural parameters, e.g. thickness, line width, refractive index, temperature, warp, bond strength, defects, optical inspection, electrical measurement of structural dimensions, metallurgic measurement of diffusions

Abstract

The present invention relates to a method of inspecting a printed circuit board for a semiconductor package and, more specifically, to a method of inspecting a printed circuit board for a semiconductor package capable of quickly inspecting defects within a mounting region of a printed circuit board and improving the accuracy when a pattern of the mounting region is photographed.

Description

Method for inspecting PCB of semiconductor packages

The present invention relates to a method for inspecting a circuit board for a semiconductor package, and more particularly, to a method for inspecting a semiconductor package circuit board that can quickly inspect a defect in a mounting area of a circuit board and improve the accuracy when photographing a pattern of the mounting area. It is about.

In general, a process for attaching a semiconductor chip to a circuit board must be performed very precisely, and a plurality of mounting regions where the semiconductor chip is fixed are provided on the substrate.

On the other hand, the semiconductor chip and the mounting region of the circuit board must be electrically connected accurately, and the semiconductor chip should be mounted on the precise position (pattern) of the mounting region in order to reduce the defect rate.

The semiconductor chip mounting process described above may be referred to as a bonding process. According to the specificity of the process requiring precise work, the semiconductor chip is mounted on the board after the inspection of the overall position of the circuit board and the position (mounting area) of the semiconductor chip fixing part of the circuit board is completed.

A plurality of mounting regions may be provided in a matrix shape on the circuit board, and a mark indicating whether the corresponding mounting region is defective may be displayed on the circuit board.

In an embodiment, each mounting area may be marked with a mark for detecting a defect through vision, and whether the mounting area is defective is inspected before mounting the semiconductor chip, and the mounting of the semiconductor chip is free of defects. Only in the mounting area.

Such a mark may be identified through vision, and the vision moves to the corresponding mounting area to check the marks of the plurality of mounting areas, and maintains the stopped state for photographing. That is, the vision repeats movement and stops as many as the number of mounting areas provided on the circuit board, and detects a defect.

Therefore, since the marks are taken in the stopped state in each mounting area, the inspection time of the circuit board is increased and the entire process is delayed.

In addition, after detecting whether the mounting area is defective, the vision position information of the circuit board and the position information of the semiconductor chip fixing part (mounting area) provided on the circuit board are obtained. The position of the circuit board can be determined through a plurality of reference coordinate points (for example, fiducial marks) formed on the circuit board, and the position information of the mounting area provided on the circuit board is corresponding to the mounting area. It can be obtained by photographing the pattern of.

Since the mounting process requires very high precision, the position information of all the semiconductor chip fixing parts must be accurately known. Therefore, the pattern inspection of the mounting area should be done very precisely.

Accordingly, there is a need for a method of inspecting a circuit board for a semiconductor package that can quickly and accurately perform a mark inspection for detecting a defect and a pattern inspection for obtaining position information of a mounting area.

An object of the present invention is to provide a method for inspecting a circuit board for a semiconductor package which can quickly inspect a defect in a mounting area of a circuit board.

In addition, an object of the present invention is to provide a method for inspecting a circuit board for a semiconductor package that can increase the accuracy in pattern imaging of a mounting area.

Another object of the present invention is to provide a method for inspecting a circuit board for a semiconductor package which can quickly and accurately perform defect inspection and pattern inspection of a circuit board before performing a flip chip bonding process.

In order to solve the above problems, according to an aspect of the present invention, (a) preparing a circuit board having a plurality of mounting areas in which a plurality of unit units cut from the wafer is mounted; and (b) the first mounting Photographing the presence or absence of a mark on the first mounting area to detect a defect in the process of moving the vision to the area; And (c) photographing a pattern of the first mounting area after stopping the vision at a reference position of the first mounting area based on whether the mark is detected. .

In addition, according to another aspect of the invention, (a) preparing a circuit board having a plurality of mounting area in which a plurality of unit units cut from the wafer is mounted; and (b) the edge portion of the first mounting area Moving the vision to a first reference position provided at the second reference position; and (c) photographing the first pattern of the first mounting area at the first reference position; And (d) photographing the presence or absence of a mark of the first mounting region in a process of moving the vision to a second reference position provided at another edge portion of the first mounting region. This is provided.

In addition, according to another aspect of the invention, (a) preparing a circuit board having a plurality of mounting area in which a plurality of unit units cut from the wafer is mounted; and (b) moving the vision to the first mounting area Photographing the presence or absence of the mark of the first mounting area in the process of making; and (c) stopping the vision at a reference position of the first mounting area based on whether the mark is detected; and (d) stopping the vision. Photographing the pattern of the first mounting area at least twice at predetermined time intervals after a signal is input; And (e) determining a pattern of the first mounting region based on the plurality of patterns photographed in step (d).

In addition, according to another aspect of the invention, (a) preparing a circuit board having a plurality of mounting area to be mounted a plurality of unit units cut from the wafer; and (b) the edge portion of the first mounting area Moving the vision to a first reference position provided in the vision; and (c) photographing the first pattern of the first mounting area at least twice at predetermined time intervals after a stop signal is input to the vision; and (d) photographing the presence or absence of a mark of the first mounting area in the process of moving the vision to a second reference position provided at another edge portion of the first mounting area; and (e) depending on whether the mark is present Moving the vision to a second reference position; and (f) photographing the second pattern of the first mounting area at least twice at predetermined time intervals after the stop signal is input to the vision; And (g) determining a pattern of the first mounting region based on the plurality of patterns photographed in steps (c) and (f).

As described above, according to the inspection method of the semiconductor package circuit board according to the embodiment of the present invention, it is possible to quickly inspect the defect of the mounting area of the circuit board.

In addition, according to the inspection method of the semiconductor package circuit board according to an embodiment of the present invention, it is possible to increase the accuracy during pattern imaging of the mounting area.

In addition, according to the inspection method of the semiconductor package circuit board according to an embodiment of the present invention, it is possible to quickly / accurately perform the defect inspection and pattern inspection of the circuit board before performing the flip chip bonding process.

1 is a schematic plan view of a flip chip bonding apparatus according to an embodiment of the present invention.
2 is a schematic side view of a bonding head in accordance with an embodiment of the present invention.
3 is a plan view of a circuit board according to an embodiment of the present invention.
Figure 4 is a plan view of a circuit board according to another embodiment of the present invention.
5 is a conceptual view illustrating a method of inspecting a circuit board for a semiconductor package according to an embodiment of the present invention.
6 is a conceptual diagram illustrating a method of inspecting a circuit board for a semiconductor package according to still another embodiment of the present invention.
7 is a conceptual view illustrating a pattern photographing method of a circuit board for a semiconductor package according to an embodiment of the present invention.

Hereinafter, a method of inspecting a circuit board for a semiconductor package according to an embodiment of the present invention will be described in detail with reference to the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS The accompanying drawings, which are included to provide a further understanding of the invention and are incorporated in and constitute a part of this application, illustrate embodiments of the invention and, together with the description, serve to explain the principles of the invention.

In addition, the same or corresponding components are denoted by the same reference numerals regardless of the reference numerals, and redundant description thereof will be omitted. For convenience of explanation, the size and shape of each constituent member shown may be exaggerated or reduced have.

On the other hand, terms including an ordinal number such as a first or a second may be used to describe various elements, but the constituent elements are not limited by the terms, and the terms may refer to a constituent element from another constituent element It is used only for the purpose of discrimination.

1 is a schematic plan view of a flip chip bonding apparatus according to an embodiment of the present invention, and FIG. 2 is a schematic side view of a bonding head related to an embodiment of the present invention.

The flip chip bonding process uses a sawing machine to hold each unit unit on a wafer cut into a plurality of unit units so that each unit is located at a reference bonding position (mounting area) on the printed circuit board. It is a process of mounting a unit.

In the flip chip bonding process, the step of holding the unit unit in such a manner that the upper surface of each unit unit is sucked by a flip-over picker, and the flip-over picker up and down so that the upper and lower surfaces of the unit unit are inverted An inversion step of rotating by 180 °, a transfer step of holding a unit unit held by the flip-over picker using a bonding picker and transferring the unit unit to the bonding picker, and moving the bonding picker to move the lower portion of the unit unit A flux coating step of immersing the unit unit in the flux so that the flux is applied to the surface; and checking the pickup position and the flux application state of the flux-coated unit unit; and moving the bonding picker to the bonding unit to bond the unit. The method may include a bonding step of mounting the unit unit at a reference bonding position on a circuit board mounted on the circuit board.

Hereinafter, each component of the flipping bonding apparatus 1000 according to the present invention will be described in detail with reference to the accompanying drawings.

1 and 2, the flip chip bonding apparatus 1000 according to the present invention includes a wafer supply unit 100 for supplying a wafer W, and a wafer W supplied from the wafer supply unit 100. A wafer portion 200 provided, a flipover picker 300 gripping each unit unit U cut into a plurality of unit units from the wafer W provided in the wafer portion 200, an X axis, A bonding head 400 that is movable in the Y-axis and the Z-axis, rotatable at an angle θ about the Z-axis, and receives and grips each unit unit U from the flip-over picker 300; A flux unit 510 containing a flux f to be applied to the lower surface of each unit unit U held by the bonding picker by moving the head 400, and the flux f is applied to the lower surface. A bonding unit 700 on which a printed circuit board (PCB) on which each unit unit (U) is to be mounted is disposed, the flipover picker (300), and the bonding DE 400 and a control unit for controlling the flux portion (510). In addition, the bonding head 400 may include a bonding picker holding a unit unit whose upper and lower surfaces are inverted by the flipover picker and a first vision provided at a predetermined distance from the bonding picker in a lateral direction. .

In addition, the flip chip bonding apparatus 1000 may include at least one or more alignment information providing units 520 including a fiducial mark, and the alignment information providing unit may be provided in the bonding head 400. The location information of the fiducial mark FM may be provided to the first vision 430. The alignment information providing unit may include the devices included in the flip chip bonding apparatus 1000 (eg, the flipover picker 300, the bonding head 400, the flux unit 510, the bonding unit 700, and the wafer). When the relative position is changed due to thermal deformation or vibration due to the repeated process of the unit 200, the wafer supply unit 100, the rail, etc., the degree of relative position of each device is changed (that is, the change distance and the change direction). Information can be provided. In particular, among the components of the flip chip bonding apparatus 100, the bonding head 400 is moved by a gantry structure as shown in FIG. 1, so that heat is generated by a motor for driving and heat of the bonding head 400 is caused by heat. It is important to check the degree of distortion during the process, and to correct the distortion, because errors in the setting are likely to occur.

On the other hand, the bonding head 400 is installed to be elevated on the wafer portion 200 and the flip-over picker 300, the wafer portion 200, the bonding portion 700, the flux portion 510 and the flip-over picker Translation between the 300 is installed to be movable. Specifically, the bonding head 400 is installed to be able to translate in the X-axis direction along the first rail as shown in FIG. 1, and is installed to be translateable to the Y-axis along the second rail. For reference, a wafer portion 200, a flux portion 510, a bonding portion 700, and a flipover picker 300 are disposed in a space formed by the first rail and the second rail.

The bonding picker 410 directly transfers a vacuum suction force to the unit unit U to hold the suction head 411 and the suction head 411 and the bonding head 400 main body. And a connection member 415 for transmitting a vacuum suction input to the suction head 411. The suction head 411 is configured to rotate the gripped unit unit U clockwise and / or counterclockwise with respect to the Z axis. Thus, the suction head 411 can correct the position of the unit by theta under the control of the controller.

The first vision 430 is spaced apart from the bonding picker 410 in one direction (for example, in the Y-axis direction as shown in FIG. 2) in the bonding head 400 by a predetermined first distance. do. In order to prevent spatial interference with the first vision 430 when the bonding picker 410 grips the unit unit or immerses the unit unit U in the flux f, the first vision 430 may not occur. The lens surface of the first vision 430 may be installed at a position higher than that of the suction head 411 of the bonding picker 410.

The first vision 430 obtains the position information of the fiducial mark FM from at least one alignment information providing unit, obtains the position information of each unit unit from the wafer W, and the bonding unit 700. ) Obtains the position information of the reference bonding position in which each unit unit is to be mounted on the circuit board (PCB). In this way, the position information obtained through the first vision 430 is transmitted to the control unit, the control unit calculates the position information to move the bonding head 400 and / or bonding picker 410 to the position of the unit unit Execute X-axis correction and Y-axis correction.

In addition, on the movement path of the bonding head 400 between the flux unit 510 and the bonding unit 700, the adsorption head 411 of the bonding picker 410 in the upper direction from the lower side of the bonding picker 410 and A second vision 530 for photographing the unit unit may be provided.

The second vision 530 is a camera that collects position information of the unit unit with respect to the bonding picker 410 and state information of the flux applied to the lower surface of the unit unit U. Specifically, the second vision 530. ) Indicates whether the center of the adsorption head 411 of the bonding picker 410 coincides with the center of the unit, the distance at which the center of the adsorption head 411 of the bonding picker 410 is separated from the center of the unit, and the bonding picker The detached angle of the unit unit with respect to the adsorption head 411 of 410 and whether the flux is immersed in the unit unit picked up by the bonding picker 410 is photographed.

In the bonding part 700, a circuit board (PCB) on which a unit unit is mounted is disposed.

In addition, the front part of the bonding part 700 may be provided with a pre-alignment unit 600 for inspecting the position alignment information of the circuit board (PCB) in advance. The pre-aligner unit 600 may be provided with a third vision 610, and the third vision 610 collects and inspects the position information and the printed circuit state of each circuit board (PCB), and prints. The circuit board PCB collects location information on a reference bonding position, which is a position where the unit units U are to be mounted.

In addition, the controller controls the flipover picker 300, the bonding head 400, and the flux unit 510. In particular, the control unit is based on the position information obtained through the first vision 430, the second vision 530, the third vision 610, the reference bonding position of the circuit board (PCB) in the bonding unit 700 ( Correct the position of the unit unit with respect to the mounting area. That is, the controller performs X axis correction, Y axis correction, and theta (θ) correction on the position of the unit based on the position information of the first vision 430, the second vision 530, and the third vision 610. Run

At the same time, the controller adjusts the reference coordinates of the bonding picker with respect to the reference bonding position of the circuit board PCB based on the position information of the alignment information providing unit obtained by the first vision 430. That is, the controller is based on the position information of the at least one alignment information providing unit obtained through the first vision 430, each device (eg, flip-over picker ( 300, the bonding head 400, the flux unit 510, the bonding unit 700, the wafer unit 200, the wafer supply unit 100, the rail, etc.) if the heat is deformed due to the repeated process its twisted degree ( The position of the reference bonding region of the circuit board PCB is accurately calculated by calculating an error value), and the position of the unit unit is corrected by adjusting the reference coordinates of the pickers during bonding.

 The control unit controls the flipover picker to return to the predetermined position O at the top of the wafer unit after the flipover picker grips the unit unit. That is, the controller controls the flipover picker so that the process of transferring the flipped over unit from the flipover picker to the bonding picker is always performed at the preset position (O). The preset position is a point at which the flip-over picker transfers the inverted unit to the bonding picker.

In the method of inspecting a circuit board for a semiconductor package according to an embodiment of the present invention, a defect of a mounting region (bonding position described above) can be quickly inspected, and the failure detection of such a mounting region can be performed by the first vision 430 or the above-described vision. It may be performed through the third vision 610. In addition, as described above, the bonding process is performed only in the mounting area without defect.

In addition, the defect inspection may be performed in the prealignment unit 600, or may be performed before the bonding process in the bonding unit 700 by omitting the prealignment unit 600. Hereinafter, for convenience of description, the first vision 430 or the third vision 610 is referred to as a vision, and the defect inspection and the pattern inspection for acquiring position information of each mounting area may be performed by the pre-alignment unit 600 or bonding. It is to be performed in the unit 700.

According to an embodiment of the present invention, a method of inspecting a circuit board for a semiconductor package may include: (a) preparing a circuit board (PCB) having a plurality of mounting regions in which a plurality of unit units cut from the wafer (W) are mounted; (b) photographing a mark of the first mounting area to detect a defect in the process of moving the vision to the first mounting area; and (c) referring to the vision of the first mounting area based on whether or not the mark is detected. Photographing the pattern of the first mounting area after stopping at the position.

According to the present invention, since the mounting area is photographed during the movement of the vision without stopping the vision in order to check the mark of the mounting area, the inspection time can be shortened because it is not necessary to stop the number of mounting areas to photograph the mark. have.

In addition, when the mark is not detected, after stopping the vision at a reference position of the corresponding mounting area, pattern photography is performed to accurately acquire position information of the corresponding mounting area. The reference position may be position information of the corresponding mounting area provided from the alignment information providing unit as described above, and may be a position at which the pattern of the mounting area may be photographed in consideration of the vision field of vision. Therefore, the photographing point for identifying the mark may be determined according to the vision range of the vision before reaching the reference position of the corresponding mounting area. In addition, shooting the mark does not require accurate accuracy, unlike shooting a pattern, and corresponds to a mark inspection for identifying whether a mounting area is defective. Therefore, the shooting of the mark is not subject to vibration and shaking due to shooting while moving the vision. Techniques for shooting while on the move can be applied.

Meanwhile, when a mark is detected in the corresponding mounting area, the mark of another mounting area may be continuously taken while moving to another mounting area adjacent to the mounting area without stopping the vision at a reference position of the mounting area. .

That is, since the vision is stopped only in the mounting area where the mark is not displayed among the plurality of mounting areas, the patterning of the corresponding mounting area is performed, thereby reducing the inspection time.

On the other hand, the step of photographing the mark is preferably inspected using photometry, it is a matter of course that can be irradiated various light sources such as direct light or metering according to the position of the mark.

3 is a plan view of a circuit board according to an embodiment of the present invention, and FIG. 4 is a plan view of a circuit board according to another embodiment of the present invention.

Referring to FIG. 3, the circuit board 10 may have a matrix shape in which a plurality of mounting regions 11, 12, and 13 are arranged in predetermined rows and columns. In one embodiment, the mounting regions may be provided as 12 × 12. Can be. In this case, each of the mounting regions 11, 12, and 13 is inspected for short and / or abnormal shapes of the conductive circuit pattern, and then a bad mark is provided by ink, and the bad mark is provided as a mark having various shapes.

As shown in FIG. 3, marks may be displayed on the first to third mounting areas 11, 12, and 13, respectively, depending on whether the mark is defective. For example, the first of the circuit board 10 shown in FIG. When the third mounting area 13 is defective based on the first row, the “X” mark may be displayed on the third mounting area 13.

In the circuit board 10 having such a structure, in order to check whether each of the mounting regions 11 to 13 is defective, it is necessary to check whether the mounting regions 11 to 13 are marked with the above-described vision. Of course, only 11 to 12 are shown in the drawings, but inspection of the entire mounting area should be performed.

Referring to FIG. 4, the circuit board 20 may have a matrix shape in which a plurality of mounting areas 21 to 25 are arranged in predetermined rows and columns, and in one embodiment, the mounting areas may be provided as 5 × 5. . In this case, the circuit board 20 is provided with a bad mark by inspecting the short and / or the abnormal shape of the conductive circuit pattern and the abnormal shape of the conductive circuit pattern, the bad mark may be provided as a mark of various shapes, the mark is The circuit board 20 may not be displayed in the mounting area, and the circuit board 20 may include a defect display unit 26 provided in a separate space such as a left side or a right side.

For example, as shown in FIG. 4, based on the first row of the circuit board 20 of FIG. 4, the third mounting area 23 of the first to fifth mounting areas 21 to 25 is shown. In this case, the defective display unit 26 may be provided in a number corresponding to the number of mounting regions belonging to the corresponding row, and the defective display unit 26 may have a circular number corresponding to the number of mounting regions belonging to the corresponding row. It may be a metal pad.

In the circuit board 20 having such a structure, in order to check whether the mounting areas 21 to 25 belonging to the corresponding row are defective, the defective display unit (21 to 25) is not photographed through vision. It is possible to detect whether the mounting areas 21 to 25 belonging to the corresponding row are defective by only photographing 26.

5 is a conceptual diagram illustrating a method of inspecting a circuit board for a semiconductor package according to an exemplary embodiment of the present invention.

The circuit board 30 may have a matrix shape in which a plurality of mounting areas 31 to 33 are arranged in predetermined rows and columns. For example, the circuit board 30 may include first to third mounting areas 31. 33) may be provided, and a mark is displayed on the defective second mounting area 32.

As described above, the method for inspecting a circuit board for a semiconductor package includes (a) preparing a circuit board (PCB) having a plurality of mounting regions in which a plurality of unit units cut from the wafer (W) are mounted; Photographing a mark of the first mounting area to detect a defect in the process of moving the vision to the mounting area; and (c) stopping the vision at a reference position of the first mounting area based on whether the mark is detected or not. And photographing a pattern of the first mounting area, and in step (c), when a mark is detected in the first mounting area, the vision is not stopped at a reference position of the first mounting area. The marks of the second mounting area may be continuously photographed while moving to the adjacent second mounting area.

1 and 5, a circuit board 30 having a plurality of mounting regions 31 to 33 on which a plurality of unit units cut from the wafer W is mounted is provided, and the circuit board 30 of the circuit board 30 is provided. Mark inspection and / or pattern photographing may be performed by the pre-aligner unit 600 or the bonding unit 700 described above.

The vision 430 captures a mark of the first mounting area 31 for detecting a failure while moving from the initial position P1 to the first mounting area 31. In this case, as described above, the position P2 for photographing the mark may be a position before the vision 430 reaches the reference position P3 of the first mounting area 31, and the field of view of the vision 430 is used. The position P2 may be variously determined in consideration of the range and the like.

As shown in FIG. 5, since the mark is not displayed in the first mounting area 31, the mark may not be detected by photographing the vision 430. Therefore, since the first mounting area 31 is determined not to be defective, pattern imaging is performed to acquire accurate position information of the first mounting area 31. In this case, the vision 430 stops at the reference position P3 of the first mounting area 31, and photographs the pattern of the first mounting area 31. A specific method of photographing the pattern will be described later through another embodiment.

In addition, when pattern photographing is completed in the first mounting area 31, the vision 430 moves to the second mounting area 32, and the vision 430 is a reference position of the first mounting area 31. In the process of moving to the reference position of the second mounting area 32 at P3, the mark of the second mounting area 32 for detecting a defect is taken. In this case, as described above, the position P4 of photographing the mark may be a position before the vision 430 reaches the reference position of the second mounting area 32.

In this case, when a mark is detected in the second mounting area 32, the second mounting area 32 is determined to be defective, and since the unit unit does not need to be mounted, the vision 430 may be replaced with the second mounting area ( It is possible to continuously photograph the marks of the third mounting region 33 while moving to the third mounting region 33 adjacent to the second mounting region 32 without stopping at the reference position of 32). As described above, the position P5 of capturing the mark may be a position before the vision 430 reaches the reference position P6 of the third mounting area 33.

In addition, since the mark is not displayed in the third mounting area 33, the mark will not be detected by the photographing of the vision 430. Accordingly, since the third mounting area 33 is determined to be not defective, pattern imaging is performed to acquire accurate position information of the third mounting area 33. In this case, the vision 430 stops at the reference position P6 of the third mounting region 33, and photographs the pattern of the third mounting region 33.

As described above, since the vision 430 does not stop in the process of photographing the mark to determine whether the defect is defective, the vision 430 is stopped for pattern shooting only in the mounting area 430 that is not the defective, so the defect inspection and the pattern shooting are performed. It has the effect of shortening the time for.

6 is a conceptual diagram illustrating a method of inspecting a circuit board for a semiconductor package according to still another embodiment of the present invention.

Referring to FIG. 6, a method of inspecting a circuit board for a semiconductor package according to still another embodiment of the present disclosure may include: (a) preparing a circuit board having a plurality of mounting regions in which a plurality of unit units cut from a wafer are mounted. (B) moving the vision to a first reference position provided at an edge portion of the first mounting area; (c) photographing a first pattern of the first mounting area at the first reference position; and (d) And photographing a mark of the first mounting area in a process of moving the vision to a second reference position provided at another edge portion of the first mounting area.

In step (d), if the mark is not detected, stopping the vision at a second reference position of the first mounting region and photographing the second pattern of the first mounting region at the second reference position. Alternatively, in step (d), when the mark is detected, the first mounting area adjacent to the first mounting area may be stopped without stopping the vision at a second reference position of the first mounting area. The method may further include moving to a reference position.

As a method of photographing a pattern of a mounting area, a method of photographing the entire pattern of the mounting area may be used when the field of view is wide according to the vision field of view, and a method of capturing a plurality of partial patterns of the mounting area when the field of view is narrow. This can be used. In the embodiment described with reference to FIG. 5, a method of photographing an entire pattern is applied, and a method of photographing a partial pattern is applied to FIG. 6.

1 and 6, a circuit board having a plurality of mounting regions 41 to 43 in which a plurality of unit units cut from the wafer W are mounted is prepared, and the mark inspection and the pattern photographing are described in the above-mentioned pre-la. It may be made in the phosphor part 600 or the bonding part 700.

In this case, in order to photograph the entire pattern of one mounting area, at least two edge portions of the corresponding mounting area are photographed for partial patterns (first and second patterns for convenience). Accordingly, the vision 430 is moved to the first reference position P1 provided at the edge portion 41a of the first mounting region 41 and then the first mounting region 41 at the first reference position P1. 1st pattern is taken.

Thereafter, the mark of the first mounting area 41 is captured in the process of moving the vision 430 to the second reference position P3 provided at another edge portion 41b of the first mounting area 41. . The position P2 of the vision 430 for capturing the presence or absence of the mark may be a movement path of the vision between the first reference position P1 and the second reference position P3 of the first mounting area 41. . The first reference position P1 and the second reference position P3 may be positioned along the diagonal direction of the first mounting area 41, respectively.

Since the mark is not displayed in the first mounting area 41, the mark of the first mounting area 41 is not detected through the vision 430, so the first mounting area 41 is determined to be not defective. In order to capture the remaining second pattern, the vision 430 is moved to the second reference position 41b of the first mounting area 41, and the vision is moved to the second reference position of the first mounting area 41. Stopping at P3) and photographing the second pattern of the first mounting area 41 at the second reference position P3. A detailed method of photographing each pattern will be described later.

The vision 430 is moved to the first reference position P4 provided at the edge portion 42a of the second mounting region 42, and the first pattern is photographed at the first reference position P4 of the second mounting region 42. do.

Subsequently, in the process of moving from the first reference position P4 of the second mounting region P2 to the second reference position provided at the other edge portion 42b, the defect inspection of the second mounting region 42 is performed. In this case, since the mark is displayed in the second mounting area 42, the mark is detected through the vision 430. When the mark is detected, the second mounting area 42 is determined to be inferior and the mounting of the unit unit is not performed, so the vision 430 is connected to another edge portion 43b of the second mounting area 42. It is not moved to the prepared second reference position but is moved to the third mounting area 43 adjacent to the second mounting area 42.

In the third mounting area 43, similarly to the other mounting areas 41, the first pattern is taken at the first reference position P6 provided in the edge portion 43a, and the first reference position P6 is taken. In the process of moving to the second reference position (P8) to take a picture for confirming the presence of the mark.

In this case, since the mark is not displayed in the third mounting area 43, the vision is shifted to the second reference position P8 and the second pattern is photographed. The photographing position P7 for confirming the presence or absence of the mark may be provided on a movement path of the vision 430 formed between the first reference position P6 and the second reference position.

As described above, even in the process of photographing the partial pattern, a mark is taken to detect the presence of a defect without stopping the vision in the middle of photographing the first pattern and the second pattern, thereby reducing the inspection time.

On the other hand, in the case of the circuit board 20 shown in FIG. 4, the defect display unit 26 is displayed on one side. In the circuit board 20 having such a structure, the mark inspection of the entire mounting area and the pattern inspection of the mounting area are performed. Each may be performed in turn. In detail, the vision display unit 26 may photograph the defective display units 26 while the vision continuously moves, and whether or not the mounting regions acquired from the defective display units 26 are defective may be input to the controller. Then, when the photographing of the defective display units 26 is completed without stopping the vision, the controller moves the vision only to the non-defective mounting areas and photographs the pattern of each mounting area. After the time stop signal is input, the pattern may be photographed at least two times at predetermined time intervals, and an accurate pattern of the mounting area may be determined through an average of the plurality of patterns. For example, since the third mounting area 23 is defective based on the first row of the circuit board 20 shown in FIG. 4, the vision is the first mounting area 21 and the second mounting area 22. After photographing a pattern of, the patterns of the fourth mounting region 24 and the fifth mounting region 25 can be photographed in sequence without stopping in the third mounting region. Therefore, in the mark photographing step for detecting a defect, the vision is completed without continuous shooting, and in the step of capturing a pattern, only the pattern of the mounting area, not the defect, can be photographed sequentially, thereby effectively reducing the inspection time. .

7 is a conceptual view illustrating a pattern photographing method of a circuit board for a semiconductor package according to an embodiment of the present invention.

5 and 7, a method of inspecting a circuit board for a semiconductor package according to still another embodiment of the present invention includes (a) a circuit board having a plurality of mounting regions in which a plurality of unit units cut from a wafer are mounted. (B) photographing the mark of the first mounting area in the process of preparing and (b) moving the vision to the first mounting area, and (c) the reference position of the first mounting area based on whether the mark is detected or not. And (d) photographing the pattern of the first mounting area at least two times at predetermined time intervals after the stop signal is input to the vision, and (e) the plurality of images photographed in step (d). And determining a pattern of the first mounting area based on the pattern.

The photographing method of the pattern related to the present exemplary embodiment may be continuously performed with the aforementioned mark inspection method, and may be continuously performed with the mark inspection method described with reference to FIG. 5.

As described with reference to FIG. 5, when a mark is not detected in the corresponding mounting area, pattern photographing of the corresponding mounting area is performed.

Referring to FIG. 7, when the stop signal is input to the vision 430, and the vision 430 stops at the first reference position R1, the bonding head is moved according to a gantry type or a linear motor. Fine vibrations are also generated in the provided vision 430. Therefore, a vibration having a predetermined amplitude d occurs at the original position, and the position of the vision 430 is finely moved. In this case, when the photographing signal is input from the above-described control unit, the pattern photographing of the corresponding mounting area 51 is performed at unintended positions R2 and R3. In this case, since the pattern of the mounting area 51 is not captured correctly, the positional information of the mounting area is not obtained correctly. In particular, in a flip chip bonding apparatus requiring a precision of several micrometers, the defect rate is increased when the bonding process is performed based on the location information having such a small error.

Accordingly, in order to reduce the error and reduce the acquisition time of the location information of the corresponding mounting area, at least two patterns of the corresponding mounting area 51 are applied at predetermined time intervals (cycles) after a stop signal is input to the vision 430. Location information is obtained by calculating an average value of the photographed values by photographing more than once.

On the other hand, the vibration of the vision 430 becomes smaller over time, and accordingly the amplitude becomes smaller. Therefore, the pattern of the mounting area 51 will have data converged to a specific value, and the more the number of photographing times, the more accurate a value can be obtained. Preferably, the number of photographing times may be set in advance for the accuracy of the measurement, and the user may measure the number of times arbitrarily determined during the measurement. In this case, the pattern of the mounting area 51 may be determined based on the average of the plurality of photographed patterns. On the other hand, the pattern may be photographed at least two times after a predetermined time elapses after the stop signal is input to the vision 430. In this case, the predetermined time indicates a section in which the vibration of the vision 430 may fall below an allowable amplitude after the stop signal is input to the vision 430.

Similarly, after the stop signal is input to the vision 430, the vibration of the vision 430 is sensed, and when the vibration of the vision 430 enters a section that is below an allowable amplitude, at least two times or more. Can be photographed.

On the other hand, in the case of averaging, a pattern having a large error may not be added to the average. Specifically, the average of the plurality of measurement pattern position values is calculated and determined. At this time, a large error among the plurality of measurement position values may cause a position value having low reliability. Therefore, removing the measured value with low reliability and calculating the average can increase the reliability of the error.

Accordingly, the standard deviation of each measurement position value is calculated through the average of the plurality of measurement position values, and when the calculated standard deviation exceeds the set value, the position value having a large deviation is removed as an invalid value. By repeating this procedure, the standard deviation can be reduced to an effective level.

In addition, as described above, the reference position of each mounting area may be confirmed by checking the fiducial mark of the circuit board 50, and may be transmitted from the alignment information providing unit.

According to this method, whether or not the corresponding mounting area is defective can be performed quickly without stopping the vision, and the pattern can be captured more precisely.

According to another aspect of the present invention, a method of inspecting a circuit board for a semiconductor package includes (a) preparing a circuit board having a plurality of mounting regions in which a plurality of unit units cut from a wafer are to be mounted; (C) moving the vision to a first reference position provided at an edge of the first mounting area; and (c) at least two or more first patterns of the first mounting area at predetermined time intervals after a stop signal is input to the vision. (C) photographing a mark of the first mounting area in a process of photographing and (d) moving the vision to a second reference position provided at another edge of the first mounting area; and (e) whether or not the mark is present. Moving the vision to a second reference position; (f) photographing the second pattern of the first mounting area at least twice at predetermined time intervals after a stop signal is input to the vision; and (g ) Step (c) and and determining a pattern of the first mounting area based on the plurality of patterns photographed in (f).

The image capturing method according to the present exemplary embodiment may be performed in association with the mark inspection method of the circuit board described with reference to FIG. 6. That is, the method relates to a method of identifying the entire pattern of the mounting area through the partial pattern, and to a method of photographing the partial pattern.

It is the same as the mark inspection method described with reference to FIG. 6 except that the first pattern of the first mounting area is applied at least twice at predetermined time intervals after a stop signal is input to the vision when the first pattern is taken at the first reference position. Photographing the second pattern at the second reference position and photographing the second pattern of the first mounting area at least two times at a predetermined time interval after the stop signal is input to the vision.

In addition, the first pattern and the second pattern of the first mounting area are determined as the average of the patterns.

In addition, the method of determining the pattern of the first mounting area based on the plurality of patterns is the same as the embodiment described with reference to FIG. 7, and overlapping descriptions thereof will be omitted.

As described above, according to the inspection method of the semiconductor package circuit board according to the embodiment of the present invention, it is possible to quickly inspect the defect of the mounting area of the circuit board.

In addition, according to the inspection method of the semiconductor package circuit board according to an embodiment of the present invention, it is possible to increase the accuracy during pattern imaging of the mounting area.

In addition, according to the inspection method of the semiconductor package circuit board according to an embodiment of the present invention, it is possible to quickly / accurately perform the defect inspection and pattern inspection of the circuit board before performing the flip chip bonding process.

The foregoing description of the preferred embodiments of the present invention has been presented for purposes of illustration and various modifications, additions and substitutions are possible, without departing from the scope and spirit of the invention, And additions should be considered as falling within the scope of the following claims.

W: Wafer
PCB: Circuit Board
100: wafer supply unit
200: wafer portion
300: flipover picker
400: bonding head
410: Bonding Picker
411: adsorption head
430 first vision
1000: flip chip bonding device

Claims (10)

delete delete delete (a) preparing a circuit board having a plurality of mounting regions in which a plurality of unit units cut from the wafer are mounted;
(b) moving the vision to a first reference position provided at an edge portion of the first mounting area;
(c) photographing a first pattern of a first mounting area at the first reference position;
(d) photographing the presence or absence of a mark of the first mounting area in a process of moving the vision to a second reference position provided at another edge portion of the first mounting area; And
If the mark is not detected in step (d), stopping the vision at a second reference position of the first mounting area and photographing the second pattern of the first mounting area at the second reference position. Inspection method of circuit board for semiconductor package. (a) preparing a circuit board having a plurality of mounting regions in which a plurality of unit units cut from the wafer are mounted;
(b) moving the vision to a first reference position provided at an edge portion of the first mounting area;
(c) photographing a first pattern of a first mounting area at the first reference position;
(d) photographing the presence or absence of a mark of the first mounting area in a process of moving the vision to a second reference position provided at another edge portion of the first mounting area; And
If the mark is detected in step (d), moving the vision to a first reference position of a second mounting region adjacent to the first mounting region without stopping the vision at a second reference position of the first mounting region; Inspection method of circuit board for semiconductor package. (a) preparing a circuit board having a plurality of mounting regions in which a plurality of unit units cut from the wafer are mounted;
(b) photographing the presence or absence of the mark of the first mounting area in the process of moving the vision to the first mounting area;
(c) stopping the vision at a reference position of the first mounting area based on whether the mark is detected;
(d) photographing the pattern of the first mounting area at least twice at a predetermined time interval after the stop signal is input to the vision; And
(e) determining a pattern of the first mounting region based on the plurality of patterns photographed in step (d). The method according to claim 6,
In step (e), the pattern of the first mounting region is determined by the average of the plurality of patterns. The method according to claim 6,
In step (a), further comprising the step of confirming the reference position of each mounting area by checking the physical marks of the circuit board. (a) preparing a circuit board having a plurality of mounting regions in which a plurality of unit units cut from the wafer are to be mounted;
(b) moving the vision to a first reference position provided at an edge portion of the first mounting area;
(c) photographing the first pattern of the first mounting area at least twice at a predetermined time interval after the stop signal is input to the vision;
(d) photographing the presence or absence of a mark of the first mounting area in a process of moving the vision to a second reference position provided at another edge portion of the first mounting area;
(e) moving the vision to a second reference position according to the presence or absence of the mark;
(f) photographing the second pattern of the first mounting area at least twice at predetermined time intervals after the stop signal is input to the vision; And
(g) determining a pattern of the first mounting region based on the plurality of patterns photographed in steps (c) and (f). The method of claim 9,
In step (g), the first pattern and the second pattern of the first mounting area are respectively determined as the average of the plurality of patterns, the inspection method for a semiconductor package circuit board.
KR1020120048631A 2012-05-08 2012-05-08 Method for inspecting pcb of semiconductor packages KR101325634B1 (en)

Priority Applications (4)

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KR1020120048631A KR101325634B1 (en) 2012-05-08 2012-05-08 Method for inspecting pcb of semiconductor packages
CN201610172885.2A CN105845594B (en) 2012-05-08 2013-05-07 The method for checking the printed circuit board of semiconductor packages
CN201310164735.3A CN103426787B (en) 2012-05-08 2013-05-07 Check the method for the printed circuit board (PCB) of semiconductor packages
TW102116432A TWI516759B (en) 2012-05-08 2013-05-08 Method of inspecting printed circuit board for semiconductor package

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